Raja Bandi

Director,
Lucid VLSI
M: +91 994 995 4576
Email: raja@lucidvlsi.com

Verilog HDL
1. Write Verilog DUT which counts upto 7 and then down to 0 and repeats for ever
as follows.

0,1,2,3,4,5,6,7,6,5,4, ,3,2,1 4
Observe that there is double 4 during down counting.

On reset, the counter starts with a value 0

Increments by unity on every clock upto 7
And then decrements by unity on every clock upto 0
But observe that during decrement number 4 repeats for two clock cycles.

Template:
module updown (
input wire clk,
input wire rst,
output reg [2:0] cnt
);

Lucid Institute of VLSI Education

Reg: HNo 7-15/8/P, Sector2D, Alkapoor TownShip, Puppalguda, Manikonda,Hyderabad.
Phone No: +91 994 995 4576 Email: raja@lucidvlsi.com
Website: www.lucidvlsi.com
Testimonials : www.youtube.com/user/lucidvlsi/videos
 Raja Bandi
Director,
Lucid VLSI
M: +91 994 995 4576
Email: raja@lucidvlsi.com

2. Write Verilog DUT which generates an output as follows for the given input

Input (I): 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,

Output(O): 0,0,0,0,0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,

module two( input wire clk, rst,i,

output wire y);

Note:
An input ,I, asserts for only one clock cycle.
After the input asserts, then the output should assert 5 cycles later and
Then deassert for another cycle and
then assert again for one cycle.
It is a 101 pattern after 5 cycles
If another pulse on input appears during these 8 cycles output 101 pattern
should not be generated for this new input.

Lucid Institute of VLSI Education

Reg: HNo 7-15/8/P, Sector2D, Alkapoor TownShip, Puppalguda, Manikonda,Hyderabad.
Phone No: +91 994 995 4576 Email: raja@lucidvlsi.com
Website: www.lucidvlsi.com
Testimonials : www.youtube.com/user/lucidvlsi/videos
 Raja Bandi
Director,
Lucid VLSI
M: +91 994 995 4576
Email: raja@lucidvlsi.com

3. Write Verilog DUT for a circuit which takes a 16bit input and generates an output
which shows how many 101, non-overlapping patterns are there in this 16bit
input from left to right. Please note that there is no clock input to this circuit. It is
pure combinatorial.

module One_Zero_One( input wire [15:0] I,

output wire [2:0] Y);

Sample input and output

INPUT :: OUTPUT
0011010100100100 :: 1
0101111010000001 :: 2
1101011000001001 :: 1
0101011001100011 :: 1
0111101100001101 :: 2
1001100110001101 :: 1
1000010001100101 :: 1
0101001000010010 :: 1
1110001100000001 :: 0
1100110100001101 :: 2
1010101010101010 :: 4
1011011011011011 :: 5

Lucid Institute of VLSI Education

Reg: HNo 7-15/8/P, Sector2D, Alkapoor TownShip, Puppalguda, Manikonda,Hyderabad.
Phone No: +91 994 995 4576 Email: raja@lucidvlsi.com
Website: www.lucidvlsi.com
Testimonials : www.youtube.com/user/lucidvlsi/videos
 Raja Bandi
Director,
Lucid VLSI
M: +91 994 995 4576
Email: raja@lucidvlsi.com

4. Draw waveform signals y1 to y8 for the given code below. And write your
explanation for its behavior.

module tb;
reg y1,y2,y3,y4,y5,y6;
wire y7,y8;

reg a;
always #5 a = ~a;
initial begin a = 0; #200; $finish; end

always @(a) y1 = a;
always @(a) begin
#7;
y2 = a;
end

always @(a)begin
y3 = #7 a;
end

always @(a)begin
#7;
y4 <= a;
end

always @(a)begin
y5 <= #7 a;
end
always #7 begin
y6 = a;
end

assign y7 = a;

assign #7 y8 = a;

endmodule

Lucid Institute of VLSI Education

Reg: HNo 7-15/8/P, Sector2D, Alkapoor TownShip, Puppalguda, Manikonda,Hyderabad.
Phone No: +91 994 995 4576 Email: raja@lucidvlsi.com
Website: www.lucidvlsi.com
Testimonials : www.youtube.com/user/lucidvlsi/videos