IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO.

1, JANUARY 2015 137

A Multi-Granularity FPGA With Hierarchical

Interconnects for Efficient and Flexible
Mobile Computing
Fang-Li Yuan, Student Member, IEEE, Cheng C. Wang, Student Member, IEEE,
Tsung-Han Yu, Student Member, IEEE, and Dejan Markovi, Member, IEEE

AbstractFollowing the rapid expansion of mobile computing,

mobile system-on-a-chip (SoC) designs have off-loaded most
compute-intensive tasks to dedicated accelerators to improve
energy and area efficiency. An increasing number of acceler-
ators in power-limited SoCs results in large regions of dark
silicon. Unlike processors, dedicated hardware is inflexible, so
any changes would require a chip re-design, which significantly
impacts cost and timeline. To address the need for efficiency and
flexibility, this work presents a multi-granularity FPGA suitable
for mobile computing. Occupying 20.5 mm in 40 nm CMOS,
the chip incorporates fine-grained configurable logic blocks,
medium-grained DSP processors and reconfigurable block RAMs,
and two coarse-grained kernels: a 64- to 8192-point FFT processor
and a 16-core universal DSP for software-defined radios. Using
a mix-radix hierarchical interconnect, the chip achieves a 34x
interconnect area reduction over commercial FPGAs for compa-
rable connectivity, reducing overall area and leakage by 22.5x, Fig. 1. Efficiency vs. flexibility for microprocessors, FPGAs, programmable
and delivering up to 50% lower active power. With coarse-grained DSPs, and dedicated hardware.
kernels, the energy efficiency reaches within 45x of ASIC designs.
Index TermsDigital integrated circuits, digital signal proces- Unlike traditional power and performance criteria, efficiency
sors (DSPs), fast Fourier transform (FFT), field programmable requires a combination of metrics. Energy efficiency quantifies
gate arrays (FPGAs), interconnect networks, low-power design. work per unit energy, and is generally measured in billions of
operations per second per milliwatt (GOPS/mW). In VLSI cir-
I. INTRODUCTION cuits, this translates to battery life and thermal budget. Area effi-
ciency quantifies work per unit area, and is generally measured in

T HE rapid expansion of mobile computing has driven the

need to integrate more functionality and signal processing
on a single chip, yet maintaining a strict power and cost budget.
As a result, flexibility and energy/area efficiency have become
major criteria for mobile designs. Todays mobile system-on-a-
chip (SoC) generally embeds microprocessor cores and several
dedicated accelerators to improve efficiency while providing
flexibility. Such heuristic migration from a purely processor-
based SoC does not truly address the problem of efficient and
flexible hardware, because efficient and flexible blocks are in-
tegrated next to each other.
Manuscript received June 03, 2014; revised November 05, 2014; accepted
November 05, 2014. Date of publication December 11, 2014; date of current
version December 24, 2014. This paper was approved by Guest Editor Stephen
Kosonocky. This work was supported in part by the DARPA HEALICs pro-
gram.
F.-L. Yuan and C.C. Wang were with the University of California, Los An-
geles, CA 90095 USA. They are now with Flex Logix Technologies, Inc., Moun-
tain View, CA 94040 USA.
T.-H. Yu was with the University of California, Los Angeles, CA 90095 USA.
He is now with Qualcomm, Irvine, CA 92618 USA.
D. Markovi is with the University of California, Los Angeles, CA 90095
USA, and also with Flex Logix Technologies, Inc., Mountain View, CA 94040
USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2014.2372034
GOPS/mm . This translates to die size and cost. Rather than fo-
cusing solely on power, area or performance, targeting efficiency
balances these tradeoffs.
To look at the efficiency of todays chips, we normalize the
available data from International Solid-State Circuit Conference
and Symposium on VLSI Circuits between 1999 and 2011 to
16 b arithmetic in 65 nm technology, categorize them and take
the average (Fig. 1). We see a 1000x of gap in energy efficiency
between microprocessors and dedicated hardware [1], [2]. Pro-
grammable digital signal processors (DSPs) have a wide range of
efficiency depending on architectures and applications, but they
generally fall in between microprocessors and dedicated hard-
ware. Field-programmable gate array (FPGA) data were gathered
from [3], [4].
The idea for an accelerator-based SoC design becomes
clear: dedicated blocks provide much higher efficiency than
processors, meeting the strict energy and cost requirements.
Meanwhile, microprocessor is used as an arbiter and/or a
system controller to compensate the flexibility loss from the
accelerators. As todays SoCs require more functions in every
generation for the same power budget, adding accelerators
has resulted in large portions of dark silicon [5], [6] and
increased chip size. Using many dedicated blocks also requires
frequent design changes, due to new standards, new features,

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138
Fig. 2. A sample 2D-mesh architecture with I/O connections (top-left) and switch boxes (bottom-left).
or re-spins. Under the frequent changes and rising design costs,
the accelerator-based SoC becomes less of a scalable solution.
Instead, there is a greater need today for flexible designs that
are re-usable, but also efficient enough for the strict energy
requirements.
Another issue with dedicated blocks is compatibility with
non-standard interfaces. We are facing an exponential growth
in the number of connected devices with wide range of require-
ments for the number of antennas, modulation classes (e.g.,
PSK, QAM) and system types (e.g., OFDM, CDMA). Some
call this the Internet of Things. In addition, each device needs
functionality adjustment to respond to real-time changes in
channel condition, such as using low-energy zero-forcing or
high-accuracy sphere decoder, to balance the link throughput,
bit-error rate and power consumption. A flexible hardware
would be highly beneficial here: besides providing flexible
I/Os, it can also perform data processing for each of the con-
nected devices.
Although Moores Law lowers the cost of transistors, chips
are becoming increasingly more expensive to design. At 28 nm,
the nonrecurring engineering (NRE) cost of a custom-made
IC is more than $50 million [7]. For chip makers to afford
the newest technology, amortizing the design cost over a large
volume is no longer enough. Chips need to work the first time,
fit in a range of end-products, and remain competitive and
up-to-date for a longer product cycle. We now need hardware
re-use. To achieve such flexibility, we need flexible hardware.
But to maintain the efficiency of current SoCs, we need effi-
cient, flexible hardware.
Among the candidates for flexible hardware, microprocessors
are least efficient. They will not replace ASICs. Software-con-
trolled programmable DSPs are unlikely to deliver the bit/cycle-
true behavior of ASICs. DSPs also have lower throughput un-
less massively-parallel single-instruction-multiple-data (SIMD)
architectures [8][10] are used. FPGAs, designed to emulate
dedicated hardware in a bit/cycle-true manner come closest in
mimicking ASICs. FPGAs have ASIC-like throughput due to
parallel logic blocks. But to make FPGAs real candidates in the
mobile space, we ought to narrow a large efficiency gap between
FPGAs and ASICs.
We present a multi-granularity FPGA aimed for mobile com-
puting and focus on two key steps towards higher efficiency:
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
interconnect networks, and coarse-grained reconfigurable DSP.
Section II gives a brief background of FPGA interconnect
networks. Section III presents our hierarchical interconnects
for a more efficient FPGA. The multi-granularity FPGA with
various configurable logic blocks is described in Section IV,
and Section V adds the coarse-grained DSP as the key module
for mobile computing. Chip software flow is presented in
Section VI, followed by measured results and comparison to
prior art in Section VII. Section VIII concludes the paper.
II. BACKGROUND OF FPGA INTERCONNECT NETWORKS
It is well known that FPGAs incur penalty in area (1770x),
speed (36x) and power (552x) compared to standard-cell
ASICs in the same process technology, but these numbers
do not represent efficiencies [3]. The actual energy efficiency
gap is the product of the speed and power gap, and the area
efficiency gap is the product of the area and speed gap.
It is natural to attribute the FPGA inefficiency to the sea-of-
lookup-tables (LUTs) architectures. Although generally called a
gate-array, it is the interconnect network that occupies the ma-
jority of the FPGAs area (7580%), delay ( 75%), and power
( 60%) today [3], [11], [45].
A. Traditional 2D-Mesh Networks
Although FPGAs have grown enormously in size since their
inception (64-LUTs in XC2000), the fundamental interconnect
architecture still remains (Fig. 2). In 2D-mesh interconnects,
LUTs are placed in configurable logic blocks (CLBs), and in-
terconnects run in the x- and y-direction surrounding the CLBs.
I/O connection switches tie the CLB I/O to the interconnect net-
work. Arrays of switch boxes are placed at interconnect cross-
ings to select and buffer the programmed path, each containing
programmable pass-transistors. Since a full switch-box array
at every interconnect crossing requires too much area, various
heuristics are used to simplify the arrays at the cost of lower con-
nectivity [12][14]. In Fig. 2, the example network only imple-
ments switch boxes along one main diagonal and two sub-diago-
nals of the switch-box array. Modern FPGAs have also migrated
toward unidirectional routing to reduce interconnect loading
[15], [16].
YUAN et al.: A MULTI-GRANULARITY FPGA WITH HIERARCHICAL INTERCONNECTS FOR EFFICIENT AND FLEXIBLE MOBILE COMPUTING
Fig. 3. An example folded-Bene network with radix-2 switches, and a data width of 2.
The root cause for interconnect overhead is the scalability of
2D-mesh interconnects. In the worst case, the number of switch
boxes grows as with the number of LUTs. Although
heuristics can reduce the number of switches, there is a limit.
Rents rule can be used to model interconnects,
where is the number of gates, is the Rents coefficient for
modeling the number of I/Os, and is a constant of propor-
tionality. In typical cases, the interconnect complexity per logic
block is for random logic, which is still
for a chip of logic blocks [17]. For highly regular designs,
such as a memory banks, the complexity per logic is . usability. These steps are further described below.
Since FPGA mapping software employs intelligent gate place-
ments, the logic is not completely random, but it is certainly
not as regular as memory banks. We therefore expect the ac-
tual Rents exponent to be between 0.5 and 0.75 [13], which
gives us lower and upper bounds on interconnect complexity.
Clearly, FPGA interconnect needs to scale much faster than the
number of logic elements . Scaling from 64 in XC2000 to
1,000,000 in modern FPGAs, it becomes clear why interconnect
area is a key concern today.
B. Previous Hierarchical Networks
To address the non-scalability of 2D-mesh, there have been
some designs adopting hierarchical interconnects based on a
Benes network that scales as . The Clos, Bene, and
similar hierarchical networks are well-known to be rearrangeably
non-blocking network for point-to-point connections, and are
commonly used in telecommunication [18][20]. Numerous
publications have also discussed hierarchical FPGAs with a
tree-of-meshes topology [21][24]. It is a limited bisection
network, where the mesh connectivity decreases for upper hierar-
chies.Acentralizedroutingnetworkisrequiredateveryhierarchy,
which increases routing congestion. The scalability issue is par-
tially resolved, as the central switches are still based on 2D-mesh.
A multilevel hierarchical FPGA was published in [25], al-
though no silicon realization is attempted. The architecture uses
a radix-4 topology with a Rents exponent of 1, but only on
the downward paths. The upward path, on the other hand, pro-
vides no path diversity. Therefore, the overall path diversity of
the architecture is very limited, and the interconnect connec-
tivity when mapping designs is about 3050%, often requiring
a 2K-LUT FPGA to map 1K-LUT designs.
C. Our Challenges
Although hierarchical FPGA has great appeal on paper, it has
not had much success in practice. The main reason is that it has
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yet to demonstrate any advantage over 2D-mesh. On the other
hand, 2D-mesh FPGAs today are already very mature, well-op-
timized products.
For our work to be considered worthwhile, we need to
demonstrate a hierarchical FPGA with significant benefits
over state-of-the-art commercial FPGAs. For practicality, an
automated tool is also needed to map user designs. Overall,
this project requires us to first create an efficient interconnect
architecture and reconfigurable logic, realize it in silicon,
then develop software tools to demonstrate its advantages and
III. OUR HIERARCHICAL INTERCONNECT NETWORK
We adopted a hierarchical interconnect architecture based on
a folded-Bene network. An example network is shown in Fig. 3
to illustrate the concept. It is radix-2, so each switch matrix (SM)
accepts inputs from two SMs, and sends its outputs to two other
SMs; both upstream and downstream. Signals will come from
the LUT output, traverse up to the required hierarchy, and tra-
verse back down to the LUT input. To ease routing congestion,
our architecture evenly distributes routing across all LUTs in-
stead of crowding them into centralized hubs [23], [27].
A. Radix-3 Boundary-Less Interconnect
Although hierarchical routings complexity is
simpler than from 2D-mesh, it can be inefficient for local
routing if the leaves are crossing a high-radix boundary, resulting
in performance loss. For example, in Fig. 4(a), LUTs 8 and 9
are neighbors, but signals have to traverse up 4 stages of net-
work, and then zig-zag their way down the hierarchy. Such lack
of spatial locality is not desirable. One method to shorten the
nearest-neighbor routing lengths is an isomorphic transforma-
tion, as shown in Fig. 4(b), which maintains the same logic con-
nectivity [28]. Although the wire length travelled has reduced,
the number of switches has not: the signal still needs to traverse
up and down 4 hierarchies for communication between LUT 8
and 9.
We propose a method of applying higher radix switches on the
lower SM levels to utilize spatial locality in routing, allowing
efficient interconnect routing for direct neighbors. We call such
network a boundary-less radix-3 (BLR3) network [29]. To con-
vert a radix-2 network to a BLR3 network, we first identify the
center 2 2 routing of each stage, shown in the dashed circle in
Fig. 4(b). They only connect across an interconnect length of 1.
All circled 2 2 routings are then moved to stage 1 (Fig. 4(c)),
140 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015

Fig. 4. (a) An original 16-LUT Bene network, (b) with isomorphic transformation to shorten nearest-neighbor lengths, and (c) with boundary-less radix-3 switches
in stage 1.

Fig. 5. A 16-LUT Bene network, (a) with boundary-less radix-3 switches in stages 1 and 2, (b) with boundary-less radix-3 switches in stage 1-3, and (c) rearranged
for distributed routing.

transforming to a BLR3 stage. All stage-1 switches are now ca-
pable of communicating with their immediate neighbors.
After stage 1 is converted into BLR3 (Fig. 4(c)), the stage
routings only connect across an interconnect length of
3. The 2 2 routes with a length of 3 are then moved down to
stage 2 (Fig. 5(a)), converting the second stage to BLR3. This
stage-by-stage transformation can be continued to the top of
the hierarchy (Fig. 5(b)). Alternatively, the designer may also
choose to stop at any hierarchy, and preserve the remaining
upper hierarchies as traditional radix-2 network.
In Fig. 5(b), we see that all stages above stage 1 have un-
evenly distributed routing: some switches have to connect more
routing than others. This scenario occurs because the number of
wires above stage 1 has been reduced by 50%. To form a regular
routing pattern, one method is to evenly re-distribute the inter-
connect routing: the dual routes branching out of stages 1-4 are
re-distributed across all switches, resulting in the final routing
architecture shown in Fig. 5(c).
The BLR3 network is one of the many techniques we used
to optimize the interconnects. It is difficult to model and quan-
tify what impacts these changes have on the overall quality of
the network. We can evaluate it by mapping benchmark designs
through our CAD tool, which reports routing congestion and crit-
ical-path delay. We then tune the architecture and re-evaluate.
The final interconnect architecture (Fig. 6) has 40 tiles in
seven different types. Each tile has 512 SM macros, ranging
YUAN et al.: A MULTI-GRANULARITY FPGA WITH HIERARCHICAL INTERCONNECTS FOR EFFICIENT AND FLEXIBLE MOBILE COMPUTING
Fig. 6. The final interconnect architecture divided into 40 tiles, each with 512 switch-matrix macros, ranging from 9 to 14 levels of hierarchies.
Fig. 7. A 4-input static mux with output inverter and our proposed, tri-state PG.
from 9 to 14 levels of hierarchy. The upper hierarchies have
fewer available wires as a result of interconnect pruning from
our closed-loop design process.
B. Fine-Grained Interconnect Power Gating
The interconnect network in an FPGA can involve long wires
and large output drivers. To reduce leakage, power gating (PG)
is employed to power off the output drivers when unused. Footer
transistors work well for PG an entire block, but interconnect
signals are long, thus lack spatial locality. It is therefore ineffec-
tive to PG interconnect at the block level, because just one ac-
tive interconnect buffer would prevent an entire region from PG.
Therefore, fine-grained PG circuitry is needed, such as adding
footer transistors and PG control to individual output drivers.
In interconnect switches, the output drivers are already large.
Because the PG footer transistors are in series with the output
transistors, the footer needs to be made wide to maintain the on
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current. So, in traditional PG designs, there is either a large area
penalty from a larger footer, or a large performance penalty from
a smaller footer.
Our power-gating method for interconnects requires minimal
area overhead and has no significant performance impact [30]. A
pass-transistor input is added for PG, and the inputs to the output
inverter are separated into pmos and nmos inputs, joined by a min-
imum-size, high- transmission gate as keeper (Fig. 7). During
PG, signal is 1, the keeper is off, and the pmos and nmos are
driven to opposite polarities, 1 and 0, respectively, turning off
both output transistors. This tri-state not only reduces leakage, but
also drastically reduces the coupling capacitance experienced by
neighboring wires by forming a capacitive divider.
When one of the select bits, is on, power-gating
is disabled, and the keeper is enabled to bring the pmos and
nmos nodes together. The static MUX must quickly transmit
the selected input to the output inverter. The MUX contains
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Fig. 8. The FFT architecture and radix factorizations of different FFT resolutions.
a full transmission gate, enabling a good drive capability for
both 0 and 1 at the input. The NMOS pass gate is connected
to the node pmos to rapidly turn on the PMOS transistor, and
the PMOS pass gate is connected to the node nmos to rapidly
turn on the NMOS transistor in the output inverter. When one
transistor in the output inverter is turning on, the other is not
yet fully off (its gate voltage hovers around until the keeper
completes the transition), but the current difference between the
output transistors is large enough to not impact the performance
by more than 10%. Eventually, the keeper connects the pmos
and nmos nets to the same voltage, and the static leakage is no
different from a traditional CMOS inverter.
The design in Fig. 7 cannot directly drive CMOS gates, be-
cause it leads to floating gates during PG. The outputs can only
drive the input of another static MUX. All nets driven by tri-state
buffers must be set as dont_touch during chip synthesis to avoid
automated buffer insertion.
Utilizing our closed-loop interconnect optimization, and our
area-efficient PG scheme, the overall interconnect area is re-
duced to 52% of the total core area, maintaining a logic-to-
interconnect ratio of 1:1. Compared to 2D-mesh FPGAs that
use 7580% of the area for interconnects, this chip achieves
a 34x reduction for a fixed logic area. Compared to our pre-
vious work [26], we have scaled the logic complexity by more
than 10 times while maintaining the same logic-to-interconnect
ratio. Even though we should see a increase in inter-
connect area, the area increase is mitigated by our closed-loop
interconnect optimization.
IV. MULTI-GRANULARITY FPGA ARCHITECTURE
An improved interconnect network does not address the inef-
ficiency of the CLB itself since fine-grained CLBs are more gen-
eral purpose but less efficient. The second step towards better
efficiency is to realize coarse-grained kernels. This chip is built
with three granularities of CLBs.
A. Fine-Grained and Medium-Grained Configurable Logic
Block
The fine-grained CLBs mainly consist of LUTs and their sur-
rounding logic, such as basic arithmetic and flip-flops. Some
CLBs also support modes for small memories and shift registers.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
The CLBs are made to be logically-compatible with the CLB
designs from Xilinx Virtex-6 and 7. This not only allows our
FPGA to be synthesized with commercial synthesis tools (e.g.,
Synplify Pro), but it also enables a direct comparison of perfor-
mance and power between our FPGA and commercial FPGAs
while mapping identical designs.
More intensive arithmetic such as wide multiplications and
multi-input additions require a more dedicated DSP acceler-
ator, and larger memories require a more dedicated memory IP.
We designed the DSP accelerators to be compatible with the
DSP48E1 accelerators from Xilinex. Various pipeline modes
are implemented to support a maximum operation frequency of
800 MHz. Our BRAM CLBs are 36 Kb each, also compatible
with the RAMB36 designs from Xilinex.
B. Coarse-Grained Configurable Logic Block for
Communication Signal Processing
Since this chip primarily targets high-throughput com-
munication applications, we integrated two coarse-grained
accelerators to achieve higher efficiency for domain-specific
computations.
The first block is a 64- to 8192-point reconfigurable Fast
Fourier Transform (FFT) processor (Fig. 8). The FFT is de-
signed with 16 parallel, 4- to 512-point cores, followed by a
16-point final stage for data combining. To save area, BRAM
and CLB memories on the FPGA are utilized to form the delay
lines (DLs) of size above 32, while the pointer-based shift reg-
isters are employed for smaller DLs. Each of the 16 cores is im-
plemented as a 3-stage mixed-radix pipelined FFT to ease the
timing requirements and leverage voltage scaling for high en-
ergy efficiency. Extensive analysis of radix factorization is per-
formed in [31] to determine the optimal radix per pipeline stage
that minimizes the energy and area cost.
The second coarse-grained block is a 16-core, highly-efficient
universal DSP accelerator, reconfigurable to perform tasks for
software-defined radio (SDR).
V. DOMAIN-SPECIFIC COARSE-GRAINED UDSP PROCESSOR
Growing number of radio standards has led to the concept
of SDRs, where hard-wired computing blocks (e.g., channel
YUAN et al.: A MULTI-GRANULARITY FPGA WITH HIERARCHICAL INTERCONNECTS FOR EFFICIENT AND FLEXIBLE MOBILE COMPUTING
Fig. 9. For SDR tasks, the (a) generic 2 2 dataflow structure is considered as the proper granularity. More detailed implementation of the SIMD-style BCE is
illustrated in (b).
estimation) are replaced by flexible hardware to adapt to
evolving protocols. The domain-specific reconfigurable pro-
cessor (DSRP) is a promising architecture for SDRs [32]. It uses
an array of compute elements linked by 2D-mesh interconnects
to reduce the control overhead associated with traditional pro-
cessors. Architectures of DSRPs have been extensively studied
with emphasis on the core granularity [33], dynamic voltage
and frequency scaling [34] and globally-asynchronous-lo-
cally-synchronous clocking [36]. However, the benefits of
control circuit simplifications for instruction deployment are
not thoroughly studied. Prior DSRPs exploited SIMD/MIMD
operations to reduce the control overhead, but their instruction
set architecture (ISA) was predefined in hardware. Such inflex-
ible ISA had to be complex to make it universal enough for the
required flexibility, increasing the area and energy overhead.
In addition, any design change may create a need for new
instructions, but a non-expandable ISA might fail to support
the new features or use existing instructions as a work-around.
The computations of todays DSRPs can be made efficient with
existing architectural and circuit techniques, but the inflexible
control architecture still limits the achievable efficiency and the
hardware reusability.
We propose flexible instruction-set architecture (ISA) aimed
at simplified control and enhanced flexibility of DSRPs. We
observe that for each domain-specific task, only a subset of
the entire instruction set is required. If we can flexibly define
the task-specific instructions prior to program execution, we
no longer need a fixed and complex ISA that has high code
coverage but low utilization. Adaptation problems with design
changes can also be resolved by simple hardware reconfigura-
143
tions. To realize this concept, the traditional ISA decoder is re-
placed by a register bank to deploy the task-dependent control
signals. Real-time instruction definition is done by configuring
the bank through specialized configuration commands.
In addition to control circuits, we investigate the core gran-
ularity and connectivity for highly efficient and flexible imple-
mentations. The butterfly compute element (BCE) supports ar-
bitrary 2 2 complex-valued matrix operations and is found as
proper granularity for SDR workloads. The multi-scale inter-
connects comprise the two-dimensional fastpaths and the hier-
archical network for efficient data arbitration between BCEs and
other FPGA fabrics.
A. 16-Core UDSP Architecture
The proposed UDSP supports filtering, channel estimation,
blind classification, and signal detection for 1 1 to 4 4
multi-antenna (MIMO) systems with modulation order from
BPSK to 64QAM. It is comprised of 16 homogeneous cores
in a 4 4 2D array [37]. Each core embeds one BCE and four
interconnect switches (ISWs) for programmable computing
and networking. Local connection between adjacent cores
is supported by a 128-bit uni-directional, 2D fast-path that
allows horizontal transmission from left to right, and vertical
link in a zigzag fashion. This approach saves 50% of the cir-
cuit-switched MUXes compared with a bi-directional scheme
[34], yet it preserves enough connectivity for stream-oriented,
multistage mappings. The ISWs form a hierarchical network,
compatible to that on the FPGA, to allow data exchange and
multicasting between cores and other on-chip CLBs.
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Fig. 10. Flexible ISA control mechanism.
Fig. 11. Energy breakdown of 4 4 QRD shows an overall 1.8x of energy saving from the flexible-ISA over the traditional fixed-ISA scheme.
B. Butterfly Compute Element
The datapath structure directly impacts energy efficiency of
the core. An efficient dataflow minimizes data movement, re-
ducing the program runtime and power. Modeling the energy
cost of each component clarifies the approach. For example,
a 16-bit add takes around 0.035 W/MHz at nominal in
40 nm CMOS, while a 16-bit read/write access from the reg-
ister file costs around 1.7 W/MHz, a 50x higher than addition.
From our examination of common SDR algorithms, we propose
a generic 2 2 butterfly dataflow structure as the proper granu-
larity (Fig. 9(a)). This 2 2 structure can map functions such
as filters (for spectrum shaping), QR decomposition (QRD) (for
channel factorization), linear equalizer and sphere decoder (SD)
(for signal detection).
The SIMD-style BCE, optimized by modeling the energy cost
of elementary components, is designed to process 16-bit com-
plex-valued data in fixed point (Fig. 9(b)). Three major compo-
nents: 16-bit multimode multipliers, 32-bit shifters, and 40-bit
adders, are flexibly concatenated to perform MAC, normaliza-
tion, Euclidean distance, 116x-iterated CORDIC, etc. Auxil-
iary components, such as sinusoid synthesis (SIN), CORDIC
pre-normalization, and the metric-enumeration unit (ME) accel-
erate the miscellaneous SDR operations. Two pipeline stages,
plus the multiplier output registers, are inserted for a 500MHz
peak clock rate, while the functional registers are used for task-
dependent retiming and data interleaving. All of the above com-
ponents and memories are aggressively clock-/input-gated to
save unnecessary switching energy. The 2R2W 64 32-bit reg-
ister file (RF) is employed for local data access and FIFO. The
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
RF is composed by two independent sub-banks, M1 and M0, re-
spectively. The write access can only be issued to different sub-
banks, but the read access can come from the same sub-bank.
This feature enables efficient data combining among M0 and
M1 to lower the memory requirement for various SDR tasks,
such as the candidate-symbol generation in the MIMO SD.
The BCE datapath consumes about 6 W/MHz per core at
nominal supply voltage, equivalent to energy overhead from 50%
to 210% as compared to the cost of active operations from heavy-
to light-loaded tasks. This overhead, however, yields great reduc-
tion in memory access and program latency. For example, a 12x-
iterated CORDIC square root takes 12 cycles with no interme-
diate RF access, 18x faster than 216 cycles in the state-of-the-art
communication processor [36]. From an efficiency perspective,
the 18x saving in instruction memory (4 W/MHz) already out-
weighs the datapath overhead by 12x, even without considering
the overhead of RF and datapath in [36].
C. Flexible ISA
The flexible control structure for each BCE comprises a
128 43 bit instruction memory (IM), a programmable SM
and a flexible ISA decoder (Fig. 10). Among each of the 43-bit
instructions, the 3-bit instruction header defines whether it
belongs to the configuration or the operation type. The former
configures the ISA decoder based on the remaining 40-bit
content, while the latter uses a 10-bit opcode to access up to
eight branching states, two network and 64 datapath config-
urations from the state, network and datapath register banks
YUAN et al.: A MULTI-GRANULARITY FPGA WITH HIERARCHICAL INTERCONNECTS FOR EFFICIENT AND FLEXIBLE MOBILE COMPUTING 145

Fig. 12. Our 2-mode place-and-route flow, from user input to bitstream generation.

Fig. 13. Die micrograph and summary.

(SRB/NRB/DRB). The contents of the RBs are then selec-
tively accessed to translate the opcodes to the physical control
patterns. To save the computing complexity of ISA decoder,
we partition the DRB into three sub-banks , each
respectively controlling the input, arithmetic, and output part
of the BCE. Compared with a heuristic approach that require a
64-row DRB to memorize 64 BCE configurations, our approach
can save the DRB area by 16x (4 vs. 64) without significant loss
in controllability. For each task mapping, the BCE configures
the instruction decoder prior to execution. The configuration
time is task-dependent, typically no more than 12 clock cycles.
Due to the reconfiguration feature, the same opcode can result
in totally different physical microcode information to distinct
SDR tasks.
The programmable SM directs the value and accumulation
mode of the program counter (PC) to access the IM. Each of
the eight available states, as configured in SRB, contains a 7-bit
inner-loop bound (ILB), 7-bit outer-loop bound (OLB), 1-bit
PC accumulation enable, 7-bit PC start value , 1-bit
state-counter accumulation enable, 5-bit state-counter start
value , and a 5-bit state-counter end value
to establish state transition and counting rules for a variety of
pointers in the SM. Overall, the SM enables zero-overhead
looping, branching and subroutine calls to map any SDR task
146
Fig. 14. Benchmark mapping of UDSP for performance measurements.
Fig. 15. Comparing the UDSP with state-of-the-art communication multiprocessors and functionally-equivalent ASICs show its good compromise between pro-
grammable and dedicated solutions.
with high efficiency and flexibility. Since the behavior of the
SM is solely controlled by the state information in the SRB, the
IM can fully focus on data manipulation without wasting time
and energy on managing the PC value and the program flow.
As a result, the SM can effectively lower the program runtime
and improve the IM efficiency as compared to traditional
processors.
The energy breakdown of the 4 4 QRD (memory- and
control-dominant task) shows the benefits of flexible control
(Fig. 11). Compared with the traditional control, the flexible
decoder dissipates 6.4x less energy due to simpler selection
logic. The IM energy is also reduced by 3.3x due to the higher
code efficiency and the SM. The overall energy saving is 1.8x,
making the efficiency of QRD around 2.34 GOPS/mW at 0.5 V,
only a 2.3x lower than a dedicated QRD [40].
VI. CHIP PROGRAMMING AND SOFTWARE FLOW
This chip is built to be a flexible hardware, but it is not useful
unless it is easy to program. With over 9 million configuration
bits, we need an automated mapping flow. In the commercial
FPGA, the user design is synthesized into a LUT-level netlist,
and then sent into a vendor-specific tool, which then packs the
LUTs into their CLBs, followed by placement and routing.
Our mapping flow supports two modes (Fig. 12). Mode 1 ex-
ecutes on a packed netlist compatible with commercial FPGAs,
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
thus only utilizes the fine- and medium-grained CLBs. Our tool
parses the packed netlist and performs floorplan, placement,
routing, static timing analysis, and bitstream generation. This
mode creates a design that is functionally identical to existing
FPGAs for a bit-accurate, cycle-accurate comparison.
Mode 2 adds support for our coarse-grained FFT and UDSP.
As of now, the user has to manually define the functions to ex-
ecute on the coarse-grained blocks, and generate the assembly
code to configure the UDSP. The rest of the logic goes through
the commercial synthesis flow.
VII. CHIP MEASUREMENT AND RESULTS
The die photo and summary are shown in Fig. 13. Due to
the high pin count and the performance requirement, a chip-on-
board is used to interface with a Kintex-7 testbench FPGA.
We consider five SDR benchmarks for standalone UDSP
measurements: 1) 64-tap raised-cosine FIR [38]; 2) 8th-order
Chebyshev Type-II IIR; 3) 4th-order cyclic-autocorrelation
(CAC) [39]; 4) 4 4 QRD [40]; (5) 4 4 MIMO SD [41].
Fig. 14 illustrates the energy efficiency vs. supply voltage. A
55.6x efficiency gap is observed between the compute-centric
SD and the memory-/control-dominant QRD. Robust chip
functionality is measured down to 415mV with minimum
power of 275 W/core at 25 MHz, 25 C for the SD. At this
operating point, the leakage and the active power are roughly
YUAN et al.: A MULTI-GRANULARITY FPGA WITH HIERARCHICAL INTERCONNECTS FOR EFFICIENT AND FLEXIBLE MOBILE COMPUTING 147

Fig. 16. Measured results showing the impact of multi-grained blocks: (Inset) A 32-tap FIR filter mapped with Virtex-6, our chip with fine- and medium-grained
CLBs, and our chip with coarse-grained UDSP CLBs; (Main plot) A 1024-point FFT mapped on microprocessor, FPGA, DSP processor, this chip, and ASICs.

equal. This point also translates to a peak energy efficiency of

13.1 GOPS/mW (76 fJ/OP). Further, the performance of the
chip can scale up to 1.17 TOPS at 500 MHz, 1.0 V, achieving
4.2 GOPS/mW.
To validate the efficiency benefits over state-of-the-art com-
munication processors, we normalize the energy per operation
of UDSP to 65nm for a fair comparison (Fig. 15). The nor-
malization is performed by matching the gate delay vs. supply
voltage, and scaling the leakage and active power separately
across technology nodes based on SPICE simulations. A nor-
malized energy of 9.2 pJ/16-bit MAC shows 2.44.8x higher
efficiency than [34], [35], [42]. The improvement scales up
to 22x for low-voltage operations. Since energy per operation
alone does not guarantee real-time performance, we also nor-
malize the energy of UDSP and functionally equivalent ASICs Fig. 17. Summary of our contributions. Efficiency and flexibility requires the
[38][41] to the same throughput for a fair comparison. As use of 1) compact interconnect networks and 2) coarse-grained reconfigurable
blocks. Efficiency of UDSP alone is shown for comparison. Compiler support
shown in Fig. 15, the UDSP bridges the energy efficiency gap for UDSP-type blocks is required for user adoption.
with ASICs to within 2.6x.
To consider the entire chip operations, a 32-tap FIR filter
implemented on Virtex-6, our FPGA with CLBs only, and our per FFT sample, but is still 1.5x less efficient than our flexible
FPGA with coarse-grained UDSP kernels is shown in Fig. 16. hardware. Another 13x gain can be achieved by enabling our
Our measured results are compared with Virtex-6 production FFT kernel.
data generated from the ISE tool. Because Virtex-6 is larger For this example, we see that our chip runs about 30% slower
than our chip, we normalize the leakage area to only the utilized than Virtex-6. This is mainly due to our software place and
area after place and route. We measured up to 0.86 GOPs/mW route, which is still rudimentary. From our experience, complex
using only fine-grained CLBs, a 4x efficiency gain over Virtex-6 designs tend to see 1030% performance degradation from our
due to interconnect area, power-gating, and voltage scaling. The router. Our design is standard-cell based, which also affects the
coarse-grained UDSP kernel provides another 8x efficiency gain speed when compared to custom-designed commercial parts.
and up to 400 MHz performance. More examples are shown in Table I. These are designs for
To illustrate how this chip compares with other devices, and which we have the RTL available in-house, synthesized onto
to illustrate the benefit of coarse-grained blocks, Fig. 16 also our FPGA using only fine-grained and medium-grained CLBs.
shows the measurement results of mapping a 1024-point FFT. These RTL designs were previously used to build our ASIC
In comparison, our chip is 1020x more efficient than DSP so- chips, measured under similar ambient conditions. With the
lutions and microprocessors, while maintaining much higher improved energy efficiency from interconnects, we are within
throughput (1 clock cycle per FFT sample vs. 17 to 100 cy- 1215x the energy efficiency of ASIC designs when normalized
cles, respectively). The DSP with a dedicated FFT core achieves for the ASIC technology. The area penalty is around 3060x.
higher efficiency and throughput by averaging only 2.8 cycles These are amongst the best efficiency numbers for FPGAs
148
TABLE I
MEASUREMENT RESULTS USING ONLY FINE- AND MEDIUM-GRAINED CLBS
TABLE II
MEASUREMENT RESULTS USING FINE-, MEDIUM-, AND COARSE-GRAINED CLBS
today. For many smaller designs, we believe flexible logic is a
good solution. For larger blocks, the efficiency gap may still be
too large for many ASIC designers to adopt, but this is where
the coarse-grained kernels can contribute.
By offloading computationally-intensive blocks to our FFT
and UDSP kernels, the energy efficiency gap can be reduced to
less than 5x (Table II), and the area penalty to 1230x (Fig. 17).
We believe this is the key step to efficiency, which is to first
identify reconfigurable kernels that can be used effectively, and
use flexible logic to do the rest.
VIII. CONCLUSION
In this work, we have made two steps towards more efficient,
flexible hardware. Our first step is a hardware with more effi-
cient interconnect. It is supported by a suite of design automa-
tion tools, leveraging commercial synthesis and custom P&R.
For some applications, the efficiency offered by this flexible
logic is sufficient. But to move even closer to ASIC efficiency,
domain-specific flexible kernels are the key addition. Such flex-
ible hardware with higher efficiency and proper tool support can
fill the need for many mobile applications. We believe the future
of mobile computing is much more than large SoCs for phones
and tablets; it would be filled with many sensors and wireless de-
vices in the Internet of Things. For these smaller wireless nodes,
this type of efficient, flexible hardware will serve as key com-
ponent for both the interface and signal processing needs.
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Fang-Li Yuan (S10) received the B.S. and M.S.
degrees from National Taiwan University, Taipei,
Taiwan, in 2006 and 2008, respectively, and the
Ph.D. degree from the University of California, Los
Angeles (UCLA), CA, USA, in 2014, all in electrical
engineering.
He joined Flex Logix Technologies, a semicon-
ductor IP startup, in 2014. His research interests
include the flexible DSP architectures and VLSI
circuits for communication signal processing, with
particular focus on the software-defined and cogni-
tive radios.
Dr. Yuan was awarded the Broadcom Fellowship in 2012 for his research on
the multi-core processors for software-defined radios. In 2014, he received the
Distinguished Ph.D. Dissertation Award in Circuits and Systems from UCLA.
Cheng C. Wang (S06) received the B.S. degree in
electrical engineering and computer sciences from
the University of California, Berkeley, CA, USA, in
2005, and the M.S. and Ph.D. degrees in electrical
engineering from the University of California, Los
Angeles, CA, USA, in 2009 and 2013, respectively.
In 2014, he co-founded Flex Logix Technologies,
Inc. His research interests include the design automa-
tion flow for reconfigurable hardware, as well as en-
ergy-efficient circuits and systems.
Dr. Wang received the Distinguished Ph.D. Disser-
tation Award in Circuits and Systems from UCLA in 2013.
Tsung-Han Yu (S10) received the B.S. and M.S.
degrees in electrical engineering from National
Taiwan University, Taipei, Taiwan, in 2005 and
2007, respectively, and the Ph.D. degree from the
Department of Electrical Engineering at the Univer-
sity of California, Los Angeles, CA, USA, in 2013.
His research is focused on digital integrated cir-
cuits and architectures for communication signal pro-
cessing, such as wideband spectrum sensing in cog-
nitive radios. In 2013, he joined Qualcomm, Inc. for
digital modem designs.
Dejan Markovi (S96M06) received the Ph.D.
degree at the University of California, Berkeley, CA,
USA, in 2006, for which he was awarded the 2007
David J. Sakrison Memorial Prize.
He is a Professor of Electrical Engineering at
the University of California, Los Angeles (UCLA),
CA, USA. He is also affiliated with UCLA Bio-
engineering Department as a co-chair of the
Neuroengineering field. His current research is
focused on low-power embedded systems for basic
neuroscience and clinical neurophysiology, with
emphasis on memory and learning. His research also includes energy-efficient
VLSI architectures, design with post-CMOS devices, optimization methods
and CAD flows. He co-founded Flex Logix Technologies, a semiconductor IP
startup, in 2014.
Dr. Markovi received an NSF CAREER Award in 2009. In 2010, he was a
co-recipient of the IEEE ISSCC Jack Paper Award for Outstanding Technology
Directions.