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Whites, EE 320 Lecture 27 Page 1 of 8

Lecture 27: MOSFET Circuits at DC.


We will illustrate the DC analysis of MOSFET circuits through
a number of examples.

Example N27.1 (similar to text Example 5.3). Design the circuit


below so that the MOSFET operates with I D 0.4 mA and
VD 1 V. The MOSFET has Vt 2 V, nCox 20 A/V2, L 10
m, and W 400 m. Neglect the channel-length modulation
effect ( 0 ).

I D 0.4 mA
VD 1 V

This last statement (i.e., = 0) means we can neglect the


MOSFET output resistance ( ro ).

5 1
RD 10 k
0.4 mA

2016 Keith W. Whites


Whites, EE 320 Lecture 27 Page 2 of 8

From this circuit we can see that VGD 1 V, which is less than
Vt. Consequently, the channel is pinched off at the drain end.
Therefore, the MOSFET is operating in the saturation or cutoff
modes (not the triode).

Well assume operation in the saturation mode. In this mode


1 W 1 W
I D kn VGS Vt nCox VGS Vt
2 2

2 L 2 L
Substituting
1 A 400
VGS 2
2
0.4 mA 20 106 2
2 V 10
Therefore
VGS 2 1 VGS 2 1
2

or VGS 1 V or 3 V
The first solution is not consistent with our initial assumption of
operation in the saturation mode since it is less than Vt.
Therefore,
VGS 3 V VS 3 V

VS 5 VS 5 3 5
Finally, RS 5 k
IS ID 0.4 mA

Example N27.2 (similar to text Exercise D5.9). Design the


circuit below so ID = 0.4 mA. The MOSFET has Vt 2 V,
nCox 20 A/V2, L 10 m, and W 100 m. Neglect ro.
Whites, EE 320 Lecture 27 Page 3 of 8

VD

With the gate and drain terminals connected together VGD 0 ,


which is not greater than Vt. This means the channel is not
continuous and the MOSFET is not operating in the triode
mode. Well assume the device is operating in the saturation
mode.

1 W
I D nCox VGS Vt
2
In saturation,
2 L
1 100
VGS 2 VGS 2 2
2
or 0.4 103 20 106
2 10
Consequently,
VGS 0 or 4 V
The first solution is not consistent with operation in the
saturation mode since VGS Vt .

Hence, withVGS 4 V and VDG 0 V VD 4 V.

Finally, since I G 0 then


10 VD 10 4
R k 15 k
0.4 mA 0.4
Whites, EE 320 Lecture 27 Page 4 of 8

Example N27.3 (text Example 5.4). Design the circuit below for
a drain voltage of 0.1 V. Determine rDS. The MOSFET has Vt 1
V and kn W L 1 mA/V2. Neglect ro.

(Fig. 5.23)
With VGS 5 V and greater than Vt, the MOSFET has an
induced channel and is not cutoff.

Next, lets check to see if the channel is pinched off at the drain
end. We can do this two (equivalent) ways. First, with VD 0.1
V then
VGD 5 0.1 4.9 V
which is greater than Vt (= 1 V), so the channel is not pinched
off at the drain. Alternatively, we can compute
VGS Vt 5 1 4 V
which is greater than VDS (= 0.1 V). So again we find that the
channel is not pinched off at the drain.

Either of these two results means the MOSFET is operating in


the triode mode (continuous channel).
Whites, EE 320 Lecture 27 Page 5 of 8

In the triode region,


W 1 2
I D kn VGS Vt VDS VDS
L 2
1
1 103 (5 1)0.1 (0.1) 2
2
so that I D 0.395 mA

5 0.1
Then RD k 12.41 k
0.395
V 0.1
and rDS DS k 253
I D 0.395

We could also use (5.13) for this last result, but the work was
already done here. From the text,
1
vDS W
rDS kn VGS Vt (5.13b)
iD vDS small L
vGS VGS

Using the values above,


1
rDS 103 5 1 250 .
This value is slightly different than what was calculated earlier.
Which one is correct? Why is the other not as accurate?

Example N27.4 (text Example 5.7). Design the circuit below so


that the MOSFET is operating in the saturation mode with
I D 0.5 mA and VD 3 V. What is the largest RD such that the
Whites, EE 320 Lecture 27 Page 6 of 8

MOSFET remains in the saturation mode? The MOSFET has


Vtp 1 V and k p W L 1 mA/V2. Neglect ro.

(Fig. 5.25)
For saturation in an enhancement type PMOS device requires
VGS Vtp (induced) or VSG Vtp (induced) (1)
and
VDS VGS Vtp (pinched off) (2)
In words, this last equation states that the drain-to-source
voltage must be less than the gate-to-source voltage plus |Vtp|.

When working with PMOS transistors, the negative Vtp and


other minus signs can sometimes cause confusion. So we can
use VSG in (1) for inducing the channel, and can multiply (2) for
a pinched off channel at the drain end (saturation mode) by -1
VDS VGS Vtp
and rearrange to read
VSD VGS Vtp VSG Vtp (pinched off) (3)

VOV p
Whites, EE 320 Lecture 27 Page 7 of 8

where
VOV p
VSG Vtp (4)
Equation (4) is only valid for a PMOS transistor that has an
induced channel [such that the RHS of (4) is a positive number,
as defined by the LHS].

Now, in the saturation mode (with 0 )


1 W
I D k p VGS Vtp
2
(5.28),(5)
2 L
1
0.5 103 1 103 VGS 1
2
or
2
Therefore, VGS 1 1 VGS 0 or -2 V.

The first result is not consistent with operation in the saturation


mode since VGS Vtp must be met for saturation. Consequently,
VG 5 VGS 5 2 3 V
RG1 and RG2 must be chosen such that
RG 2 3 RG 2
VG VS or
RG1 RG 2 5 RG1 RG 2
The text chooses RG1 2 M and RG 2 3 M to satisfy this
requirement. (Why did the book use such large values for RG1
and RG2?)

The drain resistor can be determined from the circuit above


3
RD k 6 k
0.5
Whites, EE 320 Lecture 27 Page 8 of 8

For the largest RD, remember that the PMOS device remains in
the saturation mode as long as the drain end of the channel is
pinched off.

VSG Vtp VDG Vtp

Channel pinch off at the drain end requires


VDG Vtp (pinched off)
which holds up to the point where VD exceeds VG by Vtp . That
is,
VDmax VG Vtp 3 1 4 V.
From this result,
VDmax 4V
RDmax 8 k.
ID 0.5 mA