Results DAC (20150512)

DAC section:

1) Specifications
Resolution: 4-Bit (R-2R) Ladder DAC
Component Tolerances:- 1% for Resistors
R-2R Advantage is only two values of resistors required (R=10 k, 1% and 2R=20 k, 1%)
Rail to Rail OPAMPs used (MCP6024)
FSR Full Scale Output of 5V

2) Test Setup for Static Transfer Characteristic

3) Conversion of digital data to analogue signals

FSR Full Scale Range is defined as :

The full scale range is the difference between the output levels ideally corresponding to the minimum
and maximum input codes. It can be expressed either as a voltage or a current.
The practical full scale range is the difference between the most positive and most negative analog
outputs that can be achieved from the converter. It can be expressed either as a voltage or a current.

The voltage regulator (7805) was configured with transistors one of which connected as a diode in order to
compensate the variation of the VBE with temperature and the +5V supply was used as a reference voltage and to
power the rail to rail opamps. The output of the DAC stage was configured with a non-inverting amplifier with gain
of approximately 1.066 to provide an ADC with a FSR of 5.0 V measured with an input code word of 1111.

To achieve a FSR of 5V a reference Voltage of 5.33V is required. The current reference used is +5V
and a gain of approximately 1.066 has been introduced to create a FSR of +5V.
Table 1: Summary of DAC Results Table:
Design Simulation Practical
Device LSB = 0.333125000 0.331793333 0.337333333
Max/Min INL 0.00 -0.025 0.057
Max/Min DNL 0.00 0.025 0.038
Offset Error 0.00 0.01 -0.06
Gain Error (zero offset) 7.14% 7.12% 7.23%
Gain Error (incl offset) 7.14% 6.84% 8.52%
Note: Refer to the Annexure A for the detailed results for design, simulated and practical

The results for Design, Simulation and Practical Measurement and comparisons between them are
discussed in the following sections:

Linearity Error
0.08
0.06
0.04
DNL_P
0.02
INL_P
LSB

0
DNL_D
-0.02
INL_D
-0.04
DNL_S
-0.06
INL_S
-0.08
0 2 4 6 8 10 12 14
Codes

Figure 1: Comparison of INL and DNL for Design, Simulation and Practical Results

3) Integral Nonlinearity (INL of the DAC )

Integral nonlinearity (INL) is the difference between the code centers from the ideal line. INL can also
be specified as the sum of DNLs. Additionally, INL can be defined as the distance of the code centers
with the best fit line.

The Integral Nonlinearity (INL) Results for Design versus Simulation versus Practical Measurement
are shown in Figure 1 above. The INL for the Design was calculated as zero LSB, and the maximum
absolute INL value for simulation is 0.025 LSB, and the maximum absolute INL result for practical
unit was measured and found to be 0.057 LSB. All values (design, simulated and practical) are less than
0.1 LSBs which suggests that the practical unit exhibits a very good INL value.

4) Differential Nonlinearity (DNL of the DAC)

Deviation of the code transition width from the ideal one (1 LSB) is called differential nonlinearity
(DNL). For narrow code width, DNL is negative while for the wide one DNL is positive. In an ideal
ADC the code width is always one, thus, DNL is zero.

The Differential Nonlinearity (DNL) Results for Design versus Simulation versus Practical
Measurement are shown in Figure 1 above. The DNL for the Design is zero LSB, and the maximum
absolute Simulation DNL result is 0.025 LSB, and the maximum practical absolute DNL result was
found to be 0.038 LSB. All values (design, simulated and practical) are less than 0.1 LSBs and the
practical unit exhibits a very good DNL value.

5) Offset error of the DAC

The offset error can be measured by applying the all "0"s code to the DAC and measuring
the output deviation from 0 volts.

The design offset error is ideal (zero volts), and the simulated offset error with all zero code applied
was found to be 0.01 volts. The offset error for the practical unit was initially measured as 0.01 volts,
however to create a +5V stable reference the voltage regulator (7805) was configured with transistors
one of which connected as a diode in order to compensate the variation of the VBE with temperature
and the +5V supply was used as a reference voltage and to power the rail to rail opamps. Following
this adjustment the practical unit offset error was measured as -0.06 volts.

6) Gain error of the DAC

The ideal transfer function has a slope defined by drawing a straight line through the two end points.
The slope represents the gain of the transfer function. In non-ideal DACs, this slope can differ from
the ideal, resulting in a gain errorwhich is usually expressed as a percent because it affects each
code by the same percentage. If there is no offset error, gain error is easily determined by
applying the all "1"s code to the DAC and measuring its output.

From Table 1 above, the design offset error (zero offset) and design gain error (including offset) was
found to be 7.12%. The simulated gain error (zero offset) and simulated gain error (including offset)
was found to be 7.12% and 6.84% respectively, and the practical gain error (zero offset) and practical
gain error (including offset) was found to be 7.23% and 8.52% respectively. The circuit was designed
for a FSR (Full scale range) of +5V which requires a Vref of 5.33V. A reference voltage of 5V was
used and a gain of approx. 1.066 was introduced to create a FSR = 5 which has caused the gain error.
 Annexure A: Design, Simulation and Practical Results

Theoretical/Ideal Calculations
b3 b2 b1 b0 Theoretical T_Segment DNL_D INL_D
0 0 0 0 0 0.00 0 0
1 0 0 0 1 0.33 0.33 0.000000 0
2 0 0 1 0 0.67 0.33 0.000000 0
3 0 0 1 1 1.00 0.33 0.000000 0
4 0 1 0 0 1.33 0.33 0.000000 0
5 0 1 0 1 1.67 0.33 0.000000 6.6655E-16
6 0 1 1 0 2.00 0.33 0.000000 0
7 0 1 1 1 2.33 0.33 0.000000 0
8 1 0 0 0 2.67 0.33 0.000000 0
9 1 0 0 1 3.00 0.33 0.000000 1.3331E-15
10 1 0 1 0 3.33 0.33 0.000000 1.3331E-15
11 1 0 1 1 3.66 0.33 0.000000 0
12 1 1 0 0 4.00 0.33 0.000000 0
13 1 1 0 1 4.33 0.33 0.000000 0
14 1 1 1 0 4.66 0.33 0.000000 0
15 1 1 1 1 5.00 0.33 0.000000 0

Simulation Results
b3 b2 b1 b0 Simulated S-Segment DNL_S INL_S
0 0 0 0 0 0.01 0.000000 0.000000
1 0 0 0 1 0.34 0.33 -0.002692 -0.002692
2 0 0 1 0 0.68 0.33 -0.002391 -0.005083
3 0 0 1 1 1.01 0.34 0.009665 0.004581
4 0 1 0 0 1.34 0.33 -0.005405 -0.000824
5 0 1 0 1 1.67 0.33 -0.005405 -0.006229
6 0 1 1 0 2.00 0.33 -0.005405 -0.011634
7 0 1 1 1 2.33 0.33 -0.005405 -0.017039
8 1 0 0 0 2.66 0.33 -0.005405 -0.022444
9 1 0 0 1 3.00 0.34 0.024734 0.002291
10 1 0 1 0 3.33 0.33 -0.005405 -0.003114
11 1 0 1 1 3.66 0.33 -0.005405 -0.008519
12 1 1 0 0 3.99 0.33 -0.005405 -0.013924
13 1 1 0 1 4.32 0.33 -0.005405 -0.019329
14 1 1 1 0 4.65 0.33 -0.005405 -0.024734
15 1 1 1 1 4.99 0.34 0.024734 0.000000
Practical Unit Results
b3 b2 b1 b0 Practical P_Segment DNL_P INL_P
0 0 0 0 0 -0.06 0 0
1 0 0 0 1 0.27 0.33 -0.02173913 -0.02173913
2 0 0 1 0 0.61 0.34 0.007905138 -0.013833992
3 0 0 1 1 0.95 0.34 0.007905138 -0.005928854
4 0 1 0 0 1.28 0.33 -0.02173913 -0.027667984
5 0 1 0 1 1.62 0.34 0.007905138 -0.019762846
6 0 1 1 0 1.96 0.34 0.007905138 -0.011857708
7 0 1 1 1 2.3 0.34 0.007905138 -0.003952569
8 1 0 0 0 2.64 0.34 0.007905138 0.003952569
9 1 0 0 1 2.99 0.35 0.037549407 0.041501976
10 1 0 1 0 3.33 0.34 0.007905138 0.049407115
11 1 0 1 1 3.67 0.34 0.007905138 0.057312253
12 1 1 0 0 3.99 0.32 -0.051383399 0.005928854
13 1 1 0 1 4.32 0.33 -0.02173913 -0.015810277
14 1 1 1 0 4.66 0.34 0.007905138 -0.007905138
15 1 1 1 1 5 0.34 0.007905138 0
Results DAC (20150511)
ADC section:
1) Conversion of analogue signals to digital data

Successive Approximation Register (SAR) Algorithm

In terms of the Nyquist Sampling Theorem f(sample) >= 2 f(baseband). The Aperture Uncertainty is
+/- 1 Clock cycle (Tclk). For a 66 Khz clock (Tclk = 15.15us) and the maximum frequency of the input
signal due to Aperture Uncertainty is approximately 660Hz.

The slew rate of the MCP6024 OPAMP is typically 7V/us. For a sinusoidal signal that passes through a
unity gain follower the maximum frequency is determined from the formula (SR = *Vo) which
yields an input signal with a maximum frequency of 222,817 Hz.

2) Specifications
Resolution = 4 bits
Type: Successive approximation register
reference voltage 5 V
FSR input of 5 V
 1111 Quantisation Error
1110
1101
ADC Output
1100
1011
1010
OUTPUT 1001
DIGITAL 1000
WORD 0111 2 3 4 5 6 7 8 9 10 11 12 13 TIME
0110
0101 Input Sinewave
0100
0011
0010
0001
0000

4-bit (16 level) ADC sampling a sinewave input, time domain

Table 2: Summary of ADC Results Table:

Design Practical
Device LSB = 0.312500000 0.314666667
Max/Min INL 0.00 -0.347
Max/Min DNL 0.00 -0.237
Offset Error 0.00 0.08
Gain Error (zero offset) 7.14% 7.02%
Gain Error (incl offset) 7.14% 5.23%
Note: Refer to the Annexure B for the detailed results for design and practical
The results for Design and Practical Measurement and comparisons between them are discussed in the
following sections:

Linearity Error
0.5
0.4
0.3
0.2
0.1
LSB

0
INL_P
-0.1
-0.2 DNL_P
-0.3
-0.4
-0.5
0 2 4 6 8 10 12 14
Codes

Figure 2: Comparison of INL and DNL for Design and Practical Results

3) INL of the ADC

Integral nonlinearity (INL) is the difference between the code centers from the ideal line. INL can also
be specified as the sum of DNLs. Additionally, INL can be defined as the distance of the code centers
with the best fit line.

The Integral Nonlinearity (INL) Results for Design versus Practical Measurement are shown in Figure
2 and Table 2 above. The INL for the Design was calculated as zero LSB, and the maximum absolute
INL result for practical unit was measured and found to be 0.347 LSB. The practical value is less than
0.4 LSBs which suggests that the practical unit exhibits a reasonable INL value.

4) DNL of the ADC

Deviation of the code transition width from the ideal one (1 LSB) is called differential nonlinearity
(DNL). For narrow code width, DNL is negative while for the wide one DNL is positive. In an ideal
ADC the code width is always one, thus, DNL is zero.

The Differential Nonlinearity (DNL) Results for Design versus Practical Measurement are shown in
Figure 2 and Table 2above. The DNL for the Design is zero LSB and the maximum practical absolute
DNL result was found to be 0.237 LSB. The maximum practical value is less than 0.3 LSBs.

5) Offset error of the ADC

The practical offset error is 80 mV, the voltage that corresponds to the minimum code word.

6) Gain error of the ADC

From Table 2 above, the design offset error (zero offset) and design gain error (including offset) was
found to be 7.12%. The practical gain error (zero offset) and practical gain error (including offset)
was found to be 7.02% and 5.23% respectively.

7) Conversion time of ADC

Every A/D conversion is made up of a sample or tracking period and a conversion period. The terms
track and hold and sample and hold are sometimes interchanged, although most serial ADCs are
track and hold devices. The period of time when the input signal is sampled or tracked is the Sample
Time. (Can be measured in number of clock cycles)
Conversion Time is the time required to convert the sampled input signal to a digital word.
(Can also be measured in time or number of clock cycles)

From the time Go is synchronously detected it

takes one clock cycle to Sample and Hold, and four
(4) more clock periods to reset the ADC and do the
conversion with one additional clock cycle to
synchronously clock out the EOC signal.

For a 66 Khz sample clock with a period (Tclk =

15.15us) the Sample Time is 15.15us. The
Conversion Time is 60.6us. The total Sample and
Conversion Time is 75.75us.

8) ENOB of the ADC

(Effective Number of Bits) is a global indication of ADC accuracy at a specific input frequency and
sampling rate. Prior to computing the ENOB several other parameters are calculated.

SIGNAL TO NOISE RATIO

SNR is the ratio of RMS signal amplitude to the RMS output noise for a specific input frequency and
amplitude, excluding harmonic noise. The ideal theoretical SNR is equal to (6.02n + 1.76 dB), where
n = number of bits. For a four (4) bit ADC the ideal SNR = 25.84 dB.

Figure 3: FFT of 660Hz sinusoidal sampled at 66kHz

Figure 4: FFT of 1kHz sinusoidal sampled at 132kHz

The SNR was computed using the following formula:

Using an Input signal with a frequency of f = 1 kHz and peak to peak amplitude of +5V sampled at
132 kHz, Signal/Noise Floor was found to be 37dB and the SNR is 18.80 dB.
(37dB - 10*LOG10((132000/2)/1000) .

SPURIOUS FREE DYNAMIC RANGE (SFDR)

The spurious free dynamic range (SFDR) is the ratio of the input signal to the peak spurious harmonic
component. Using an Input signal with a frequency of f = 1 kHz and peak to peak amplitude of +5V
sampled at 132 kHz, the SFDR was found to be 20 dB.

TOTAL HARMONIC DISTORTION

The THD was calculated from the measurements using the following formula:
 Freq dB Gain THD (dB)
f1 3.6 1.5135612
f2 -15.2 0.1737801
f3 -17.6 0.1318257
f4 -20.8 0.0912011 -15.50
f5 -24.4 0.060256
f6 -24.4 0.060256
f7 -28.4 0.0380189
The THD was found to be -15.50 dB for an input signal with a frequency of f = 660Hz and
peak to peak amplitude of +5V sampled at 66 kHz.

1kHz input/sampling freq 132kHz

Freq dB Gain THD (dB)
f1 2.8 1.380384265
f2 -17.2 0.138038426
f3 -22 0.079432823 -18.49
f4 -28 0.039810717

The THD was found to be -18.49 dB for an input signal with a frequency of f = 1kHz and
peak to peak amplitude of +5V sampled at 132 kHz.

SIGNAL TO NOISE AND DISTORTION RATIO (SINAD)

SINAD is the ratio of RMS signal amplitude to the RMS sum of the noise and distortion products for
a specific input frequency and amplitude

SINAD was computed and found to be 15.50 dB for an input signal with a frequency of f =
600Hz and peak to peak amplitude of +5V sampled at 66 kHz.

EFFECTIVE NUMBER OF BITS (ENOB)

ENOB is a measurement of the resolution of the ADC and is directly related to Signal to
Noise+Distortion (SINAD).

ENOB was computed using the following formula: ENOB = [SINAD - 1.76]/6.02. The ENOB for a
input signal with a frequency of f = 660Hz and peak to peak amplitude of +5V sampled at 66 kHz was
found to be 2.28.
 Annexure B: ADC Design and Practical Results

ADC (theoretical) Gain= Unity 1 Design Ideal Results

b3 b2 b1 b0 voltage w ideal DNL_D INL_D
0 0 0 0 0 0.00 0 0.000000
1 0 0 0 1 0.31 0.31 0.0000 0.000000
2 0 0 1 0 0.63 0.31 0.0000 0.000000
3 0 0 1 1 0.94 0.31 0.0000 0.000000
4 0 1 0 0 1.25 0.31 0.0000 0.000000
5 0 1 0 1 1.56 0.31 0.0000 0.000000
6 0 1 1 0 1.88 0.31 0.0000 0.000000
7 0 1 1 1 2.19 0.31 0.0000 0.000000
8 1 0 0 0 2.50 0.31 0.0000 0.000000
9 1 0 0 1 2.81 0.31 0.0000 0.000000
10 1 0 1 0 3.13 0.31 0.0000 0.000000
11 1 0 1 1 3.44 0.31 0.0000 0.000000
12 1 1 0 0 3.75 0.31 0.0000 0.000000
13 1 1 0 1 4.06 0.31 0.0000 0.000000
14 1 1 1 0 4.38 0.31 0.0000 0.000000
15 1 1 1 1 4.69 0.31 0.0000 0.000000

ADC (theoretical) Gain= Unity Practical Unit Results

b3 b2 b1 b0 non ideal voltages w non ideal DNL_P INL_P
0 0 0 0 0 0.08 0
1 0 0 0 1 0.32 0.24 -0.237288136 -0.23729
2 0 0 1 0 0.6 0.28 -0.110169492 -0.34746
3 0 0 1 1 0.92 0.32 0.016949153 -0.33051
4 0 1 0 0 1.24 0.32 0.016949153 -0.31356
5 0 1 0 1 1.56 0.32 0.016949153 -0.29661
6 0 1 1 0 1.92 0.36 0.144067797 -0.15254
7 0 1 1 1 2.24 0.32 0.016949153 -0.13559
8 1 0 0 0 2.56 0.32 0.016949153 -0.11864
9 1 0 0 1 2.88 0.32 0.016949153 -0.10169
10 1 0 1 0 3.16 0.28 -0.110169492 -0.21186
11 1 0 1 1 3.52 0.36 0.144067797 -0.0678
12 1 1 0 0 3.8 0.28 -0.110169492 -0.17797
13 1 1 0 1 4.12 0.32 0.016949153 -0.16102
14 1 1 1 0 4.48 0.36 0.144067797 -0.01695
15 1 1 1 1 4.8 0.32 0.016949153 0
 Schematics and Simulation

ADC and DAC Schematic captured in Proteus Professional

Simulation of Sample and Hold with increasing code word

DAC Simulation