Two Stage Amplifier

Robert Tac-an Nericua BSECE-IV ECE 126 A8
Two Stage Amplifier

Lab 4
ECE 126
Introduction to Analog CMOS IC
Design
Submitted by:
Robert Tac-an Nericua
Submitted to:
Prof. Allenn dela Cerna Lowaton
ECE 126 Introduction to Analog CMOS IC Design

Lab 4 Page 1
Introduction
In this modern age, electronic systems are very common to our everyday lives. One of the most
important electronic systems is an electronic amplifier which is very dominant especially in wireless
communications, broadcasting, instrumentation and all kinds of audio equipment. An electronic
amplifier is an electronic device that increases the voltage, current, or power of a signal.
It does this by taking energy from a power supply and controlling the output to match the input
signal shape but with a larger amplitude. In this sense, an amplifier modulates the output of the power
supply to make the output signal stronger than the input signal. An amplifier is effectively the opposite
of an attenuator: while an amplifier provides gain, an attenuator provides loss.
In the previous laboratory activities we only deal with single stage amplifiers. In this laboratory
activity we will explore and deal with two stage amplifier. This amplifier obviously has two stages in
amplifying signals. For this activity we will focus on the behavior of a two stage amplifier on the
following parameters: gain, bandwidth, Phase Margin, ICMR (Input Common Mode Range), output
voltage swing, CMRR (Common Mode Rejection Ratio), Slew Rate and Setting Time.
The definition of the above parameters is listed below:
Gain- the ratio between the magnitude of output and input signal
Bandwidth- the width of the useful frequency range
Phase Margin- is the difference between the phase, measured in degrees, and 180, for
an amplifier's output signal (relative to its input), as a function of frequency
ICMR (Input Common Mode Range)- the range of the input common mode voltage
Output Voltage Swing- the range of output voltage which can operate normally
CMRR (Common Mode rejection Ratio)-the ability of rejecting common mode signal
Slew Rate-the maximum rate of change of the output
Setting Time-the time during output signal is stable.
We will simulate the circuit for this laboratory activity using HSPICE A-2008.03 by Synopsys. The
model that we are going to use in this laboratory activity is a TSMC (Taiwan Semiconductor
Manufacturing Company, Limited) RF Spice Model of 0.18m Mixed Signal SALICIDE (1P6M+, 1.8V/3.3v)
Process.
Below are the circuits that we will be using in this laboratory activity.

Lab 4 Page 2

Lab 4 Page 3
Objectives
The following are the objectives of this laboratory activity:
a. To be able to simulate the differential amplifier and two stage amplifier respectively and
compare the gain, -3dB frequency and Gain Bandwidth;
b. To be able to simulate the two stage amplifier configured as unit gain buffer and observe the
stability and output waveform;
c. To be able to simulate the effect of phase margin when adding compensation capacitor to the
two stage amplifier;
d. To be able to simulate and observe the effect of phase margin with varying compensation
capacitor in the two stage amplifier and also the effect of the compensation capacitor to slew
rate;
e. To be able to simulate and observe the effect after adding a compensation resistor in the
capacitor compensated-two stage amplifier; and ,
f. To answer the end questions attached to this laboratory activity at the end of the Spice
simulations.
This activity is in line with the following course outcomes of BSECE:

1. The student can design a system, component, or process to meet desired needs within
identified constraints.
2. The student can recognize, formulate and solve engineering problems.
3. The student will have the ability to use the skills, techniques and modern engineering tools
necessary for engineering practice.
Laboratory Procedures
In doing the simulation for this laboratory activity the following procedures are to be
performed:
1. Following the circuit below, simulate differential amplifier and two stage amplifier respectively
and compare the gain, -3dB and Gain Bandwidth.

Lab 4 Page 4
2. Connect the two stage amplifier as a unit gain buffer, simulate it and observe the stability and
output waveform.
3. Following the circuit below, simulate the effect of phase margin when adding compensation
capacitor.
4. Vary the value of the compensation capacitor to observe the effect to phase margin and also to
observe the effect to slew rate.
5. Following the circuit below, observe the effect after adding a compensated resistor.

Lab 4 Page 5
Results and Discussions

These are the results and discussions when performing the following steps of the Laboratory
Procedures:
For Step 1.
Following the circuit given in step 1 we have generated the following code.
ece 126 lab 4 two_stage_amplifier_Nericua_step1.sp In this simulation we introduce a new .meas command.
.option post probe
.meas allows us to measure the numerical value that we need
.lib 'C:\synopsys\Hspice_A-2008.03\library\rf018.l' tt such voltage, current, power, frequency etc. Take .meas ac
m1 vx vin+ v2 gnd nch l=1u w=5u
GB_vx when Vdb(Vx)=0 as an example. This line of code will
allow us to determine the value of the frequency in which
m2 v1 vin- v2 gnd nch l=1u w=5u
VdB is equal to zero.
m3 vdd v1 v1 vdd pch l=1u w=11u
m4 vdd v1 vx vdd pch l=1u w=11u
m5 v2 v3 gnd gnd nch l=1u w=10u
m6 vdd vx vout vdd pch l=1u w=66u
m7 vout v3 gnd gnd nch l=1u w=30u
iref vdd v3 8u
vdd vdd gnd 1.8
vin+ vin+ gnd dc 0.7 ac 1
vin- vin- gnd dc 0.7 ac 0
cl vout gnd 10p
.op
.ac dec 100 10 10g
.probe ac vdb(vout) vdb(vx) vp(vout)
.meas ac GB_vout when Vdb(Vout)=0
.meas ac GB_vx when Vdb(Vx)=0
.end

Lab 4 Page 6
The result of the simulation is attached below:
Two Stage Amp
Differential Amp
The blue trace is the VdB(vout) while the other one is VdB(Vx) which is in green trace.
Gain -3dB Gain Bandwidth

Two Stage Amp 84.3dB 17.7kHz 11.956MHz
Differential Amp 43.1dB 21kHz 24.889MHz
From the simulation result, the performance of a Two Stage Operational Amplifier is better than
Differential Amplifier.
Below is the result of the .op

Lab 4 Page 7
For Step 2.
ece 126 lab 4 two_stage_amplifier_Nericua_step2.sp iref vdd v3 8u In this simulation we introduce a

.option post probe vdd vdd gnd 1.8 new transient source, a piecewise
linear source having a syntax of
.lib 'C:\synopsys\Hspice_A-2008.03\library\rf018.l' tt vin+ vin+ gnd pwl(199ns 0 200ns 1 3u 1)
pwl(t1 v1 t2 v2 t3 v3 t4 v4 ...) where
m1 vx vin+ v2 gnd nch l=1u w=5u cl vout gnd 10p t1 is the first instance that the
m2 v1 vout v2 gnd nch l=1u w=5u .op
voltage is v1, and linearly increasing
to t2 until reach v2 and so on.
m3 vdd v1 v1 vdd pch l=1u w=11u .plot tran v(vout) v(vin+) vp(vout)
Take pwl(199ns 0 200ns 1 3u 1) as
m4 vdd v1 vx vdd pch l=1u w=11u .tran 1ns 2us
an example. From time 0 to 199ns
m5 v2 v3 gnd gnd nch l=1u w=10u .end the value of the voltage is 0 and
m6 vdd vx vout vdd pch l=1u w=66u from time 200ns to 3us the value of
the voltage is 1V.

Lab 4 Page 8
The result of the simulation is attached below.
If we connect the circuit as a unit gain buffer, we can see from the simulation result that phase
margin < 0, so it will become an unstable system, In fact, the typical value of phase margin must be
larger than 45 to form a stable system.

Lab 4 Page 9
For Step 3.
ece 126 lab 4 two_stage_amplifier_Nericua_step3.sp
.option post probe
.lib 'C:\synopsys\Hspice_A-2008.03\library\rf018.l' tt
m2 v1 vin- v2 gnd nch l=1u w=5u
iref vdd v3 8u
vdd vdd gnd 1.8
vin_ vin- gnd dc 0.7 ac 0
cl vout gnd 10p
.op
.ac dec 100 10 10g
.probe ac vdb(vout) vdb(vx) vp(vout)
.meas ac GB_vout when Vdb(Vout)=0
.meas ac GB_vx when Vdb(Vx)=0
.alter
cc vx vout 2p
.end

Lab 4 Page 10
Without CC
CC=2pF (gain)
Without CC
CC=2pF (Phase)
The result of the .op with CC is attached below.

Lab 4 Page 11
For Step 4.
Following the circuit given in step 3 having different CC we have generated the following code.
ece 126 lab 4 two_stage_amplifier_Nericua_step4.sp .op
.option post probe .ac dec 100 10 10g
.lib 'C:\synopsys\Hspice_A-2008.03\library\rf018.l' tt .probe ac vdb(vout) vdb(vx) vp(vout)
m1 vx vin+ v2 gnd nch l=1u w=5u .meas ac GB_vout when Vdb(Vout)=0
m2 v1 vin- v2 gnd nch l=1u w=5u .meas ac GB_vx when Vdb(Vx)=0
m3 vdd v1 v1 vdd pch l=1u w=11u .alter
m4 vdd v1 vx vdd pch l=1u w=11u cc vx vout 2p
m5 v2 v3 gnd gnd nch l=1u w=10u .alter
m6 vdd vx vout vdd pch l=1u w=66u cc vx vout 4p
m7 vout v3 gnd gnd nch l=1u w=30u .alter
m8 v3 v3 gnd gnd nch l=1u w=10u cc vx vout 6p
iref vdd v3 8u .end
vdd vdd gnd 1.8
vin- vin- gnd dc 0.7 ac 0
cl vout gnd 10p

Lab 4 Page 12
CC=6pF (Gain)
CC=4pF (Gain)
CC=2pF (Gain)
CC=6pF (phase)
CC=4pF (phase)
CC=2pF (phase)
ece 126 lab 4 two_stage_amplifier_Nericua_step4.1.sp cl vout gnd 10p
.option post probe .op
.lib 'C:\synopsys\Hspice_A-2008.03\library\rf018.l' tt .plot tran v(vout)
m1 vx vin+ v2 gnd nch l=1u w=5u .tran 100ns 3us
m2 v1 vout v2 gnd nch l=1u w=5u .alter
m3 vdd v1 v1 vdd pch l=1u w=11u cc vx vout 2p
m4 vdd v1 vx vdd pch l=1u w=11u .alter
m5 v2 v3 gnd gnd nch l=1u w=10u cc vx vout 4p
m6 vdd vx vout vdd pch l=1u w=66u .alter
m7 vout v3 gnd gnd nch l=1u w=30u cc vx vout 6p
m8 v3 v3 gnd gnd nch l=1u w=10u .end
iref vdd v3 8u
vdd vdd gnd 1.8
vin+ vin+ gnd pwl(199ns 0 200ns 1 3us1)

Lab 4 Page 13
We can see that while the CC increases the phase margin also increases and decrease the slew
rate, because the larger CC needs more time to charge or discharge.
For Step 5.
Following the circuit given in step 3 having different CC we have generated the following code
ece 126 lab 4 two_stage_amplifier_Nericua_step5.sp vdd vdd gnd 1.8 rc vx vcr 1.234k
.option post probe vin+ vin-+ gnd dc 0.7 ac 1 .end
.lib 'C:\synopsys\Hspice_A-2008.03\library\rf018.l' tt vin- vin- gnd dc 0.7 ac 0
m1 vx vin+ v2 gnd nch l=1u w=5u cl vout gnd 10p
m2 v1 vin- v2 gnd nch l=1u w=5u cc vcr vout 2p
m3 vdd v1 v1 vdd pch l=1u w=11u rc vx vcr 0
m4 vdd v1 vx vdd pch l=1u w=11u .op
m5 v2 v3 gnd gnd nch l=1u w=10u .ac dec 100 10 10g
m6 vdd vx vout vdd pch l=1u w=66u .probe ac vdb(vout) vdb(vx) vp(vout)
m7 vout v3 gnd gnd nch l=1u w=30u .meas ac GB_vout when Vdb(Vout)=0
m8 v3 v3 gnd gnd nch l=1u w=10u .meas ac GB_vx when Vdb(Vx)=0
iref vdd v3 8u .alter

Lab 4 Page 14
Let RC=6k.
The result of the simulation is also attached below.

Lab 4 Page 15
For simulation of the Input Common Mode Range, the following code is implemented.
ece 126 lab 4 two_stage_amplifier_Nericua_step5.1icmr.sp
.option post probe
.lib 'C:\synopsys\Hspice_A-2008.03\library\rf018.l' tt
m2 v1 vout v2 gnd nch l=1u w=5u
cl vout gnd 10p
iref vdd v3 8u
vdd vdd gnd 1.8
vin+ vin+ gnd dc 0.7
.op
.dc vin+ 0 1.8 0.001
.probe v(vout) i(m2)

T
.end

Lab 4 Page 16
Questions
1. Why do we use Common Source structure as the output stage of Two-Stage Operational
Amplifier? What if we use the other structures?
Common Source configuration is being used because it will produce a very large voltage gain as
compared to other configurations. Common Drain has a dc gain of less than unity while the Common
Gate provides a positive dc gain but a function of its body-effect
Conclusion
I hereby conclude that I have performed the following:
a. Simulated the differential amplifier and two stage amplifier respectively and compared the gain,
-3dB frequency and Gain Bandwidth;
b. Simulated the two stage amplifier configured as unit gain buffer and observed the stability and
output waveform;
c. Simulated the effect of phase margin when adding compensation capacitor to the two stage
amplifier;
d. Simulated and observed the effect of phase margin with varying compensation capacitor in the
two stage amplifier and also the effect of the compensation capacitor to slew rate;
e. Simulated and observed the effect after adding a compensation resistor in the capacitor
compensated-two stage amplifier; and,
f. Answered the end question attached in this laboratory activity at the end of the Spice
simulations.

Lab 4 Page 17

Two Stage Amplifier

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Robert Tac-an Nericua BSECE-IV ECE 126 A8

Two Stage Amplifier

ECE 126 Introduction to Analog CMOS IC Design

The definition of the above parameters is listed below:

ECE 126 Introduction to Analog CMOS IC Design

ECE 126 Introduction to Analog CMOS IC Design

This activity is in line with the following course outcomes of BSECE:

ECE 126 Introduction to Analog CMOS IC Design

ECE 126 Introduction to Analog CMOS IC Design

Results and Discussions

m4 vdd v1 vx vdd pch l=1u w=11u

m5 v2 v3 gnd gnd nch l=1u w=10u

m6 vdd vx vout vdd pch l=1u w=66u

m7 vout v3 gnd gnd nch l=1u w=30u

m8 v3 v3 gnd gnd nch l=1u w=10u

vdd vdd gnd 1.8

vin+ vin+ gnd dc 0.7 ac 1

vin- vin- gnd dc 0.7 ac 0

cl vout gnd 10p

.ac dec 100 10 10g

.probe ac vdb(vout) vdb(vx) vp(vout)

.meas ac GB_vout when Vdb(Vout)=0

.meas ac GB_vx when Vdb(Vx)=0

ECE 126 Introduction to Analog CMOS IC Design

The result of the simulation is attached below:

Two Stage Amp

Gain -3dB Gain Bandwidth

Below is the result of the .op

ECE 126 Introduction to Analog CMOS IC Design

ece 126 lab 4 two_stage_amplifier_Nericua_step2.sp iref vdd v3 8u In this simulation we introduce a

m8 v3 v3 gnd gnd nch l=1u w=10u

ECE 126 Introduction to Analog CMOS IC Design

The result of the simulation is attached below.

ECE 126 Introduction to Analog CMOS IC Design

.option post probe

m1 vx vin+ v2 gnd nch l=1u w=5u

m2 v1 vin- v2 gnd nch l=1u w=5u

m3 vdd v1 v1 vdd pch l=1u w=11u

m4 vdd v1 vx vdd pch l=1u w=11u

m5 v2 v3 gnd gnd nch l=1u w=10u

m6 vdd vx vout vdd pch l=1u w=66u

m7 vout v3 gnd gnd nch l=1u w=30u

m8 v3 v3 gnd gnd nch l=1u w=10u

vdd vdd gnd 1.8

vin+ vin+ gnd dc 0.7 ac 1

vin_ vin- gnd dc 0.7 ac 0

cl vout gnd 10p

.ac dec 100 10 10g

.probe ac vdb(vout) vdb(vx) vp(vout)

.meas ac GB_vout when Vdb(Vout)=0

.meas ac GB_vx when Vdb(Vx)=0

ECE 126 Introduction to Analog CMOS IC Design

The result of the simulation is attached below.

The result of the .op with CC is attached below.

ECE 126 Introduction to Analog CMOS IC Design

ece 126 lab 4 two_stage_amplifier_Nericua_step4.sp .op

.option post probe .ac dec 100 10 10g

.lib 'C:\synopsys\Hspice_A-2008.03\library\rf018.l' tt .probe ac vdb(vout) vdb(vx) vp(vout)

m1 vx vin+ v2 gnd nch l=1u w=5u .meas ac GB_vout when Vdb(Vout)=0

m2 v1 vin- v2 gnd nch l=1u w=5u .meas ac GB_vx when Vdb(Vx)=0

m3 vdd v1 v1 vdd pch l=1u w=11u .alter

m4 vdd v1 vx vdd pch l=1u w=11u cc vx vout 2p

m5 v2 v3 gnd gnd nch l=1u w=10u .alter

m6 vdd vx vout vdd pch l=1u w=66u cc vx vout 4p