Advanced Arch 2011 PDF

History of Processor Performance

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1
Tuesday, April 24, 12


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3
Abstract Stages of Execution
Instruction Fetch
(Instructions fetched from memory into CPU)
Instruction Issue / Execution

(Instructions executed on ALU or other functional unit)
Instruction Completion / Commit

(Architectural state updated, i.e., regfile or memory)
4
Multiple Instruction Issue Processors
Multiple instructions fetched, executed, and committed in each cycle
F:
In superscalar processors instructions E:
are scheduled by the HW C:
In VLIW processors instructions are F:

E:
scheduled by the SW C:
In all cases, the goal is to exploit instruction-level parallelism (ILP)

5
Flynns Taxonomy
Single Instruction, Single Data (SISD) Single Instruction, Multiple Data (SIMD)
Multiple Instruction, Single Data (MISD) Multiple Instruction, Multiple Data (MIMD)
Exploits
instr-level
parallelism
(ILP)
Exploits data-level parallelism (DLP)
6
Out-of-order execution
In in-order execution, In out-of-order execution (OOO),
instructions are fetched, instructions are fetched, and
executed, and committed in committed in compiler, order; may be
compiler order executed in some other order
F: F: One stalls,
independent
One stalls, instrs may
they all stall proceed
E: E:
Relatively Additional
simple hardware
HW required for
C: C: reordering
Another way to exploit instruction-level parallelism (ILP)

7
Speculation
Speculation is executing an instruction before it is known that it
should be executed
Speculate If correct If incorrect
F: F: F:
Mis-
E: E: speculation
executes
E: excess
instructions,
C: C: costing time
and power
C:
8
The Memory Wall
a l l y
annu
Performance
2 0 %
25 -
ro x
a pp
as e
c re
e ds in
sp e lly
n n u a
C PU o x 2 - 11 % a
d s i n c rease appr
A M s p e e
D R
Time
A result of this gap is that cache design has increased in
importance over the years. This has resulted in
innovations such as victim caches and trace caches.
9
Modern Processor Performance
While single threaded performance has leveled, multithreaded performance potential scaling.


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10


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Source: Hennessy and Patterson, Computer Architecture: A Quantitative Approach


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5
Area Performance Power MIPS/Watt (%)
4

3
Increase

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The Power Wall

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12
Much of it goes back to the transistor
Source: Intel press foils

individual atoms!
Source: Intel press foils

individual atoms!
= leakage current +
defects Source: Intel press foils
A model of power
P = Pswitch + Pleakage
2
Pswitch = Eswitch x F = (C x Vdd ) x F
Pleakage = Vdd x I
Voltage Scaling: DVFS + Near-Threshold Computing
[Source: Dreslinski et al.: Near-Threshold Computing: Recplaiming Moores Law Through Energy Efficient Integrated Circuits]
Voltage Scaling: DVFS + Near-Threshold Computing
[Source: Dreslinski et al.: Near-Threshold Computing: Recplaiming Moores Law Through Energy Efficient Integrated Circuits]
Chip Area and Power Consumption
Power Density (Watts/cm2)
1500
Active Power
Leakage Power
1000
With leakage power dominating,
500
power envelope to remain constant
power consumption roughly
proportional to transistor count
0
90nm 65nm 45nm 32nm 22nm 16nm
Source: Shekhar Borkar (Intel)
1000
Integer Performance
100
Pollacks Law:
Processor performance grows
10 with sqrt of area
1
1 10 100 1000 10000 100000
Processor Area
Source: Shekhar Borkar (Intel)
The Resulting Shift to Multicore
Perf = 1
Power = 1

Perf = 1 Perf = 2
Power = 1 Power = 4

Perf = 1 Perf = 2 Perf = 4

Power = 1 Power = 4 Power = 4

Sea Change in Architecture: Multicore
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18
x86 64-bit Architecture Evolution
2003 2005 2007 2008 2009 2010

AMD AMD Barcelona Shanghai Istanbul Magny-Cours
Opteron Opteron
Mfg.
90nm SOI 90nm SOI 65nm SOI 45nm SOI 45nm SOI 45nm SOI
Process
K8 K8 Greyhound Greyhound+ Greyhound+ Greyhound+
CPU Core
L2/L3 1MB/0 1MB/0 512kB/2MB 512kB/6MB 512kB/6MB 512kB/12MB
Hyper
Transport 3x 1.6GT/.s 3x 1.6GT/.s 3x 2GT/s 3x 4.0GT/s 3x 4.8GT/s 4x 6.4GT/s
Technology
Memory 2x DDR1 300 2x DDR1 400 2x DDR2 667 2x DDR2 800 2x DDR2 1066 4x DDR3 1333
Max Power Budget Remains Consistent
3 | The AMD Magny-Cours Processor | Hot Chips | August 2009
[Source: HotChips 09] 19

Tick%Tock'Development'Model
Sandy
Merom Penryn Nehalem Westmere Bridge
NEW NEW NEW NEW NEW

Microarchitecture 1 Process Microarchitecture Process Microarchitecture
65nm 45nm 45nm 32nm 32nm
TOCK TICK TOCK TICK TOCK
Forecast
Nehalem-EX Architecture All products, dates, and figures are preliminary and
are subject to change without notice.
6 Hot Chips 2009

Nehalem'Core/Uncore'Modularity
C C C
O O O Core
R R R
E E E

L3 Cache
DRAM
Uncore
Power
IM QPI QPI &
C Clock
QPI

Common%core%for%client%and%server%CPUs
http://www.intel.com/technology/architecture<silicon/next<gen/whitepaper.pdf
Some%unique%features%only%on%NHM<EX
Uncore%differentiates%different%segment%specific%CPUs
Scalable%Core/Uncore%gasket%interface
Decouples%core%and%uncore%operation
Nehalem-EX Architecture
7 Hot Chips 2009

Nehalem'EX*CPU
Monolithic)single)die)CPU
8)Nehalem)cores,)16)threads
3MB*LLC 3MB LLC
24MB)shared)L3)cache
3MB*LLC 3MB*LLC 2)integrated)memory)controllers
Scalable)Memory)Interconnect)(SMI))with)
support)for)up)to)8)DDR)channels)
3MB*LLC 3MB*LLC 4)Quick)Path)Interconnect)(QPI))links)with)up)to))
6.4GT/s
3MB LLC 3MB*LLC
Supports)2,)4)and)8)socket)in)glueless)configs)
and)larger)systems)using)Node)Controller)(NC)
Intel)45nm)process)technology
2.3)Billion)transistors
Nehalem-EX Architecture
8 Hot Chips 2009

POWER7: IBMs Next Generation, Balanced POWER Server Chip
45nm
20+ Years of POWER Processors 65nm

Next Gen.
POWER7
RS64IV Sstar 130nm -Multi-core
POWER6TM
RS64III Pulsar 180nm -Ultra High Frequency
.18um
RS64II North Star POWER5TM
.25um
-SMT
RS64I Apache .35um
BiCMOS .5um
POWER4TM Major POWER Innovation
Muskie A35 .5um -Dual Core -1990 RISC Architecture
.22um
.5um -1994 SMP
-Cobra A10 -1995 Out of Order Execution
-64 bit
-1996 64 Bit Enterprise Architecture
POWER3TM -1997 Hardware Multi-Threading
.35um -630 -2001 Dual Core Processors
-2001 Large System Scaling
-2001 Shared Caches
.72um POWER2TM
-2003 On Chip Memory Control
P2SC -2003 SMT
.25um -2006 Ultra High Frequency
RSC -2006 Dual Scope Coherence Mgmt
.35um
1.0um -2006 Decimal Float/VSX
.6um -2006 Processor Recovery/Sparing
604e
-2009 Balanced Multi-core Processor
-603
POWER1 -2009 On Chip EDRAM
-AMERICAs
-601
1990 1995 2000 2005 2010

3 * Dates represent approximate processor power-on dates, not system availability

POWER7: IBMs Next Generation, Balanced POWER Server Chip
POWER7 Processor Chip
567mm2 Technology: 45nm lithography, Cu,

SOI, eDRAM
1.2B transistors
Equivalent function of 2.7B
eDRAM efficiency
Eight processor cores
12 execution units per core
4 Way SMT per core
32 Threads per chip
256KB L2 per core
32MB on chip eDRAM shared L3
Dual DDR3 Memory Controllers
100GB/s Memory bandwidth per chip
sustained
Scalability up to 32 Sockets
360GB/s SMP bandwidth/chip
20,000 coherent operations in flight
Advanced pre-fetching Data and Instruction
Binary Compatibility with POWER6
* Statements regarding SMP servers

do not imply that IBM will introduce
a system with this capability.
4

Challenges in Multicore
1. Performance dependent on parallel codes
2. Memory bandwidth 3. Communication and
(feeding the beast) coherence
[Source: Sandia NL]

25
Computer architecture: the long view

The Transistor
John Bardeen, Walter Brattain, William Shockley

Nobel Prize in Physics in 1965

The Integrated Circuit
Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Camera

2000 Nobel Prize in Physics

Technology:
Logic gates
SRAM
DRAM
Circuit technologies
Packaging
Magnetic storage
Flash memory
Biochips
3D stacking
[Credit: Milo Martin, UPenn]

Computing Devices

Technology:
Logic gates Application domains:
SRAM PCs
DRAM Servers
Circuit technologies PDAs
Packaging Mobile phones
Magnetic storage Supercomputers
Flash memory Game consoles
Biochips Embedded
3D stacking
[Credit: Milo Martin, UPenn]

Computing Applications

Technology:
SRAM PCs
DRAM Servers
Circuit technologies PDAs
Flash memory Game consoles
Biochips Embedded
3D stacking
Goals:
Functional
Performance
Reliability
Cost
Energy efficiency
Time to market [Credit: Milo Martin, UPenn]
Technology:
SRAM PCs
DRAM Servers
Circuit technologies Computer PDAs
architecture
Flash memory is at the Game consoles
Biochips intersection Embedded
3D stacking
Goals:
Functional
Performance
Reliability
Cost
Energy efficiency
Time to market [Credit: Milo Martin, UPenn]

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History of Processor Performance

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Instruction Issue / Execution

Instruction Completion / Commit

In VLIW processors instructions are F:

In all cases, the goal is to exploit instruction-level parallelism (ILP)

Exploits data-level parallelism (DLP)

Another way to exploit instruction-level parallelism (ILP)

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Source: Intel press foils

Source: Intel press foils

Source: Shekhar Borkar (Intel)

Tuesday, April 24, 12

Tuesday, April 24, 12

Perf = 1 Perf = 2 Perf = 4

Tuesday, April 24, 12

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2003 2005 2007 2008 2009 2010

L2/L3 1MB/0 1MB/0 512kB/2MB 512kB/6MB 512kB/6MB 512kB/12MB

Max Power Budget Remains Consistent

3 | The AMD Magny-Cours Processor | Hot Chips | August 2009

[Source: HotChips 09] 19

NEW NEW NEW NEW NEW

65nm 45nm 45nm 32nm 32nm

TOCK TICK TOCK TICK TOCK

[Source: HotChips 09] 20

[Source: HotChips 09] 21

[Source: HotChips 09] 22

20+ Years of POWER Processors 65nm

1990 1995 2000 2005 2010

[Source: HotChips 09] 23

POWER7 Processor Chip

567mm2 Technology: 45nm lithography, Cu,

* Statements regarding SMP servers

[Source: HotChips 09] 24

[Source: Sandia NL]

Tuesday, April 24, 12

John Bardeen, Walter Brattain, William Shockley

Tuesday, April 24, 12

Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Camera

Tuesday, April 24, 12

[Credit: Milo Martin, UPenn]

Tuesday, April 24, 12

[Credit: Milo Martin, UPenn]

Tuesday, April 24, 12

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