1359A
IRL2703
HEXFET Power MOSFET
l Logic-Level Gate Drive
l Advanced Process Technology D
l Dynamic dv/dt Rating VDSS = 30V
l 175C Operating Temperature
l Fast Switching RDS(on) = 0.04
G
l Fully Avalanche Rated
ID = 24A
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
device for use in a wide variety of applications.
Thermal Resistance
Parameter Min. Typ. Max. Units
RJC Junction-to-Case 3.3
RCS Case-to-Sink, Flat, Greased Surface 0.50 C/W
RJA Junction-to-Ambient 62
8/27/97
IRL2703
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Min. Typ.Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 30 V VGS = 0V, I D = 250A
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient 0.030 V/C Reference to 25C, I D = 1mA
0.040 VGS = 10V, ID = 14A
RDS(on) Static Drain-to-Source On-Resistance
0.060 VGS = 4.5V, I D = 12A
VGS(th) Gate Threshold Voltage 1.0 V VDS = VGS , ID = 250A
gfs Forward Transconductance 6.4 S VDS = 25V, I D = 14A
25 VDS = 30V, VGS = 0V
IDSS Drain-to-Source Leakage Current A
250 VDS = 24V, VGS = 0V, TJ = 150C
Gate-to-Source Forward Leakage 100 V GS = 16V
I GSS nA
Gate-to-Source Reverse Leakage -100 VGS = -16V
Qg Total Gate Charge 15 ID = 14A
Qgs Gate-to-Source Charge 4.6 nC VDS = 24V
Qgd Gate-to-Drain ("Miller") Charge 9.3 V GS = 4.5V, See Fig. 6 and 13
td(on) Turn-On Delay Time 8.5 VDD = 15V
tr Rise Time 140 I D = 14A
ns
td(off) Turn-Off Delay Time 12 RG = 12, VGS =4.5V
tf Fall Time 20 RD = 1.0, See Fig. 10
Between lead, D
LD Internal Drain Inductance 4.5
6mm (0.25in.)
nH G
from package
LS Internal Source Inductance 7.5
and center of die contact S
Notes:
Repetitive rating; pulse width limited by I SD 14A, di/dt 140A/s, VDD V(BR)DSS ,
max. junction temperature. ( See fig. 11 ) TJ 175C
VDD = 15V, starting TJ = 25C, L = 570H Pulse width 300s; duty cycle 2%.
RG = 25, IAS = 14A. (See Figure 12)
IRL2703
1000 1000
VGS VGS
TOP 15V TOP 15V
12V 12V
10V 10V
8.0V 8.0V
ID , D ra in -to -S o u rc e C u rre n t (A )
10 10
2.5V
1 1
2 .5V 2 0 s PU L SE W ID TH 2 0 s PU L SE W ID TH
T J = 2 5C T J = 1 75 C
0.1 A 0.1 A
0.1 1 10 100 0.1 1 10 100
V D S , Drain-to-S ource Voltage (V ) V D S , Drain-to-S ource Voltage (V )
100 2.0
I D = 24 A
R D S (o n ) , D ra in -to -S o u rc e O n R e si sta n ce
T J = 2 5 C
I D , D r ain- to-S ourc e C urre nt (A )
T J = 1 7 5 C 1.5
10
(N o rm a li ze d )
1.0
0.5
V DS = 1 5 V
2 0 s P U L S E W ID T H V G S = 10 V
0.1 0.0 A
A
2 3 4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
1000 15
V GS = 0 V, f = 1M H z I D = 14A
C is s = C gs + C gd , Cds SH OR TE D V DS = 2 4V
C rss = C gd
C i ss
C , C a p a c ita n c e (p F )
600 9
C o ss
400 6
C rs s
200 3
FO R TEST CIR CU IT
SEE FIG UR E 13
0 A 0 A
1 10 100 0 4 8 12 16 20
V D S , D rain-to-S ource Voltage (V ) Q G , T otal Gate C harge (nC )
100 1000
OPE R ATIO N IN TH IS A RE A LIMITE D
BY R D S(o n)
I S D , R e v e rse D ra in C u rre n t (A )
I D , D ra in C u rre n t (A )
TJ = 17 5C
100
10 s
TJ = 2 5C
10
10 0s
10
1 ms
T C = 25 C
T J = 17 5C 1 0m s
VG S = 0 V S ing le Pulse
1 A 1 A
0.4 0.8 1.2 1.6 2.0 2.4 1 10 100
V S D , Source-to-D rain V oltage (V ) V D S , Drain-to-Source Voltage (V)
24
RD
VDS
20 VGS
D.U.T.
I D , D ra in C u rre n t (A m p s)
RG
+
16 -VDD
5.0V
12 Pulse Width 1 s
Duty Factor 0.1 %
8
Fig 10a. Switching Time Test Circuit
4 VDS
90%
0 A
25 50 75 100 125 150 175
TC , Case Temperature (C )
10%
VGS
Fig 9. Maximum Drain Current Vs.
td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms
10
Th erm al R esp on se (Z th JC )
D = 0.5 0
1
0 .2 0
0.1 0
0.05
0.02 PD M
0 .0 1
0.1
S IN G L E P U LS E t
1
( TH E RM A L RE S P O N S E ) t2
N o te s :
1 . D u ty fa c to r D = t 1 / t 2
2 . P e a k T J = P D M x Z th J C + T C
0.01 A
0.00001 0.0001 0.001 0.01 0.1 1
160
L ID
E A S , S in g le P u ls e A va la n c h e E n e rg y (m J)
VDS
TO P 5.7 A
D.U.T. 9 .9A
B OTTO M 14A
RG + 120
V
- DD
5.0 V IAS
tp 80
0.01
V D D = 1 5V
V(BR)DSS 0 A
25 50 75 100 125 150 175
tp Starting TJ , Junction T emperature (C)
VDD
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
VDS
IAS
50K
12V .2F
QG .3F
+
4.5 V V
D.U.T. - DS
QGS QGD
VGS
VG 3mA
IG ID
Charge Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit
IRL2703
+
- +
-
RG dv/dt controlled by RG +
Driver same type as D.U.T. VDD
-
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VGS=10V *
Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent
Ripple 5% ISD
0 . 9 3 ( .0 3 7 ) 0 . 5 5 (. 0 2 2 )
3 X 0 . 6 9 ( .0 2 7 ) 3X
1 .4 0 (. 0 5 5 ) 0 . 4 6 (. 0 1 8 )
3X
1 .1 5 (. 0 4 5 ) 0 .3 6 (. 0 1 4 ) M B A M 2 .9 2 (. 1 1 5 )
2 .6 4 (. 1 0 4 )
2 . 5 4 ( .1 0 0 )
2X
NO TE S :
1 D I M E N S IO N I N G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 . 3 O U T L IN E C O N F O R M S T O J E D E C O U T L I N E T O -2 2 0 -A B .
2 C O N T R O L L I N G D IM E N S IO N : I N C H 4 H E A T S IN K & L E A D M E A S U R E M E N T S D O N O T IN C L U D E B U R R S .
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http://www.irf.com/ Data and specifications subject to change without notice. 8/97
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/