A High Speed Counter for Analog-to-Digital

Converters
Prudhvi Raj Thota and Ashis Kumar Mal
Department of Electronics and Communication Engineering
National Institute of Technology, Durgapur-713209, India

prudhvi691@gmail.com akmal@ece.nitdgp.ac.in

AbstractA high speed and power efficient synchronous

counter is proposed using True Single-Phase Clock (TSPC)
based Toggle Flip-Flop (TFF) with the Extended True
Single-Phase Clock (E-TSPC) based combinational logic
embedded in it. The principle of realizing both synchronous
up and down counter at both positive and negative edges
using these flip-flops are discussed. Also gray counter is
accomplished using same principle. It has been designed
in 0.18 m CMOS process under 1.8 V power supply. The
simulation results show that an eight bit synchronous counter
can operate at clock frequencies upto 4.54 GHz with the
power dissipation of 0.67 mW, while an eight-bit asynchronous
counter can operate at clock frequencies upto 5 GHz with the Fig. 1. Conventional Counter Design
power dissipation of 0.5 mW.

Index Termsflip-flop (FF), digital counter, gray counter,

true single-phase clock (TSPC), extended TSPC (E-TSPC),
analog-to-digital converter (ADC)

I. I NTRODUCTION
Analog-to-digital converters (ADCs) demand a
synchronous counter that is capable of operating efficiently
for wide range of frequencies[1,2] . Besides its necessity
in ADCs, it is found to be the basic block for various
applications in the field of VLSI design, communication
and measuring systems. Thus, the extensive studies are
going on the design of high speed low power counters.

Synchronous counters for low to moderate frequency
applications, are usually build using stage by stage, each
containing combinational logic and T Flip-Flop (TFF) or
D Flip-Flop (DFF). Although a common clock triggeres all
TFFs simultaneously as shown in Fig. 1, the decision of
toggling depends on the input T, which is driven by the
combinational logic. The combinational logic is usually the
carry propogation chain having the inputs from the outputs
of previous stages.
The counting rate of synchronous counter is bounded
by the delay of combinational logic (tplogic ), setup time
(tsetup ) and the propagation delay (tpT F F ) of TFF. Thus,
the clock period of a conventional counter (tclk ) can be
expressed as [6]
tclk tplogic + tsetup + tpT F F (1)
978-1-4673-6621-2/16/$31.00
c 2016 IEEE
Fig. 2. TSPC based Positive-edge Triggered Divide-by-two circuit
To minimize the tclk , various techniques have been
proposed. The tplogic being the main factor due to
its increase in proportion with the number of stages,
several efficient counters have been proposed based on
Manchester carry chain, carry-look-ahead and binary tree
carry propagation to decrease tplogic , but they occupy
larger area and dissipate more power.
Even Transmission Gate (TG) based TFF does not
minimize propogation delay (tpT F F ) to the greater extent.
Yuan[3] proposed a true single phase clock (TSPC) based
counter capable of operating at 250 MHz with transistor
sizing in a 3 m CMOS process. However, the speed
improvement allowed by the technolgy scaling has made
this counter (transistors sized in scale with the sizes in [3])
 Fig. 3. TSPC based Positive-edge Triggered Toggle Flip-Flop
to operate at near about 4.44 GHz in 0.18 m CMOS
process. With a small modification in the Yuans counter
design[3] , this paper proposes an efficient synchronous
counter that can be operated upto a maximum frequency of
4.54 GHz.
The rest of the paper is organized as follows. Section II
gives the review on the basic building block i.e., TFF
facilitating the asynchronous inputs like preset and clear.
Section III introduces the proposed counters including the
way of embedding the combinational carry chain logic along
with the TFF. Simulation results are discussed in Section IV,
followed by a conclusion in Section V.
II. BASIC B UILDING B LOCK : T OGGLE F LIP -F LOP
Fig. 2 shows a basic nine-transistor (M1 to M9 ) TSPC
based T Flip-Flop proposed by Yuan[3] . It follows the
single-phase precharge logic, which is an alternate se-
quence of P-units (comprising of P-dynamic block fol-
lowed by P-C2 MOS latch stage) and N-units (comprising
of N-dynamic block followed by N-C2 MOS latch stage).
It comprises of three stages : P-C2 MOS stage for latching,
N-dynamic block for precharging and evaluating the logic,
followed by N-C2 MOS stage for latching. The output of
last (N-C2 MOS) stage is fed back as the input to first
(P-C2 MOS) stage, still satisfying the rules of single-phase
precharge logic. The operation of the circuit is as follows:
The first stage latches the input data by every positive
edge of the clock (Clk) signal.
When the clock is at logic 0, the N-dynamic block is
precharged and its N-C2 MOS stage is OFF, as PMOS
(M7 ) and one NMOS (M8 ) are OFF. The output is
therefore stable.
At the positive edge of the clock transition, the
N-dynamic block is in evaluation phase.
If the evaluation result is at logic 1, the NMOS
(M7 ) of the N-C2 MOS stage is ON and makes the
output as logic 0. This is same as the precharge
phase, so no change occurs at the following nega-
tive edge of the clock transition.
If the evaluation result is at logic 0, the PMOS
(M9 ) of the N-C2 MOS stage is ON and makes
the output as logic 1. When the N-dynamic
block starts to precharge, at the subsequent clock
transition, the clocked NMOS (M8 ) is OFF. So, the
ON result is latched at the output of the N-C2 MOS
stage.
An extra unit inverter load (M10 and M11 ) increases the
current driving ability and gives out the non-inverting output
with level restored.
A. Csk as the Input of Toggle Flip-Flop
Placing the transistors M12 and M13 as shown in Fig. 3
provides the input to the flip-flop. Yuan[3] suggested that this
transistor is to be inserted at a lower position to the clocked
transistor in the last stage, so that no charge sharing takes
place at the output node.
If Csk is at logic 1, it operates in toggle mode as
shown in Fig. 2.
If Csk is at logic 0, the N-stage is completely OFF
and thus remains in the previous state.
B. Asynchronous Inputs
Two asynchronous inputs (Preset and Clear) on a flip-flop
have control over the outputs regardless of clock and input
status i.e., they are given higher priority than any other
 TABLE I
T RUTH TABLE OF T OGGLE F LIP -F LOP
Csk qk
0 qk1
1 q k1
input. The preset input drives the flip-flop to a logic 1
while the clear input drives it to a logic 0. Preset and
clear facilities are provided through the transistors M14 and
M15 respectively as shown in Fig. 3. Preset with logic 1
and clear with logic 0 makes the flip-flop to operate in
normal mode. If any of this facility is not at all required in
the design of a counter, the transistors with the respective
inputs can simply be eliminated.
C. Toggle State with Static locking loop
The dynamic condition is possibly broken at the Most
Significant Bit (MSB) or at low clock frequencies, due to
the problems like charge sharing and leakage. This problem
can be solved by placing a weak PMOS (M16 ) and weak
NMOS (M17 ) as shown in Fig. 3.
When the clock is at logic 0, these transistors together
with the first three transistors (M1 , M2 and M3 ) forms
a static dual-inverter locking loop, making the output
unable to change and remain in the previous state.
When the clock is at logic 1, the loop will be broken
and hence allowing the change in the output.
As weak devices have slower performance, they does not
effect the operation at high frequencies. If the circuit is
desired to be operated always at high frequencies, these
transistors (M16 and M17 ) could be removed.
III. P ROPOSED C OUNTER D ESIGNS
A. Synchronous Counter
Synchronous counter is designed using TFFs having
Csk as one of the input to its N-unit. The carry logic
that drives Csk should be P-unit with the inputs from
N-units (previous stages), so as to make it single-phase
precharge logic. The carry stage used by Yuan[3] is
the P-unit consisting of P-dynamic block followed by
P-C2 MOS stage. An Extended True Single-Phase Clock
(E-TSPC) circuit technique: NMOS like P-latch block[7]
allow building P-unit with speed comparable to NMOS.
So, NMOS like P-latch block based combinational carry
unit is designed to make Csk equal to one whenever q 0 ,
q 1 , ... and q n1 are logic 0s.
NMOS like blocks may suffer from charge-sharing
problem[8] , but in this case this problem does not exist as
there are no dynamic nodes. Further, NMOS like blocks can
also be used to bulid divide-by-2 circuit, but the problem
of charge sharing does not allow to provide Csk as input
and hence cannot be used in synchronous counter design.
Fig. 4. E-TSPC based Carry Stages for Positive-edge Triggered Up
Counter
Fig. 5. 2:1 TG based Multiplexer facilitating the counter with U p/Down
mode control
Least significat bit can be generated using either a simple
divide-by-two circuit (Fig. 2) or TSPC based TFF (Fig. 3)
producing Cs0 from E-TSPC based carry stage (Fig. 4).
Since each stage is enabled only when the carry is high,
the power consumption of the most significant bit stages
are substantially reduced.
TABLE II
F UNCTION TABLE OF P ROPOSED C OUNTER
Enable Preset Clear Comment on output
0 0 0 Resets all bits to logic 0
0 0 1 Undetermined
0 1 0 Counts up by one
0 1 1 Sets all bits to logic 1
1 0 0 Resets all bits to logic 0
1 0 1 Undetermined
1 1 0 Holds its previous state
1 1 1 Sets all bits to logic 1
1) Down Counter: The positive edge triggered
synchronous down counter can be obtained by providing
the carry stage with non-inverting inputs (qk=0,1,...(n1) )
instead of inverting inputs (q k=0,1,...(n1) ).
2) Up / Down Counter: Up / Down count feature can be
added using 2:1 Transmission (TG) based multiplexer with
qk and q k as data inputs and U p/Down as selection input
as shown in Fig. 5. The output bk=0,1,...(n2) is fed as the
input to carry stage instead of feeding in qk=0,1,...(n2) or
q k=0,1,...(n2) directly.
3) Negative-edge Triggered Counter: Negative edge
triggered counter can be realized on holding the same
single-phase precharge logic using TSPC based TFF
(N-C2 MOS stage, P-dynamic block, P-C2 MOS stage)
shown in Fig. 6 and E-TSPC based carry stage (NMOS
 Fig. 6. TSPC based Negative-edge Triggered Toggle Flip-Flop
Fig. 7. E-TSPC based Carry Stages for Negative-edge Triggered Up
Counter
like N-latch block) shown in Fig. 7. The down count can
be obtained by providing the inverting inputs while up
count by providing non-inverting inputs. The enable input
is applied at the gate of PMOS, so it is active high.
4) Terminal Count Generation: Terminal count output is
logic 1, when the up counter reaches to all 1s or when
the down counter reaches to all 0s. It can be generated
using E-TSPC based carry stage. Csk=n itself will be the
terminal count for n-bit counter.
B. Asynchronous Counter
The counters can also be realized in an asynchronous
manner, just with the series connection of toggle flip-flops
always opearting in toggle mode (i.e., with input Csk = 1).
The flip-flop holding the least significant bit is triggered by
the incoming count pulses, where as the next higher order
flip-flop is trigerred by the output transistion of previous flip-
flop. Circuit is very simple even for more number of states.
As tplogic is zero in this case, the maximum frequency
is typically higher than that of synchronous counter. But at
higher frequencies, the count may not be read-out properly
due to the change in the state of clock before it reaches
last FF. However, it can still purpose good as a frequency
divider.
C. Synchronous Gray Counter
The principle of designing the synchronous binary
counter can also be extended to design gray counter, which
finds its application in building a FIFO (First-in First-out)
data buffer. Gray counter initially requires parity bit (p) and
Fig. 8. E-TSPC based Carry Stages for Gray Counter
its complement (p), generated using divide-by-two circuit
shown in Fig. 2. The only change in the design of gray
counter lies in feeding the inputs to E-TSPC based carry
stage as shown in Fig. 8.
IV. S IMULATION R ESULTS
The proposed 8-bit synchronous counter is realized using
Cadence Spectre (BSIM3v3 model) with 0.18 m CMOS
technology with 1.8 V supply voltage. Fig. 8 and Fig. 9
shows the simulation result of 8-bit synchronous up counter
at the clock frequency of 4.54 GHz.
TABLE III compares the performance of the proposed
counter with other published works. As depicted in
Table III, Salehs[5] 8-bit counter can operate at a maximum
frequency of 2 GHz, but this counter occupies large area
and dissipates more power. Even though Aliotos[4] design
requires fewer transistors and consumes less power, the
clock frequency is limited to 500 MHz. Resimulating the
Yuans[3] design in 0.18 m CMOS technology with the
transistors sized in scale with the sizes in [3], the maximum
operating frequency is observed to be 4.44 GHz with the
power dissipation of 2.08 mW. Although, the proposed
counter does not offer load facility, the advantage of having
maximum frequency of 4.54 GHz make it more useful in
the applications like the design of time based ADC[9] .
Area and power figures of merit, i.e., F oMArea and
F oMP ower , are useful measures of the relative performance
of counters because they compare various parameters of
different design solutions. They are defined as:
A
F oMArea = pm2 / Count (2a)
2N OB fmax
P
F oMP ower = fJ / Count (2b)
2N OB fmax
 TABLE IV
F IGURE OF M ERITS OF R ELATIVE W ORKS

Counter F oMArea F oMP ower

(pm2 /Count) (fJ/Count)
Yuan[3] 89121.09 -
Alito[4] 54.00 17.26
Saleh[5] 29.88 7.59
Zhang[6] 34.17 18.79
Yuan[3]a 3.48 1.85
Proposed 2.55 0.52

a Resimulated result

Fig. 9. Simulation result of Lower order bits (Clk, q0 to q3 ) of 8-bit V. C ONCLUSION

Synchronous Binary Up counter at 4.54 GHz
The design of synchronous counters facilitating enable
input, preset and clear with high speed, low area and low
power consumption are presented. An eight bit counter has
been designed in 0.18 m CMOS process. Simulation result
shows that the 8-bit synchronous counter can operate upto
a clock frequency of 4.54 GHz with a power dissipation of
0.67 mW where as asynchronous counter at 5 GHz with a
power dissipation of 0.5 mW.
ACKNOWLEDGMENT
The authors wish to acknowledge The Ministry of Com-
munication and Information Technology, Government of
India, for extending the SMDP at NIT Durgapur.

Fig. 10. Simulation result of Higher order bits (Clk, q4 to q7 ) of 8-bit

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