Typical Application
+5 V
8
1 VCC
IP+
7 VOUT
2 CBYP
IP+ VIOUT
0.1 F
IP ACS713
3 6
IP FILTER
4 CF
IP 5
GND
ACS713-DS, Rev. 12
Fully Integrated, Hall Effect-Based Linear Current Sensor IC
ACS713 with 2.1 kVRMS Isolation and a Low-Resistance Current Conductor
Description (continued)
the device at up to 5 overcurrent conditions. The terminals of the The ACS713 is provided in a small, surface mount SOIC8 package.
conductive path are electrically isolated from the signal leads (pins The leadframe is plated with 100% matte tin, which is compatible
5 through 8). This allows the ACS713 to be used in applications with standard lead (Pb) free printed circuit board assembly processes.
requiring electrical isolation without the use of opto-isolators or Internally, the device is Pb-free, except for flip-chip high-temperature
other costly isolation techniques. Pbbased solder balls, currently exempt from RoHS. The device is
fully calibrated prior to shipment from the factory.
Selection Guide
TA Optimized Range, IP Sensitivity, Sens
Part Number Packing*
(C) (A) (Typ) (mV/A)
ACS713ELCTR-20A-T Tape and reel, 3000 pieces/reel 40 to 85 0 to 20 185
ACS713ELCTR-30A-T Tape and reel, 3000 pieces/reel 40 to 85 0 to 30 133
*Contact Allegro for additional packing options.
Isolation Characteristics
Characteristic Symbol Notes Rating Unit
Agency type-tested for 60 seconds per
Dielectric Strength Test Voltage* VISO 2100 VAC
UL standard 60950-1, 1st Edition
For basic (single) isolation per UL standard
Working Voltage for Basic Isolation VWFSI 354 VDC or Vpk
60950-1, 1st Edition
For reinforced (double) isolation per UL standard
Working Voltage for Reinforced Isolation VWFRI 184 VDC or Vpk
60950-1, 1st Edition
* Allegro does not conduct 60-second testing. It is done only during the UL certification process.
Parameter Specification
CAN/CSA-C22.2 No. 60950-1-03
Fire and Electric Shock
UL 60950-1:2003; EN 60950-1:2001
+5 V
VCC
(Pin 8)
Hall Current
Drive
Signal VIOUT
Recovery (Pin 7)
IP
(Pin 3)
Sense
Trim
IP
(Pin 4) 0 Ampere
Offset Adjust
GND FILTER
(Pin 5) (Pin 6)
Pin-out Diagram
IP+ 1 8 VCC
IP+ 2 7 VIOUT
IP 3 6 FILTER
IP 4 5 GND
COMMON OPERATING CHARACTERISTICS1 over full range of TA, and VCC = 5 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Units
ELECTRICAL CHARACTERISTICS
Supply Voltage VCC 4.5 5.0 5.5 V
Supply Current ICC VCC = 5.0 V, output open 10 13 mA
Output Capacitance Load CLOAD VIOUT to GND 10 nF
Output Resistive Load RLOAD VIOUT to GND 4.7 k
Primary Conductor Resistance RPRIMARY TA = 25C 1.2 m
Rise Time tr IP = IP(max), TA = 25C, COUT=10 nF 3.5 s
Frequency Bandwidth f 3 dB, TA = 25C; IP is 10 A peak-to-peak 80 kHz
Nonlinearity ELIN Over full range of IP, IP applied for 5 ms 1.5 %
VCC
Zero Current Output Voltage VIOUT(Q) Unidirectional; IP = 0 A, TA = 25C V
0.1
Output reaches 90% of steady-state level, no capacitor on
Power-On Time tPO 35 s
FILTER pin; TJ=25; 20 A present on leadframe
Magnetic Coupling2 12 G/A
Internal Filter Resistance3 RF(INT) 1.7 k
1Device may be operated at higher primary current levels, IP, and ambient, TA, and internal leadframe temperatures, TA, provided that the Maximum
Junction Temperature, TJ(max), is not exceeded.
21G = 0.1 mT.
3R
F(INT) forms an RC circuit via the FILTER pin.
Characteristic Performance
IP = 20 A, unless otherwise specified
Mean Supply Current versus Ambient Temperature Supply Current versus Supply Voltage
10.5 11.2
10.4 11.0
10.3 10.8
10.2 VCC = 5 V
ICC (mA)
10.6
Mean ICC (mA)
10.1
10.4
10.0
10.2
9.9
9.8 10.0
9.7 9.8
9.6 9.6
-50 -25 0 25 50 75 100 125 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
TA (C) VCC (V)
ELIN (%)
IOM (mA)
2.0 0.20
2.5 VCC = 5 V; IP = 0 A,
After excursion to 20 A 0.15
3.0
3.5 0.10
4.0
0.05
4.5
5.0 0
-50 -25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150
TA (C) TA (C)
Mean Total Output Error versus Ambient Temperature Sensitivity versus Ambient Temperature
10 188
8
187
6
Sens (mV/A)
4 186
ETOT (%)
2
185
0
2 184
4
183
6
8 182
50 25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150
TA (C) TA (C)
Output Voltage versus Sensed Current Sensitivity versus Sensed Current
5.0 200.00
4.5 198.00
196.00
4.0 194.00
Sens (mV/A)
3.0 190.00
TA (C) 188.00
2.5 186.00
40
2.0 184.00 TA (C)
20
1.5 182.00 40
25
180.00 25
1.0 85
178.00 85
0.5 125
176.00 150
0 174.00
0 5 10 15 20 25 0 5 10 15 20 25
Ip (A)
IP (A)
0 A Output Voltage versus Ambient Temperature 0 A Output Voltage Current versus Ambient Temperature
525 0.140
0.120
520
0.100
515 IP = 0 A IP = 0 A
0.080
VIOUT(Q) (mV)
IOUT(Q) (A)
510 0.060
505 0.040
0.020
500
0
495
-0.020
490 -0.040
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA (C) TA (C)
Characteristic Performance
IP = 30 A, unless otherwise specified
Mean Supply Current versus Ambient Temperature Supply Current versus Supply Voltage
10.1 10.8
10.0 10.6
9.9 10.4
ICC (mA)
Mean ICC (mA)
9.7 10.0
9.6 9.8
9.5 9.6
9.4 9.4
-50 -25 0 25 50 75 100 125 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
TA (C) VCC (V)
ELIN (%)
IOM (mA)
Mean Total Output Error versus Ambient Temperature Sensitivity versus Ambient Temperature
8 133.5
6 133.0
Sens (mV/A)
4 132.5
ETOT (%)
2 132.0
0 131.5
2 131.0
4 130.5
6 130.0
8 129.5
50 25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150
TA (C) TA (C)
135
3.0 134
TA (C) 133
2.5
132
40 131
2.0 TA (C)
20 130
1.5 25 40
129
85 128 25
1.0
125 127 85
0.5 126 150
0 125
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
Ip (A)
IP (A)
0 A Output Voltage versus Ambient Temperature 0 A Output Voltage Current versus Ambient Temperature
514 0.080
512
510 0.060
508 IP = 0 A IP = 0 A
VIOUT(Q) (mV)
0.040
506
IOUT(Q) (A)
504 0.020
502
500 0
498
-0.020
496
494 -0.040
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA (C) TA (C)
Noise (VNOISE). The product of the linear IC amplifier gain Full-scale current at 25C. Accuracy at the the full-scale current
(mV/G) and the noise floor for the Allegro Hall effect linear IC at 25C, without the effects of temperature.
(1 G). The noise floor is derived from the thermal and shot Full-scale current over temperature. Accuracy at the full-
noise observed in Hall elements. Dividing the noise (mV) by the scale current flow including temperature effects.
sensitivity (mV/A) provides the smallest current that the device is
Ratiometry. The ratiometric feature means that its 0 A output,
able to resolve.
VIOUT(Q), (nominally equal to VCC 0.1 ) and sensitivity, Sens, are
Linearity (ELIN). The degree to which the voltage output from proportional to its supply voltage, VCC.The following formula is
the IC varies in direct proportion to the primary current through
used to derive the ratiometric change in 0 A output voltage,
its full-scale amplitude. Nonlinearity in the output can be attrib-
uted to the saturation of the flux concentrator approaching the VIOUT(Q)RAT (%).
full-scale current. The following equation is used to derive the
VIOUT(Q)VCC / VIOUT(Q)5V
linearity: 100
{ [ [{
(VIOUT_full-scale amperes VIOUT(Q) ) VCC / 5 V
100 1
2 (VIOUT_half-scale amperes VIOUT(Q)) The ratiometric change in sensitivity, SensRAT (%), is defined as:
100
Quiescent output voltage (VIOUT(Q)). The output of the device VCC / 5 V
when the primary current is zero. For a unipolar supply voltage,
it nominally remains at VCC 0.1 . Thus, VCC = 5 V translates Output Voltage versus Sampled Current
into VIOUT(Q) = 0.5 V. Variation in VIOUT(Q) can be attributed to Accuracy at 0 A and at Full-Scale Current
the resolution of the Allegro linear IC quiescent voltage trim and Increasing VIOUT(V)
Full Scale
0A
Decreasing VIOUT(V)
of its full scale value. The rise time to a step response is used to
derive the bandwidth of the device, in which (3 dB) = 0.35/tr. Transducer Output
10
Both tr and tRESPONSE are detrimentally affected by eddy current 0
IP = 0 A
100 100
80
60
40 10
20
0
1
0 10 20 30 40 50 0.01 0.1 1 10 100 1000
CF (nF)
CF (nF)
Rise Time versus External Filter Capacitance Rise Time versus External Filter Capacitance
1200 CF (nF) tr (s) 180
160
1000 Open 3.5 140
1 5.8
800 120
4.7 17.5
tr(s)
tr(s)
47 88.2
400 100 291.3 60
220 623 40
200 20
470 1120
0 0
0.1 1 10 100 1000 0.1 1 10 100
CF (nF) CF (nF)
Chopper Stabilization is an innovative circuit technique that is the filter. As a result of this chopper stabilization approach, the
used to minimize the offset voltage of a Hall element and an output voltage from the Hall IC is desensitized to the effects
associated on-chip amplifier. Allegro has a Chopper Stabiliza- of temperature and mechanical stress. This technique produces
tion technique that nearly eliminates Hall IC output drift induced devices that have an extremely stable Electrical Offset Voltage,
by temperature or package stress effects. This offset reduction are immune to thermal stress, and have precise recoverability
technique is based on a signal modulation-demodulation process. after temperature cycling.
Modulation is used to separate the undesired DC offset signal This technique is made possible through the use of a BiCMOS
from the magnetically induced signal in the frequency domain. process that allows the use of low-offset and low-noise amplifiers
Then, using a low-pass filter, the modulated DC offset is sup- in combination with high-density logic integration and sample
pressed while the magnetically induced signal passes through and hold circuits.
Regulator
Clock/Logic
Low-Pass
Hall Element Sample and Filter
Hold
Amp
CBYP
0.1 F
8
1 VCC
IP+ U1
2 7 VOUT + LMC6772
Typical Applications
IP+ VIOUT
ACS713 VREF
IP1
3 6
IP FILTER
CF
4
IP 5
GND
Q3
2N7002
+5 V Q1 R3 +5 V
FDS6675a 10 k
R1
CBYP 100 k CBYP
R1 R1
0.1 F 33 k 0.1 F 100 k
VS2 +5 V LOAD
RPU
R2 100 k R2
100 k 100 k
8 1 + LM321
1 CBYP 8 5
IP+ VCC 1 VCC 4 VOUT
0.1 F IP+
2 7 VOUT 4 8
IP+ VIOUT 1
IP+ 5 1
VCC Fault 2
IP+ VIOUT
7 3
2
U2
IP ACS713
2 3 +
IP+ VIOUT
7 VOUT + LMC6772 RF
2 U1 IP ACS713 1 k C1
3 6 6 R3 1000 pF
V
LMV7235
IP FILTER ACS713 REF 3
IP FILTER 3.3 k
CFIP2 CF
4 3 6 4
IP 5 0.01 F
GND IP FILTER IP 5
CF GND
4
IP 5 D1
GND 1N914
Application 2. 10 A Overcurrent Fault Latch. Fault threshold
Q4 Application 3. This configuration increases gain to 610 mV/A
2N7002
set by R1 and R2. This circuit latches an overcurrent fault (tested using the ACS712ELC-05A).
Q2 is powered down. R4
and holds it until the 5 V rail
FDS6675a 10 k
R2
100 k
VS1 +5 V VS2 +5 V
CBYP CBYP
0.1 F 0.1 F
8 8
1 VCC 1 VCC
IP+ IP+ U2
U1
2 7 VOUT + LMC6772 2
IP+ VIOUT
7 VOUT + LMC6772
IP+ VIOUT
Q3 Q4
2N7002 2N7002
Q1 R3 Q2 R4
FDS6675a 10 k FDS6675a 10 k
R1 R2
100 k 100 k
LOAD
In low-frequency sensing applications, it is often advantageous temperature. Therefore, signal attenuation will vary as a function
to add a simple RC filter to the output of the device. Such a low- of temperature. Note that, in many cases, the input impedance,
pass filter improves the signal-to-noise ratio, and therefore the RINTFC, of a typical analog-to-digital converter (ADC) can be as
resolution, of the device output signal. However, the addition of low as 10 k.
an RC filter to the output of a sensor IC can result in undesirable
device output attenuation even for DC signals. The ACS713 contains an internal resistor, a FILTER pin connec-
tion to the printed circuit board, and an internal buffer ampli-
Signal attenuation, VATT, is a result of the resistive divider
fier. With this circuit architecture, users can implement a simple
effect between the resistance of the external filter, RF (see Appli-
cation 5), and the input impedance and resistance of the customer RC filter via the addition of a capacitor, CF (see Application 6)
interface circuit, RINTFC. The transfer function of this resistive from the FILTER pin to ground. The buffer amplifier inside of
divider is given by: the ACS713 (located after the internal resistor and FILTER pin
RINTFC connection) eliminates the attenuation caused by the resistive
VATT = VIOUT .
divider effect described in the equationfor VATT. Therefore, the
RF + RINTFC ACS713 device is ideal for use in high-accuracy applications that
Even if RF and RINTFC are designed to match, the two individual cannot afford the signal attenuation associated with the use of an
resistance values will most likely drift by different amounts over external RC low-pass filter.
+5 V
Allegro ACS706
Application 5. When a low pass filter is construct-
ed externally to a standard Hall effect device, Voltage
Regulator
a resistive divider may exist between the filter To all subcircuits
resistor, RF, and the resistance of the custom-
VIOUT Resistive Divider
er interface circuit, RINTFC. This resistive divider Pin 7
Dynamic Offset
Input
Cancellation
Temperature
Gain Offset
Coefficient CF
RINTFC
Trim Control
+5 V
VCC
Pin 8
Allegro ACS713
Application 6. Using the FILTER pin
provided on the ACS713 eliminates Hall Current
Drive
the attenuation effects of the resis-
tor divider between RF and RINTFC, IP+
Pin 1 Sense Temperature
Coefficient Trim
shown in Application 5. IP+ Buffer Amplifier
Pin 2
Dynamic Offset
and Resistor
Cancellation
Signal VIOUT
Recovery Pin 7
Input
IP Application
Pin 3 Interface
Sense
Trim Circuit
IP
Pin 4 0 Ampere
Offset Adjust
RINTFC
GND FILTER
Pin 5 Pin 6
CF
4.90 0.10
8
0 8 1.27
0.65
8
1.75
0.25
0.17
1 2 1 2
1.27
0.40
For Reference Only; not for tooling use (reference MS-012AA) N = Device part number
Dimensions in millimeters T = Device temperature range
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions P = Package Designator
Exact case and lead configuration at supplier discretion within limits shown A = Amperage
L = Lot number
A Terminal #1 mark area Belly Brand = Country of Origin
B Branding scale and appearance at supplier discretion
C Reference land pattern layout (reference IPC7351
D SOIC127P600X175-8M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances
Revision History
Revision Revision Date Description of Revision
Update rise time and isolation, IOUT reference data,
Rev. 12 November 16, 2012
patents