implementation
ELECTRONICS FINAL PROJECT (1ST YEAR ELECTRICAL
ENGINEERING)
2 REVIEW OF LITERATURE
The 4-T SRAM cell consists of two PMOS pass-gate transistors and two NMOS pull-down
transistors, resulting in relatively smaller cell area than the 6-T SRAM design. It maintains
a logical 1 state at one of the internal storage nodes via PMOS transistor off- state
leakage current. This results not only in higher static power consumption but also in larger
susceptibility to VT variation (since transistor off-state leakage current varies
exponentially with VT), so that the 4-T SRAM cell architecture is not promising for sub-22
nm SRAM technologies.
The 7-T SRAM cell utilizes dedicated word- lines and bit-lines for read vs. write operations
to avoid the possibility of a read disturbance even if the read SNM is lower than 0, so that
minimum-width transistors can be used for minimal cell area.
The 8-T SRAM cell also utilizes dedicated word-lines and bit-lines for read vs. write
operations, but uses complementary bit-lines for write operation as does a 6-T SRAM cell.
Write disturbance is still a general issue for these alternative cell architectures.
The 10-T SRAM cell decouples the storage nodes from the bit-lines to improve read
stability, but requires the use of peripheral write-assist circuitry. These alternative SRAM
cell architectures each have undesirable tradeoffs in cell area or performance as
compared to the 6-T SRAM cell. This thesis therefore focuses on technological approaches
to improve the scalability of the 6-T SRAM cell.
1. 6T SRAM cell It is 2 CMOS inverters with an enable circuit on both sides. The output of
one inverter is connected to the input of the other and vice versa. This creates a simple
latch because when one of the inputs is low, that inverter's output goes high, this makes
the other inverter's input high, so its output is now low. To change the inverters' states,
a high current is plugged into the low side AND a low current on the high side. This pulse
is enough to change the input of that inverter, so the output changes, and the circuit
latches again, but in the opposite state. The enables connect and disconnect it from the
rest of the circuit.
2. The N-channel MOSFET will turn on when it's gate is brought up to the supply voltage,
typically 3.3v or 5v, and turn off when the gate it brought down to ground.
3. The P-channel MOSFET will turn on when it's gate is brought down to ground and turn off
when it's gate is brought up to the supply.
4. Construction of 2 inverters. They are simply a IRF 9540 and a 2N7000 with their drains
connected together.
5. Now we are going to connect the inverters together. The output of one is connected to
the input of the other. To do this, connect a wire to pin 2 of a transistor on the left inverter
and connect it to the output of the other transistor. The output of the inverter is where
pin 3 of the IRF 9540 and pin 1 of the 2N7000 are connected together. Repeat this, but
with the input of the right inverter and the output of the left one.
6. The enable is simple. One 2N7000 has its rounded side facing you, the other has its flat
side facing you. The right-most pin of the left transistor is connected to the left-most pin
of the right transistor. Next, the gates get connected together via a wire. Lastly, we need
to connect the enable to the SRAM bit. To do this, put a wire on either the very left or
very right pin. Next, put the other end of the wire on the gate of the closest inverter.
7. Making another enable on the other side of the circuit, and connect it up.
8. Connect the gates of the enables together then connect another wire from ground to
one of the gates.
9. Add the LED and resistor by putting a resistor on the output or gate of one inverter then
to the positive lead of the LED and ground the negative lead of the LED.
10. Plug in your power supply, turn the supply on and enable the circuit by disconnecting the
gates from ground and setting to +5v. The LED should turn on, or off. If it holds its state,
disable the circuit and switch the wires around, as in the input that was grounded should
be set high and vice versa. If the LED still doesn't change, check your circuit.
11. One pin gets tied to +5v and the other is tied to ground through a resistor. The output of
the button is the pin that is tied to ground.
12. The Write Enable button output connected to the enable gates. The output of the Bit Line
button is connected to the first inverter's input. Its output goes to the enable and to the
second inverter's gate. Its output goes to the other enable. I'm not going into detail on
building the inverters, because I already covered that.
13. To turn the power supply on again and try out your new RAM. To verify the operation of
6TSRAM, the LED's state changes when the write enable is high, but it should latch when
the write enables it low.
Different time ranges (from 10-40 ns to 10-20 us) were tested for the bit line and bit line bar
pulses based on literature as well as curve optimization on LTspice.
4 RESULTS
Hardware implementation results were verified by constructing the previously mentioned circuit
in hardware implementation subsection. The results were computed by a simple test on the LED,
multiple pushes were tested to assure the writing and reading process.
Figure 3: Voltage pulses were plotted for each voltage source in the schematic: word line, bit line, bit line bar
Figure 4: Full simulation of Q nodes
6 REFERENCES
1. Note, A. (1997). Applications Note Understanding Static RAM Operation Overview Fast,
Faster, Fastest What is a Cache? Why use an SRAM? 112.
2. Binggeli, M. (2014). EE 4432 VLSI Design Layout and Simulation of a 6T SRAM Cell Mat
Binggeli.
3. Stamenkovi, Z. (2009). SOC Design for Wireless Sensor Networks. Design, (October).
http://doi.org/10.1007/978-1-4614-4039-0
4. Drapatz, S. (2011). Parametric Reliability of 6T-SRAM Core Cell Arrays. Thesis.
5. Random, R. a M., & Memory, A. (n.d.). SRAM Basics. Notes, 134.
6. Agal, A., & Krishan, B. (2014). 6T SRAM Cell: Design and Analysis. International Journal of
Engineering Research and Applications, 4(3), 574577.
7. Singh, S., & Lakhmani, V. (2014). Read and Write Stability of 6T SRAM, 3(5), 569571.
8. Basics, S., Cell, C. S., Sram, C., Design, C., Operation, R., Operation, W., Cell, C. S. (n.d.). Module
6: Semiconductor Memories Lecture 28: Static Random Access Memory (SRAM).
9. Engelhardt, M. (2010). LTspice Help, 1206. Retrieved from
http://ecee.colorado.edu/~mathys/ecen1400/pdf/scad3.pdf
10. Chandrasetty, V. A. (2011). VLSI Design, 1746. http://doi.org/10.1007/978-1-4614-1120-8
11. Baas, B. (2010). Memories Differential bitlines, 113.
12. Fallis, A. (2013). No Title No Title. Journal of Chemical Information and Modeling, 53(9), 1689
1699. http://doi.org/10.1017/CBO9781107415324.004
13. Spice, C. (2008). Ecen4827/5827.