VISVESVARAYA TECHNOLOGICAL UNIVERSITY

BELAGAVI, KARNATAKA-590018

A Seminar report on
SMART RECORDING OF TRAFFIC VIOLATION USING M-RFID"
Submitted in partial fulfillment for the award of degree of Bachelor of Engineering in Electronics
& Communication Engineering during the year 2016-17
Submitted by
AISHWARYA .P. USN: 4AD13EC001
Under the guidance of
MrS.CHAITRA.G.D
Assistant Professor
Department of ECE
ATME College of Engineering

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ATME COLLEGE OF ENGINEERING
Mysuru-570028
2016-17
 ATME COLLEGE OF ENGINEERING
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Mysuru-570028

CERTIFICATE

This is to certify that the seminar work entitled "smart recording of traffic violation using
MRFID" is a bonafied work carried out by AISHWARYA.P, USN:4AD13EC001 in partial
fulfillment for the award of Bachelor of Engineering in Electronics and Communication of
Visvesvaraya Technological University, Belgaum during the year 2016-2017. It is certified that
all corrections or suggestions indicated for Internal Assessment have been incorporated in the nal
report. The seminar report has been approved as it satisfies the requirements in respect of
seminar prescribed for the degree.

.. .................. ................... .........................

Mrs.Chaitra.G.D Mr. Chandan G N Smt. S R Bhagya Shree

Asst. Professor Asst. professor
Project Guide Seminar Coordinator Dept. of ECE
 ACKNOWLEDGMENT

I take this opportunity to acknowledge my profound gratitude to Dr.L Basavaraj,

Principal, ATME college of Engg, Mysuru for all the Infrastructure and facilities provided during
my study in the institution.

I sincerely thank Smt.S R Bhagyashree, Associate Professor and Head, Dept. of ECE,
ATME college of Engg, Mysuru for her suggestions and support for completion of the seminar
work.

I would like to thank and place on record my deep sense of gratitude to my guide

Mrs.Chaitra.G.D, Asst Professor, Dept. of ECE, ATME college of Engg, Mysuru for his valuable
guidance, help and useful suggestions in this Seminar work.

I would like to thank my seminar coordinators Smt.Pavithra A C, Asst professor and

Mr.Chandan G N,Asst professor, Dept. of ECE, ATME college of Engg, Mysuru for their
constant and valuable guidance in completing the seminar work.

I express my sincere gratitude to the Teaching and non-teaching sta of E&C de-partment
and all my friends and classmates who helped me directly or indirectly for the successful
completion of the work.

Finally I would like to thank my Parents and all my beloved ones for supporting me in
many ways that meant a lot to me.

AISHWARYA .P
4AD13EC001
iv
 TABLE OF CONTENTS

ACKNOWLEDGMENT iii

ABSTRACT iv

LIST OF FIGURES vii

1 INTRODUCTION 2

1.1

2 WORKING OF CONVENTIONAL CMOS AND ADIABATIC LOGIC 7

2.1 Principle of conventional cmos . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Principle of adiabatic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.1 Four phase powerclock supply . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Comparsion of conventional cmos and adiabatic logic . . . . . . . . . . . . . 11

3 TYPES OF ADIABATIC LOGIC 13

3.1 Quasi/partial adiabatic logic . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1.1 E cient Charge Recovery Logic (ECRL). . . . . . . . . . . . . . . . 13

3.1.2 Positive Feedback Adiabatic Logic (PFAL) . . . . . . . . . . . . . . . 15

3.1.3 NMOS energy recovery logic(NERL) . . . . . . . . . . . . . . . . . . 16

3.1.4 Clocked Adiabatic logic . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.5 True Single-phase Adiabatic Logic . . . . . . . . . . . . . . . . . . . . 17

v
 3.1.6 Source-Coupled Adiabatic Logic . . . . . . . . . . . . . . . . . . . . . 18

3.2 Fully adiabatic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Pass Transistor Adiabatic Logic (PAL) . . . . . . . . . . . . . . . . . 20

3.2.2 Split-Level Charge Recovery Logic (SCRL) . . . . . . . . . . . . . . . 21

4 ADVANTAGES AND DISADVANTAGES 24

4.1 Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 Disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 Application of adiabatic logic . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 SCOPE OF FUTURE WORK 27

CONCLUSION 28

REFERENCES 29

vi
 LIST OF FIGURES

1.1 General Block diagram of adibatic logic . . . . . . . . . . . . . . . . . 4

2.1 Working of conventional cmos along with charging and discharging 7

2.2 Working of adiabatic logic along with charing and discharging . . . 9

2.3 Four phase powerclock supply . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 ECRL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 PFAL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 NERL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4 CAL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.5 TSEL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6 SCAL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7 PAL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8 SCRL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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Chapter 1

INTRODUCTION

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1 INTRODUCTION

New generations of processing technology are being developing while present

gener-ation of devices are at very safe distance from fundamental physical limits. Need
for low power VLSI chips arise from such evolution forces of integrated circuits. The
Intel 4004 mi-croprocessor, developed in 1971, had 2300 transistors that dissipated
about 1 watt of power and at 1 MHz frequency. After that Pentium comes in 2001, which
has 42 million transis-tors, dissipating 65 watts of power at a frequency of 2.4 GHz. If
power density rises in this exponential way increase continuously, a microprocessor
designed a few years later, would have the same power as that of the nuclear reactor.
Such high power density introduces re-liability concerns such as, electro migration,
thermal stresses and hot carrier induced device degradation, resulting in the loss of
performance. Another factor that fuels the need for low power chips is the increased
market demand for portable consumer electronics powered by batteries. The craving for
smaller, lighter and more durable electronic products indirectly translates to low power
requirements. Battery life is becoming a product di erentiator in many portable devices.

Being the heaviest and biggest component in many portable systems, batteries have
not experienced the similar rapid density growth compared to the electronic circuits. The main
source of power dissipation in these high performance battery-portable digital systems running
on batteries such as note-book computers, cellular phones and personal digital assis-tants are
gaining prominence. For these systems, low power consumption is a prime concern, because it
directly a ects the performance by having e ects on battery longevity.

In this situation, low power VLSI design has assumed great importance as an active
and rapidly developing eld. Power consumption is one of the basic parameters of any kind
of integrated circuit (IC). Power and performance are always traded o to meet the system
requirements. Power has a direct impact on the system cost. Adiabatic circuits are low
power circuitry which use "reversible logic" to conserve energy. The word adiabatic comes
from a Greek word that describe thermodynamic processes which exchange no energy with
the environment and therefore, no energy loss in the form of dissipated heat. In ideal

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adiabatic logic, each charge could be recycled (reused) an in nite number of times. So
that a signi cant power dissipation reduction would be possible. In real-time computing,
such ideal process cannot be achieved because of the presence of dissipative elements
like resistances in a circuit. There are classical approaches to reduce the dynamic
power such as reducing supply voltage, decreasing physical capacitance and reducing
switching activity. Adiabatic logic works on the concept of switching activities which
reduces the power by giving stored energy back to the supply.

There are several principles that are shared by all of these low - power adiabatic
systems. These include only turning switches on when there is no potential di erence
across them, only turning switches o when no current is owing through them, and using
a power supply that is capable of recovering or recycling energy in the form of electric
charge. To achieve this, in general, the power supplies of adiabatic logic circuits have
used constant current charging , in contrast to more traditional non-adiabatic systems
that have generally used constant voltage charging from a xed-voltage power supply
.The power supplies of adiabatic logic circuits have also used circuit elements capable
of storing energy. This is often done using inductors which store the energy by
converting it to magnetic ux, or using capacitors, which can directly store electric
charge. There are a number of synonyms that have been used by other authors to refer
to adiabatic logic type systems, these include: Charge recovery logic, recycling logic,
clock-powered logic, Energy recovery logic and Energy recycling logic. Because of the
reversibility requirements for a system to be fully adiabatic, most of these synonyms
actually refer to and can be used inter-changeably to describe quasi-adiabatic systems.

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1.1 Block diagram of Adiabatic logic

The simple circuit con gurations which can be used for adiabatic switching. A
general circuit topology for the conventional CMOS gates and adiabatic counterparts is
shown. To convert a conventional CMOS logic gate into an adiabatic gate, the pull-up
transistor and the pull-down transistor networks must be replaced with complementary
transmission-gate (T-gate).

Figure 1.1: General Block diagram of adibatic logic

The T-gate network implementing the pull-up function is used to drive the
true output of the adiabatic gate, while the T-gate network implementing the pull down
function drives the complementary output node. Note that all the inputs should also be
available in complementary form.

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Both the pull-up and pull-down networks in the adiabatic logic circuit are used for
charging as well as discharging the output node capacitance, which ensures that the
energy stored at the output node can be retrieved by the power supply, at the end of
each cycle. To allow adiabatic operation, the DC voltage source of the original circuit
must be replaced by a varying power supply with the ramped voltage output.

The necessary circuit modi cations which are used to convert a conventional
CMOS logic circuit into an adiabatic logic circuit increase the device count by a factor of
two or even more.

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Chapter 2

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2 WORKING OF CONVENTIONAL CMOS AND

ADIABATIC LOGIC

2.1 Principle of conventional cmos

Power d
 issipation in conventional CMOS circuits primarily occurs during device
switching.Both PMOS and NMOS transistors can be modelled by including an ideal
switch in series with a resistor in order to represent the e ective channel resistance of
the switch and the interconnect resistance.

Figure 2.1: Working of conventional cmos along with charging and discharging

The pull-up and pull-down networks are connected to the node capacitance CL, which is
referred to as the load capacitance. When the logic level in the system is 1 there is a
sudden ow of current through R.Q. = CLVdd is the charge supplied by the positive
power supply rail for charging CL to Vdd.

Hence, the energy drawn from the power supply is Q Vdd = CLVdd2. If it is assumed that
the energy drawn from the power supply isequal to that supplied to CL, the energy stored

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in CL becomes one-half the supplied energy, i.e. Estored = 0.5 CL Vdd2 . The
remaining energy is dissipated in R. The same amount of energy is dissipated during
discharging in the NMOS pull-down network when the logic level in the system is 0.

Therefore, the total amount of energy dissipated as heat during charging and discharging is

Etotal = E charge+ E discharge

Etotal = 0.5CL Vdd 2+ 0.5CL Vdd2
Etotal = CLVdd2
From the above equation, it is apparent that the energy consumption in a conventional
CMOS circuit can be reduced by reducing Vdd. By decreasing the switching activity in
the circuit, the power consumption (P = dE/dt) can also be proportionally suppressed.

2.2 Principle of adiabatic logic

Adiabatic switching is commonly used to minimize energy loss during

charging/discharging. The word adiabatic (Greek adiabatos, which means impassable) indicates
a state change that occurs without heat loss or gain. During adiabatic switching, all the nodes are
charged or discharged at a constant current in order to minimize power dissipation.

This is accomplished by using AC power supplies to initially charge the circuit

during speci c adiabatic phases and then discharge the circuit to recover the supplied
charge. The principle of adiabatic switching can be best explained by contrasting it with
the conventional dissipative switching technique. Figure shows the manner in which
energy is dissipated during a switching transition in adiabatic logic circuits.

In contrast to conventional charging, the rate of switching transition in adiabatic

circuits is decreased because of the use of a time-varying voltage source instead of a
xed voltage supply. The peak current in adiabatic circuits can be signi cantly reduced by
en-suring uniform charge transfers over the entire available time. Hence, if I is
considered as the average of the current owing to CL, the overall energy dissipation
during the transition phase can be reduced in proportion as follows.

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Figure 2.2: Working of adiabatic logic along with charing and discharging

Theoretically, during adiabatic charging, when the time for the driving voltage to change
from 0 V to Vdd, Tp is long, power dissipation is nearly zero. When changes from HIGH
to LOW in the pulldown network, discharging via the Nmos transistor occurs.It is
apparent that when power dissipation is minimized by decreasing the rate of switching
transition, the system draws some of the energy that is stored in the capacitors during a
given computation step and uses it in subsequent computations. The signal energy may
be recycled instead of dissipated as heat.

2.2.1 Four phase powerclock supply

The four Phases powerclock supply are Evaluate (E): outputs are evaluated
from stable input signals.Hold (H): outputs are kept stable to supply subsequent gate
with stable input signal. Recover (R): Energy is recovered Wait (W): for symmetry
reasons because symmetric signals are easier to generate.

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Figure 2.3: Four phase powerclock supply

Adiabatic Logic circuits are operated with an oscillating power-supply, the so-called power-clock.
Depending on the regarded adiabatic family, more than one powerclock signal is used to
operate an system consisting of Adiabatic Logic gates. In this work adiabatic families are
employed, that use a four-phase power-clock 0-3. Each power-clock cycle consists of four
intervals. In the evaluate (E) interval, the outputs are evaluated from the stable input signals.
During the hold (H) interval, outputs are kept stable for supplying the subsequent gate with a
stable input signal. Energy is recovered in the interval called recover (R). And for symmetry
reasons a wait (W) interval is inserted, as symmetric signals are easier and more e cient to be
generated. Data in adiabatic systems is processed in a pipeline fashion, data is handed over as
shown. Valid data words 1, 2, 3 and 4 are sketched in phase 0. Data word 1 is transferred
during the H interval of 0 and while 1 is in E. It is processed by the logical function given in the
succeeding gate and valid at the outputs as 1 for further processing in the next gates. As
mentioned before, signals have to be kept constant during E, therefore a 90 phase shift
between subsequent phases is obtained. In a pipeline, subsequent gates have

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to be connected to the right phases in order to guarantee a transfer of valid input data.

2.3 Comparsion of conventional cmos and adiabatic logic

Compare various quasi-adiabatic logic styles for power consumption and energy-
delay product using one common platform of 180 nm technology since the reported results
are on adiabatic circuits developed at di erent times and hence of di erent technologies.

Select and hypothesize a suitable quasi-adiabatic MOS logic style for a typical
digital circuit and experimentally prove that it is superior to conventional optimized
CMOS logic styles.

Propose and demonstrate a way to reduce leakage power dissipation in quasi-

adiabatic logic and develop a boundary circuit which would act as interface between
adiabatic logic and CMOS logic.

In the past had preferred to design a large chain of inverters or a complex digital
system to prove that their logic style consumed less energy as compared to CMOS. The
emphasis in work was kept on testing the new logic style for various conditions rather
than building a complex digital circuit.

In adiabatic logic it depends on size of transistor and time period whereas in

cmos it depends on capacitor and vdd.

In adiabatic logic during discharging the energy is drawn from stored output and it
recycled whereas in cmos during discharging the stored energy is pull down to ground.

In CMOS Dissipated energy in pull up and pull down = CVdd2 and it depends on C
and Vdd only. Whereas in adiabatic logicDissipated energy in charge and recovery = 2*R*
C2 * Vdd2/T.Depends on size of transistor and T as well Slower circuit is charged less
energy dissipation.Adiabatic has less energy dissipation if we assume activity factor of 1.

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Chapter 3

TYPES OF ADIABATIC LOGIC

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3 TYPES OF ADIABATIC LOGIC

3.1 Quasi/partial adiabatic logic

Quasiadiabatic circuits have simple architecture and power clock system. The adia-
batic loss occurs when current ows through non-ideal switch, which is proportional to the
frequency of the power-clock. Popular Partially Adiabatic families include the following:

3.1.1 E cient Charge Recovery Logic (ECRL).

E cient Charge Recovery Logic (ECRL) proposed by Moon and Jeong , shown in
Figure, uses cross-coupled PMOS E cient Charge Recovery Logic (ECRL) proposed by
Moon and Jeong.

Figure 3.1: ECRL Circuit

It has the structure similar to Cascode Voltage Switch Logic (CVSL) with di
erential signalling. It consists of two cross-coupled transistors M1 and M2 and two NMOS

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transistors in the N functional blocks for the ECRL adiabatic logic block.An AC power supply pwr
is used for ECRL gates, so as to recover and reuse the supplied energy. Both out and /out are
generated so that the power clock generator can always drive a constant load capacitance
independent of the input signal Full output swing is obtained because of the cross-coupled
PMOS transistors in both precharge and recover phases. But due to the threshold voltage of the
PMOS transistors, the circuits su er from the non-adiabatic loss both in the precharge and
recover phases.That is, to say, ECRL always pumps charge on the output with a full swing.
However, as the voltage on the supply clock approaches to |Vtp|, the PMOS transistor gets
turned o . So the recovery path to the supply clock to the supply clock is disconnected, thus,
resulting in incomplete recovery. Vtp is the threshold voltage of PMOS transistor. The amount of
loss is given as EECRL = C|Vtp|2/2 .From this Equation , it can be inferred that the nonadiabatic
energy loss is dependent on the load capacitance and independent of the frequency of
operation. The ECRL circuits are operated in a pipelining style with the four-phase supply
clocks. When the output is directly connected to the input of the next stage (which is a
combinational logic), only one phase is enough for a logic value to propagate. However, when
the output of a gate is fed back to the input, the supply clocks should be in phase. A latch is one
of the simplest cases which have a feedback path.The input signals propagate to the next stage
in a single phase, and the input values are stored in four phases (1-clock) safely.Let us assume
in is at high and inb is at low. At the beginning of a cycle, when the supply clock pwr rises from
zero toVDD, out remains at a ground level, because in turns on Ftree (NMOS logic tree). /out
follows pwr through M1. When pwr reaches VDD, the outputs hold valid logic levels. These
values are maintained during the hold phase and used as inputs for the evaluation of the next
stage. After the hold phase, pwr falls down to a ground level, out node returns its energy to pwr
so that the delivered charge is recovered. Thus, the clock pwr acts as both a clock and power
supply.

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3.1.2 Positive Feedback Adiabatic Logic (PFAL)

The partial energy recovery circuit structure named Positive Feedback Adiabatic
Logic (PFAL) has been used, since it shows the lowest energy consumption if compared to
other similar families, and a good robustness against technological parameter variations.

Figure 3.2: PFAL Circuit

. It is a dual-rail circuit with partial energy recovery. The general

schematic of the PFAL gate is shown in Figure. The core of all the PFAL gates is an
adiabatic ampli er, a latch made by the two PMOS M1-M2 and two NMOS M3-M4, that
avoids a logic level degradation on the output nodes out and/out. The two n-trees
realize the logic functions. This logic family also generates both positive and negative
outputs. The functional blocks are in parallel with the PMOSFETs of the adiabatic ampli
er and form a transmission gate. The two n-trees realize the logic functions. This logic
family also generates both positive and negative outputs.

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The two major di erences with respect to ECRL are that the latch is made by two
PMOSFETs and two NMOSFETS, rather than by only two PMOSFETs as in ECRL logic,
and that the functional blocks are in parallel with the transmission PMOSFETs. Thus the
equivalent resistance is smaller when the capacitance needs to be charged.

3.1.3 NMOS energy recovery logic(NERL)

NMOS energy recovery logic (NERL), which uses NMOS transistors only and a sim-
pler 6-phase clocked power. Its area overhead and energy consumption are smaller,
compared with the other fully adiabatic logics. We employed bootstrapped NMOS switches
to simplify the NERL circuits. With the results for a full adder, we con rmed that the NERL
circuit consumed substantially less energy than the other adiabatic logic circuits at low-
speed op-eration. NERL is more suitable than the other adiabatic logic circuits for the
applications that do not require high performance and low energy consumption.

Figure 3.3: NERL Circuit

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3.1.4 Clocked Adiabatic logic

CAL is a dual-rail logic that operates from a single-phase AC power-clock supply. In the
adiabatic mode, the powerclock supply waveform is generated using an on-chip switching
transistor and a small external inductor between the chip and a low-voltage dc supply. Cross-
coupled CMOS inverters, transistors M1 M4, provide memory function. In order to realize an
adiabatic inverter andtiming control clock signal CX has been introduced. This signal controls
the transistors that are in series with the logic trees represented by the functional blocks F
and /F. The CX-enabled devices allow operation with a single power clock pwr.

Figure 3.4: CAL Circuit

3.1.5 True Single-phase Adiabatic Logic

TSEL is a partially adiabatic circuit family related to 2N2P, 2N- 2N2P, and CAL.
Power is supplied to TSEL gates by a single phase sinusoidal power-clock. Cascades are

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composed of alternating PMOS and NMOS gates. Two DC reference voltages ensure
high-speed and high-e ciency operation. They also enable the cascading of TSEL gates
in an NP-domino style. In comparison with corresponding adders in Alternative logic
styles and minimum possible supply voltages, TSEL is more energy e cient across a
broad range of operating frequencies. Speci cally for clock frequencies ranging from
10MHz. To 200MHz. TSEL is the rst energy-recovering logic family that operates with a
single-phase sinusoidal clocking scheme. Both TSEL and SCAL gates are dual-rail and
always present a balanced load to the clock generator, regardless of the particular data
computed. Moreover, they are both functionally complete.

Figure 3.5: TSEL Circuit

3.1.6 Source-Coupled Adiabatic Logic

SCAL is, a partially adiabatic, dynamic logic family. SCAL retains all of TSELs positive
features, including single-phase power-clock operation. Moreover, it achieves energy

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e cient operation across a broad range of operating frequencies by using an individually

tunable current source at each gate. SCAL achieves increased energy e ciency by using
a tunable current source to control the rate of charge ow into or out of each gate. Our
adi-abatic circuitry avoids a number of problems associated with multiple power-clock
schemes, including increased energy dissipation, layout complexity in clock
distribution,clock skew, and multiple power-clock generators.

Figure 3.6: SCAL Circuit

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3.2 Fully adiabatic logic

Full-adiabatic circuits have no non-adiabatic loss, but they are much more
complex than quasi-adiabatic circuits. All the charge on the load capacitance is
recovered by the power supply. Some Fully adiabatic logic families include:

3.2.1 Pass Transistor Adiabatic Logic (PAL)

PAL is a dual-rail adiabatic logic with a relatively low gate complexity that operates with a
two-phase power clock. A PAL gate consists of true and complementary pass transistor
NMOS functional blocks (f, /f), and a cross coupled PMOS latch ( M p l, Mp2). ,

Figure 3.7: PAL Circuit

which shows the implementation of an AND-OR gate: Q = A.B + C. The power is supplied
through a sinusoidal power-clock (PC). When PC starts rising from low, input states make a
conduction path from the power clock (PC) through one of the functional blocks to the

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corresponding output node and allow it to follow the power clock. The other node will be
tri-state and kept close to OV by its load capacitance. This in turn causes one of the
PMOS transistors to conduct and charge the node that should go to one state, up to the
peak of PC. The output state is valid at around the top of the power clock.

3.2.2 Split-Level Charge Recovery Logic (SCRL)

Knight and Younis developed a family of adiabatic circuits known as Splitlevel

Charge Recovery Logic or SCRL.

Figure 3.8: SCRL Circuit

Analyzing a full cycle of the SCRL NAND presented in gure 1 gives a good
understanding of how this family of logic works in general. This circuit is very similar to a
conventional NAND; however, one of the main di erences is that the top and bottom rails
are driven by trapezoidal clocks (1 and /1) rather then Vdd and Gnd. In the beginning the
whole circuit is set at Vdd/2 except for P1 which is set to Gnd and /P1 which is set to Vdd

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so that the transmission gate is o . In the next step, the transmission gate is turned on by
gradually switching the value of P1 and /P1. Following, 1 and /1 which were at Vdd/2 are
split to Vdd and Gnd respectively. At this point, the gate computes the NAND of a and b like
a non-adiabatic gate would. Once the output is used by the next gate, the transmission gate
can be turned back o gradually. Then 1 and /1 are gradually returned to Vdd/2 and now the
input can change and the next cycle can begin. It is important not to change the input until
the rails are back to Vdd/2 so that a transistor is not turned on when there is a potential di
erence thus violating the rst rule. The last part that needs explaining is the extra P-MOS
connected to input B. Lets analyze what happens when that transistor is missing. Once 1
and/1 are split, when a has a value of logical 1 and b of logical 0, current ows from Vdd
through the P-MOS controlled by b and down through the N-MOS controlled by a which
means that a high voltage is passing through an NMOS which will thus dissipate energy.
This problem is solved by the extra P-MOS and in general care must be taken to ensure
that an internal node is not dissipating energy in this way. Finally the only node that is not
restored by the gate is the output. This is so that a fully pipelined circuit at the gate level can
be achieved. Also, in order to achieve the gradual swings needed to operate these gates,
trapezoidal clock are used so that initially, the voltage is held constant for quarter of a cycle,
then gradually gets turned up or down, held constant again, and for the nal quarter, is
gradually returned to the initial value.

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Chapter 4

ADVANTAGES AND DISADVANTAGES

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4 ADVANTAGES AND DISADVANTAGES

4.1 Advantages

Adiabatic logic circuits provide a method of decreasing the energy dissipation

when compared with conventional logic switching under certain circumstances.

The peak current in adiabatic circuits can be signi cantly reduced by ensuring
uni-form charge transfers over the entire available time.

The low power consumption is a prime concern, because it directly a ects the
per-formance by having e ects on battery longevity.

The craving for smaller, lighter and more durable electronic products indirectly
trans-lates to low power requirements. Battery life is becoming a product di erentiator in
many portable devices.

The biggest energy saving with the least time needed for consumption analysis
is acquired on the system design level.

The results obatined in the proposed techniques has less power dissipation
compared to conventional CMOS design with less transistor count. These advantages
made these logics more convenient for energy e cient digital applications.

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4.2 Disadvantages

A major disadvantage in ECRL Adiabatic logic circuit is the existence of the

coupling e ects, because the two outputs are connected by the PMOS latch and the two
complemen-tary outputs can interfere each other.

The fully adiabatic circuits reduce the power consumption signi cantly but they
are very complex to design and although the partially adiabatic circuits are not as e
cient as fully adiabatic circuits in terms of power consumption but they reduce the circuit
complexity and conserve the power.

In the sub-threshold regime, consumption is several orders of magnitude lower,

but operating speed is lowered by nearly the same amount in comparison to the strong
inversion regime.

Adiabatic circuits face di culties in speed for a number Of

reasons: Charging time is inherently much slower than CMOS.
Increasing speed of adiabatic circuits enlarges power-clock data sensitivity.

It requires 50 percent more area than conventional CMOS and simple circuit
designs can be very complicated.

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4.3 Application of adiabatic logic

The adiabatic logic circuits can play a signi cant role in designing applications
where power conservation is of prime importance such as in high performance, hand
held and portable digital systems running on batteries such as note-book computers,
cellular phones and personal digital assistants.

Depending on the application and the system requirements, this approach can
be used to reduce the power dissipation of the digital systems.

Mobile computing devices such as laptop computers, personal digital assistants,

mo-bile gaming console, portable mp3 players, portable DVD players, photo storage and
review-ing devices and cellular phones among the other are getting increased popularity.

In the absence of low power design technique, portable and hand handheld products
would su er from very short battery life, while packaging and cooling would be very di cult.

To protect the device from thermal breakdown this also results in increase of
total area of the device.In addition reliability is also a ected by power consumption.
Finally, from environmental point of view, lower the power dissipation of the product
lesser is the electricity consumed and lower is the impact on global environment.

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5 SCOPE OF FUTURE WORK

To perform digital logic CMOS in a truly adiabatic fashion requires that the logic
transitions be driven by a quasi trapezoidal power clock voltage waveform, which must be
Pass transistor adiabatic logic for low power VLSI design. The high cost-per weight of
launching computing related power supplies solar panels and cooling systems into orbit im-
poses a demand for adiabatic power reduction in space craft in which these components
weigh a signi cant fraction of total spacecraft weight. There is a huge scope of improve-
ment in the design and implementation of the power clock for the adiabatic circuit. The
synchronous power clock can only achieve e ciency up to 58 percent and hence becomes
the major source of power dissipation in the circuit. Work can be done in this regard.The e
ciency of adiabatic circuit largely depends on the e ciency of the power-clock generation.
The various techniques reported in literature use resonant drivers to generate power-clock
supply. The energy e ciency of these circuits is very poor and therefore the e ciency of the
entire adiabatic circuit diminishes. This has been a major hindrance in the commercial-
ization of adiabatic logic style. This is an upcoming area and has lot of research potential.
Secondly, the adiabatic cell library is not available for the researchers to use. There is a
scope for generating cell libraries of di erent adiabatic logic styles. But this requires either
advanced library generation tools or manpower. We made an attempt to design a typical.lib
le for our own logic style. This work was done manually in the absence of library genera-tion
tool. If energy e cient solutions to power clock generation for driving adiabatic circuits are
found out in future, then adiabatic circuits can have good scope to become an integral part
of large digital systems dissipating considerably low energies. Of course, this demands the
availability of standard adiabatic cell libraries built using designers and manufacturers
knowledge and made available with standard chip design tools. In that case many conclu-
sions drawn from this research work and many solutions suggested will help as guidelines
to design quasi-adiabatic digital systems either in totality, or partly in combination with
conventional CMOS withbridge between the two being established through recommended
boundary circuit.

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CONCLUSION

Adiabatic circuits all input signals must undergo a controlled transition in the form of a
ramp, unlike the conventional logic switching where only the input signals which have di erent
nal logic state change. To reduce energy dissipation, logic switching cannot be instantaneous
but must be gradual instead. There is a lower limit to the energy dissipation beyond which no
signi cant improvements can be achieved for increasing rise/fall times. This limitation is mainly
due to the nite threshold voltage of the MOS transistors and possibly to a lesser extent, the non
linear characteristics of the MOS channel resistance. It was also observed that the fully
adiabatic circuits reduce the power consumption signi cantly but they are very complex not as e
cient as fully adiabatic circuits in terms of power consumption but they reduce the circuit
complexity and conserve the power. So we can say that partially adiabatic circuits are fair
compromise between the power consumption and complexity trade o . The adiabatic approach
to VLSI circuit design is an attractive method in designing low power dissipating digital
applications. This paper primarily focuses on the design of low power high speed CMOS cell
structures. A family of conventional CMOS Logic and an Adiabatic Logic units were designed
and simulated on the tanner using the 0.18 m CMOS technology and further analysis of average
dynamic power dissipation with respect to the frequency and load capacitance was done. It was
observed that the adiabatic logic style is advantageous in applications where power reduction
as well as speed is of prime importance. The study observed that an improvement of 90 to 95
percent in energy savings as compared with conventional CMOS circuits. The di erent
parameter variations against adiabatic logic families are investigated, which shows that
adiabatic logic families highly depend upon its. But less energy consumption in adiabatic logic
families can be still achieved than CMOS logic over the wide range of parameter variations.
PFAL shows better energy shavings than ECRL at the high frequency and high load
capacitance. Hence adiabatic logic families can be used for low power application over the wide
range of parameter variations.

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REFERENCES

[1] Frank M,Reversible Computing and Truly Adiabatic Circuits: Truly Adiabatic Cir-
cuits,The Next Great Challenge for Digital Engineering, 2006.

[2] Teichmann Philip, Adiabatic Logic Springer, 2012.

[3] Deepti Adiabatic Logic Circuits: A Retrospect, , MIT International Journal of Electron-
ics and Communication Engineering, Vol. 3, No. 2, August 2013.

[4] Gurpreet Kaur M.Tech Scholar(ECE) and Narinder Sharma,Comparison of adiabatic

and Conventional CMOS, Volume1 Issue 2 Dec 2014.

[5] Sakshi Goyal, Power Dissipation analysis of Conventional CMOS and Adiabatic
CMOS circuits,, International Journal of Emerging Technologies in Computational
and Applied Sciences (IJETCAS) www.iasir.net.

[6] Samik Samanta, EFFICIENT ENERGY RECOVERY LOGIC: Study and Implementa-
tion ,International Journal of Advanced Research in Electrical,Electronics and Instru-
mentation Engineering Vol. 2, Issue 9, September 2013

[7] Anu Priya, Adiabatic Technique for Power E cient Logic Circuit Design,Dept. of Elec-
tronics and Communication, RIET.

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