Quartus II Project Multiplier & Divider

2016/12/9 by TA

Problems Description:

Please refer to Unit18 in our textbook. It descripts the architecture of a binary

multiplier and a binary divider in 18.2, 18.3 respectively. In our final project, each
group have to choose one target (either Multiplier or Divider), implement it, verify it
by vwf simulation and write a simple report.

Since the Divider is harder to implement, your grade would be slightly different
accordingly:
Multiplier Grades (6%)
(If fail, TA will grade it by your report) 0 ~ 3.5
Pass basic vwf test 3.5
Pass advanced vwf test 4.5
Choose to present & well prepared 5.0
Chosen to present in 1/7 5.5
Divider Grades (6%)
(If fail, TA will grade it by your report) 0~4
Pass basic vwf test 4
Pass advanced vwf test 5
Choose to present & well prepared 5.5
Chosen to present in 1/7 6.0

Noted that you can bring out your creativity. The architecture descripted in
textbook is not the only solution. Under the premise that you follow all the
specification in corresponding topic, we encourage you to try different designs.
Special designs would have higher probability to be chosen to give the presentation
(in other words, more grades). In this case, you must write down whats the
advantages in your circuit and have a short discussion.

If you choose willing to present, you have to make slides for 4-5 minutes
presentation. You have to hand in the slides together with other files before the
deadline.

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Report Requirements:
No more than 4 pages. And it must have the following check point:
Topic (choose either Multiplier or Divider)
Group information:
Name, student ID, and which teachers class
Achievements, a check list as follow:
Pass basic test Willing to present Special design
O/X O/X O/X
Fill either O or X accordingly and honestly.

If you fail for the basic/advanced test and cannot fix all the problem, you are
requested to describe your design detailedly in order to get partial points. (If you
pass you can still write something down.) [e.g. Architecture of your current design;
State graph of control logic; How it fail; Whats the probably problem; ]
If you wish to be picked for the presentation (01/07), please let TA know your
effort in the report. Special design only means higher probability, if you just make
a common design, you still have the opportunity for presentation (& more points).
You can show your effort such as: analyzing that architecture, doing better logic
simplification, how do you do the debugging, what special bugs you find, how do you
fix these special bugs , etc.
Heres some direction for special design: Speed (smaller comb. propagation
delay, or fewer cycle), Area (gate count, register number), Throughput, Architecture
improvement Sometimes you need to mark out under what kind of data I/O
can your system work optimally. You can use your own .vwf to show that (e.g.
pipeline structure), but your system must still remain the basic ability to pass our
specification.
Slides Requirements:
Must be contained in your submission file if you select willing to present. The
slides are used to present to other students, not TA, so make it more interesting. You
can show your characteristic of your work (special design, effort, special bugs ).
Since you have only 5 minutes, your presentation dont need to contain the details,
just introduce your work briefly.
Files for You:
We advise you to start with project built by TA. You can find them by
decompressing: ch18_div.tgz or ch18_mul.tgz. Both of them are well-set with
our basic elements library: NTUEE_LogicDesign_Lib. Quartus built-in modules
are not allowed in final project!! You can only those in NTUEE_LogicDesign_Lib
or bsf made by yourself.

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Submit Rules:
Upload your files to ceiba. For groups, uploading files to anyone members
ceiba is enough. Please download & check again for your files to insure that not
submitting error occurs. Deadline: 12/30 23:59
Files for submission are:
Report (PDF files, maximum 4 pages)
A folder names either ch18_mul or ch18_div that contains all your .bdf
& .bsf files (Dont submit NTUEE_LogicDesign_Lib)
Dont submit the whole quartus project!!! They are too big!!!
Slides for 4-5 minutes presentation (optional : if willing to present)
Example:

project.zip

Penalties:
1. Make sure that your submitted files are only those mentioned above.
Incorrect submission will cause a penalty of -1 on your final grade!
2. Delayed assignment: -1 for one day delay! (Get 0 for over 6 days delay)

Specification for Multiplier: -----------------------------------------------------------

I/O Pins
Name Width Type Radix Describe
clk 1 in Clock, duty cycle 50%
rst_n 1 in Asyc. reset when (rst_n==0)
start 1 in Marks a new operation & inputs
x_i[3..0] 4 in unsigned Multiplicand
y_i[3..0] 4 in unsigned Multiplier
done 1 out Marks the output & end of a work
result_o[7..0] 8 out unsigned Product result

Input Format
All input signal change at the neg-edge of clk. That is, they are always stable at
pos-edge. It is easier for you to design a system works at rising edge because TA
only test your system under functional simulation.
Each multiple operation would be marked by signal start. Start only holds
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one cycle. Simultaneously, the new multiplicand (x_i) and multiplier (y_i) come
with start. But x_i and y_i would keep their value until your done signal
raised up.
Your system must have the ability to continuously serve for other work, too.
The earliest coming start would be set at the coming falling edge after your done.
But start are not necessarily following your done. There might be a silence
period and you cant send any false done.
Output Format
Your done signal denotes the output data is valid and is the end of current
work. Your output data and done would be checked at neg-edge, too. That is, a
system works at rising edge is suitable since your signals are only unstable at pos-
edge under functional simulation. One done is for one start.
We dont care the latency between start and done. So no matter Mealy
machines, Moore machines, or even slower state machines are OK.
Timing Chart Example

VWF List
Basic test: test01.vwf + test02.vwf + test03.vwf

Specification for Divider:---------------------------------------------------------------

I/O Pins
Name Width Type Radix Describe
clk 1 in Clock, duty cycle 50%
rst_n 1 in Asyc. reset when (rst_n==0)
start 1 in Marks a new operation & inputs
x_i[7..0] 8 in unsigned Dividend
y_i[3..0] 4 in unsigned Divisor
done 1 out Marks the output & end of a work
quo_o[4..0] 5 out unsigned Quotient
rem_o[3..0] 4 out unsigned Remainder

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Input Format
All input signal change at the neg-edge of clk. That is, they are always stable at
pos-edge. It is easier for you to design a system works at rising edge because TA
only test your system under functional simulation.
Each multiple operation would be marked by signal start. Start only holds
one cycle. Simultaneously, the new dividend (x_i) and divisor (y_i) come with start.
But x_i and y_i would keep their value until your done signal raised up.
Your system must have the ability to continuously serve for other work, too.
The earliest coming start would be set at the coming falling edge after your done.
But start are not necessarily following your done. There might be a silence
period and you cant send any false done.
In addition, you don't have to deal with the overflow problem. For all test
cases, it would always match the inequation: 32*y_i > x_i. So 5 bits for quotient is
enough. But maybe you can discuss the overflow handling in special design.
Output Format
Your done signal denotes the output data is valid and is the end of current
work. Your output data and done would be checked at neg-edge, too. That is, a
system works at rising edge is suitable since your signals are only unstable at pos-
edge under functional simulation. One done is for one start.
We dont care the latency between start and done. So no matter Mealy
machines, Moore machines, or even slower state machines are OK.
Timing Chart Example

VWF List
Basic test: test01.vwf + test02.vwf + test03.vwf

About advanced vwf test:

This test is not released. However, you need to know that this test contain some
rare and extreme cases. Therefore, additional tests made by yourself are needed. You
can figure out some cases (such as those mentioned in the class) and modify or make
a vwf files to test it.