Rayat Shikshan Sansthas

KARMAVEER
BHAURAO PATIL
POLYTECHNIC,
SATARA
Combinational
Logic
Circuits
Department Of Electronics And
Telecommunication Engineering
 Principles of Digital
Techniques
EJ3G Subject Code: 17320
Second Year Entc

Amit Nevase
Lecturer,
Department of Electronics & Telecommunication
Engineering,
Karmaveer Bhaurao Patil Polytechnic, Satara

Amit Nevase
3/12/17 2
 Objectives
The student will be able to:
Understand basic digital circuits.

Understand conversion of number

systems.
Implement combinational and sequential
circuits.
Understand logic families, data converters
Amit Nevase
3/12/17 3
Teaching & Examination Scheme

Teaching Scheme Examination Scheme

PAPER
TH TU PR TH PR OR TW TOTAL
HRS

03 -- 02 03 100 25# --- 25@ 150

Two tests each of 25 marks to be conducted as per the schedule given

by MSBTE.
Total of tests marks for all theory subjects are to be converted out of 50
and to be entered in mark sheet under the head Sessional Work (SW).

Amit Nevase
3/12/17 4
 Module I Number System
Introduction to digital signal, Advantages
of Digital System over analog systems
(8 Marks)
Number Systems: Different types of number
systems( Binary, Octal, Hexadecimal ), conversion of
number systems,
Binary arithmetic: Addition, Subtraction,
Multiplication, Division.
Subtraction using 1s complement and 2s
complement
Codes
(4 Marks)
Amit Nevase
Codes -BCD, Gray Code, Excess-3, ASCII code
3/12/17 5
 Module II Logic Gates & Introduction to Logic Families

Logic Gates
(8 Marks)
Basic Gates and Derived Gates
NAND and NOR as Universal Gates
Boolean Algebra: Fundamentals of Boolean Laws
Duality Theorem, De-Morgans Theorem
Numericals based on above topic
Logic Families
(8 Marks)
Characteristics of Logic Families & Comparison
between different Logic Families
Logic Families such as TTL, CMOS, ECL
Amit Nevase
3/12/17 6
TTL NAND gate Totem Pole, Open Collector
Module III Combinational Logic Circuits

Introduction
(8 Marks)
Standard representation of canonical forms (SOP &
POS), Maxterm and Minterm , Conversion between
SOP and POS forms
K-map reduction techniques upto 4 variables (SOP &
POS form), Design of Half Adder, Full Adder, Half
Subtractor & Full Subtractor using k-Map
Code Converter using K-map: Gray to Binary Binary
to Gray Code Converter (upto 4 bit)
IC 7447 as BCD to 7- Segment decoder driver
IC 7483 as Adder & Subtractor, 1 Digit BCD Adder
Block SchematicAmitofNevase
ALU IC 74181 IC 74381
3/12/17 7
Module III Combinational Logic Circuits

Necessity, Applications and Realization of

following
(8 Marks)
Multiplexers (MUX): MUX Tree
Demultiplexers (DEMUX): DEMUX Tree, DEMUX as
Decoder
Study of IC 74151, IC 74155
Priority Encoder 8:3, Decimal to BCD Encoder
Tristate Logic, Unidirectional & Bidirectional buffer
ICs: IC 74244 and IC 74245

Amit Nevase
3/12/17 8
 Module IV Sequential Logic Circuit

Sequential Circuits
(12 Marks)
Comparison between Combinational & Sequential
circuits
One bit memory cell: RS Latch- using NAND & NOR
Triggering Methods: Edge & Level Triggering
Flip Flops: SR Flip Flop, Clocked SR FF with preset &
clear, Drawbacks of SR FF
Clocked JK FF with preset & clear, Race around
condition in JK FF, Master Slave JK FF
D and T Flip Flops
Excitation Tables of Flip Flops
Block schematic
3/12/17 and function table of IC 7474,9 IC
Amit Nevase
 Module IV Sequential Logic Circuit
Study of Counters
(8 Marks)
Counter: Modulus of Counter, Types of Counters:
Asynchronous & Synchronous Counters
Asynchronous Counter/Ripple Counter: 4 Bit Up/Down
Counter
Synchronous Counter: Excitation Tables of FFs, 3 Bit
Synchronous Counter, its truth table & waveforms
Block schematic and waveform of IC 7490 as MOD-N
Counter
Shift Registers
(4 Marks)
Logic diagram, AmitTruth
Nevase
Table and waveforms of 4 bit
3/12/17 10
shift registers: SISO, SIPO, PIPO, PISO
 Module V Data Converters

Introduction and Necessity of Code

Converters
(8 Marks)
DAC Types & Comparison of weighted resistor type
(Mathematical Derivation) and R-2R Ladder Type DAC
(Mathematical Derivation upto 3 variable)
ADC Types & Their Comparison
(8 Marks)
Single Slope ADC. Dual Slope ADC, SAR ADC
IC PCF 8591: 8 Bit ADC-DAC

Amit Nevase
3/12/17 11
 Module VI Memories

Principle of Operation & Classification of

memory (10 Marks)
Organization of memories
RAM (Static & Dynamic), Volatile and Non-volatile
ROM (PROM, EPROM, EEPROM)
Flash Memory
Comparison between EEPROM & Flash
Study of Memory ICs

Identification of IC number and their function of

following ICs: IC 2716, IC 7481 and IC 6116
Amit Nevase
3/12/17 12
 Module-III
Combinational
Logic Circuits

Amit Nevase
3/12/17 13
 Specific Objectives

Realize various digital Circuits using

K-map.
Realize various combinational logic
circuits.
Use peripheral devices like buffer.

Amit Nevase
3/12/17 14
Module III Combinational Logic Circuits

Introduction
(8 Marks)
Standard representation of canonical
forms (SOP & POS), Maxterm and
Minterm , Conversion between SOP and
POS forms
K-map reduction techniques upto 4 variables (SOP &
POS form), Design of Half Adder, Full Adder, Half
Subtractor & Full Subtractor using k-Map
Code Converter using K-map: Gray to Binary Binary
to Gray Code Converter (upto 4 bit)
IC 7447 as BCD to 7- Segment decoder driver
IC 7483 as Adder
3/12/17 & Subtractor, 1 Digit BCD Adder15
Amit Nevase
Standard Representation

Any logical expression can be

expressed in the following two forms:
Sum of Product (SOP) Form

Product of Sum (POS) Form

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3/12/17 16
SOP Form

For Example, logical expression given

is;
Sum

Y A.B B.C A.C

Product

Amit Nevase
3/12/17 17
POS Form

For Example, logical expression given

is;
Product

Y ( A B ).( B C ).( A C )
Sum

Amit Nevase
3/12/17 18
Standard or Canonical SOP & POS
Forms

We can say that a logic expression is

said to be in the standard (or
canonical) SOP or POS form if each
product term (for SOP) and sum term
(for POS) consists of all the literals in
their complemented or
uncomplemented form.

Amit Nevase
3/12/17 19
Standard SOP

Y ABC ABC ABC

Each product term
consists all the
literals

Amit Nevase
3/12/17 20
 Standard POS

Y ( A B C ).( A B C ).( A B C )
Each sum term
consists all the
literals

Amit Nevase
3/12/17 21
Examples

Sr.
Expression Type
No.

1 Y AB ABC ABC Non Standard SOP

2 Y AB AB AB Standard SOP

3 Y ( A B ).( A B ).( A B ) Standard POS

4 Y ( A B ).( A B C ) Non Standard POS

Amit Nevase
3/12/17 22
Conversion of SOP form to
Standard SOP

Procedure:
1. Write down all the terms.
2. If one or more variables are missing
in any product term, expand the
term by multiplying it with the sum
of each one of the missing variable
and its complement .
3. Drop out the redundant terms
Amit Nevase
3/12/17 23
 Example 1
Y AB AC BC
onvert given expression into its standard SOP form

Y AB AC BC

Missing literal is A
Missing literal is B

Missing literal is C

Y AB.(C C ) AC .( B B ) BC .( A A)

Term formed by ORing of missing

literal & its complement
Amit Nevase
3/12/17 24
Example 1
Continue.

Y AB.(C C ) AC .( B B ) BC .( A A)

Y ABC ABC ABC ABC ABC ABC

Y ABC ABC ABC ABC ABC ABC

Y ABC ABC ABC ABC

Standard SOP form

Each product term consists all the literals

Amit Nevase
3/12/17 25
Conversion of POS form to
Standard POS

Procedure:
1. Write down all the terms.
2. If one or more variables are missing
in any sum term, expand the term
by adding the products of each one
of the missing variable and its
complement .
3. Drop out the redundant terms
Amit Nevase
3/12/17 26
 Example 2
Y ( A B).( A C ) ( B C )
onvert given expression into its standard SOP form

Y ( A B).( A C ) ( B C )

Missing literal is A
Missing literal is B

Missing literal is C

Y ( A B CC ).( A C B B ).( B C A A)

Term formed by ANDing of missing

literal & its complement
Amit Nevase
3/12/17 27
Example 2
Continue.

Y ( A B CC ).( A C B B ).( B C A A)
Y ( A B C )( A B C ).( A B C )( A B C ).( A B C )( A B C )

Y ( A B C )( A B C )( A B C )( A B C )

Y ( A B C )( A B C )( A B C )( A B C )

Standard POS form

Each sum term consists all the literals

Amit Nevase
3/12/17 28
Concept of Minterm and Maxterm

Minterm: Each individual term in the

standard SOP form is called as
Minterm.

Maxterm: Each individual term in the

standard POS form is called as
Maxterm.

Amit Nevase
3/12/17 29
The concept of minterm and max
term allows us to introduce a very
convenient shorthand notation to
express logic functions

Amit Nevase
3/12/17 30
Minterms & Maxterms for 3
variable/literal logic function
Variables Minterms Maxterms

A B C mi Mi

0 0 0 ABC m 0 A B C M 0

0 0 1 ABC m1 A B C M1
0 1 0 ABC m 2 A B C M 2
0 1 1 ABC m3 A B C M3
1 0 0 ABC m 4 A BC M 4
1 0 1 ABC m5 A B C M5
1 1 0 ABC m 6 A B C M 6
Amit Nevase
1 3/12/17 1 1 ABC m 7 A B C M 7 31
Minterms and maxterms

Each minterm is represented by mi

where i=0,1,2,3,.,2n-1
Each maxterm is represented by Mi
where i=0,1,2,3,.,2n-1
If n number of variables forms the
function, then number of minterms or
maxterms will be 2n
i.e. for 3 variables function f(A,B,C), the
number of minterms or maxterms are 23=8
Amit Nevase
3/12/17 32
Minterms & Maxterms for 2
variable/literal logic function

Variables Minterms Maxterms

A B mi Mi

0 0 AB m 0 A B M0

0 1 AB m1 A B M1
1 0 AB m 2 A B M 2
1 1 AB m3 A B M3

Amit Nevase
3/12/17 33
Representation of Logical expression
using minterm

Y ABC ABC ABC ABC Logical Expression

m7 m3 m4 m5 Corresponding
minterms

Y m7 m3 m 4 m5

Y m(3, 4,5, 7) OR

Y f ( A, B, C ) m(3, 4,5, 7)

where denotes sum of

products
Amit Nevase
3/12/17 34
Representation of Logical expression
using maxterm

Y ( A B C ).( A B C ).( A B C ) Logical Expression

M0 Corresponding
M2 M6
maxterms

Y M 2.M 0.M 6

Y M (0, 2, 6) OR

Y f ( A, B, C ) M (0, 2, 6)

where denotes product

of sum
Amit Nevase
3/12/17 35
Conversion from SOP to POS &
Vice versa

The relationship between the

expressions using minters and
maxterms is complementary.

We can exploit this complementary

relationship to write the expressions
in terms of maxterms if the
expression in terms of minterms is
known and vice versa
Amit Nevase
3/12/17 36
Conversion from SOP to POS &
Vice versa

For example, if a SOP expression for

4 variable is given by,
Y m(0,1, 3, 5, 6, 7,11,12,15)

Then we can get the equivalent POS

expression using the complementary
relationship as follows,
Y M (2, 4,8, 9,10,13,14)
Amit Nevase
3/12/17 37
 Examples
1. Convert the given expression into standard form

Y A BC ABC

2. Convert the given expression into standard form

Y ( A B ).( A C )

Amit Nevase
3/12/17 38
Module III Combinational Logic Circuits

Introduction
(8 Marks)
Standard representation of canonical forms (SOP &
POS), Maxterm and Minterm , Conversion between
SOP and POS forms
K-map reduction techniques upto 4
variables (SOP & POS form), Design of Half
Adder, Full Adder, Half Subtractor & Full Subtractor
using k-Map
Code Converter using K-map: Gray to Binary, Binary
to Gray Code Converter (upto 4 bit)
IC 7447 as BCD to 7- Segment decoder driver
IC 7483 as Adder
3/12/17
Amit& Subtractor, 1 Digit BCD Adder39
Nevase
Karnaugh Map (K-map)

In the algebraic method of

simplification, we need to write
lengthy equations, find the common
terms, manipulate the expressions
etc., so it is time consuming work.

Thus K-map is another

simplification technique to reduce
the Boolean equation.
Amit Nevase
3/12/17 40
Karnaugh Map (K-map)

It overcomes all the disadvantages of

algebraic simplification techniques.

The information contained in a truth

table or available in the SOP or POS
form is represented on K-map.

Amit Nevase
3/12/17 41
Karnaugh Map (K-map)

K-map Structure - 2 Variable

A & B are variables or inputs
0 & 1 are values of A & B
2 variable k-map consists of 4 boxes i.e. 22=4

A
B 0 1

Amit Nevase
3/12/17 42
Karnaugh Map (K-map)

K-map Structure - 2 Variable

Inside 4 boxes we have enter values of Y
i.e. output

A A
A A
B 0 1 B 0 1

0 AB AB 0 m0 m1
B
B 1 AB AB 1 m2 m3
K-map & its associated minterms
Amit Nevase
3/12/17 43
Karnaugh Map (K-map)
Relationship between Truth Table & K-map
A A
A
B 0 1

A B Y 0 0 0
B
0 0 0 B 1 1 1

0 1 1

1 0 0 B B
B
A 0 1
1 1 1
A 0 0 1

A 1 0 1
Amit Nevase
3/12/17 44
Karnaugh Map (K-map)
K-map Structure - 3 Variable
A, B & C are variables or inputs
3 variable k-map consists of 8 boxes i.e. 23=8
AB
C A
BC 0 1
0
0
1 0
0
1
BC
0 0 1 1 1
A
0 1 1 0 1
1
0 0
1

Amit Nevase
3/12/17 45
Karnaugh Map (K-map)
3 Variable K-map & its associated
product terms
AB
C 0 0 1 1 A
0 1 1 0 BC 0 1
0 ABC ABC ABC ABC
0 ABC ABC
1 ABC ABC ABC ABC 0
0 ABC ABC
1
BC
1 ABC ABC
A 0 0 1 1
0 1 1 0 1
ABC ABC ABC 1 ABC ABC
0 ABC
0
1 ABC ABC ABC ABC

Amit Nevase
3/12/17 46
Karnaugh Map (K-map)
3 Variable K-map & its associated
minterms
AB
0 0 1 1
C A
0 1 1 0
BC 0 1
0 m0 m 2 m6 m 4
0 m0 m4
1 m1 m3 m 7 m5 0
0 m1 m5
1

A
BC
0 0 1 1 1 m3 m 7
0 1 1 0 1
0 m0 m1 m3 m 2 1 m2 m6
0
1 m 4 m5 m 7 m6
Amit Nevase
3/12/17 47
Karnaugh Map (K-map)
K-map Structure - 4 Variable
A, B, C & D are variables or inputs
4 variable k-map consists of 16 boxes i.e. 2 4=16

AB C
C 0 0 1 1 A D 0 0 1 1
D 0 1 1 0 B 0 1 1 0
0 0
0 0
0 0
1 1
1 1
1 1
1 1
0 0

Amit Nevase
3/12/17 48
Karnaugh Map (K-map)
4 Variable K-map and its associated
product terms

AB C
C 0 0 1 1 A D 0 0 1 1
D 0 1 1 0 B 0 1 1 0
0 ABCD ABCD ABCD ABCD 0 ABCD ABCD ABCD ABCD
0 0
0 ABCD ABCD ABCD ABCD 0 ABCD ABCD ABCD ABCD
1 1
1 ABCD ABCD ABCD ABCD 1 ABCD ABCD ABCD ABCD
1 1
1 ABCD ABCD ABCD ABCD 1 ABCD ABCD ABCD ABCD
0 0

Amit Nevase
3/12/17 49
Karnaugh Map (K-map)
4 Variable K-map and its associated
minterms

AB C
C 0 0 1 1 A D 0 0 1 1
D 0 1 1 0 B 0 1 1 0
0 m0 m4 m12 m8 0 m0 m1 m3 m2
0 0
0 m1 m5 m13 m9 0 m4 m5 m7 m6
1 1
1 m3 m7 m15 m11 1 m12 m13 m15 m14
1 1
1 m2 m6 m11 m10 1 m8 m9 m11 m10
0 0

Amit Nevase
3/12/17 50
Representation of Standard SOP
form expression on K-map
For example, SOP equation is given as
Y ABC ABC ABC ABC ABC
The given expression is in the standard SOP form.
Each term represents a minterm.
We have to enter 1 in the boxes corresponding to each minterm
as below
ABC ABC
BC BC BC BC BC
A 0 0 1 1
0 1 1 0
A 0 1 1 0 0

A 1 1 0 1 1 ABC

3/12/17 ABC Amit Nevase ABC 51

Simplification of K-map

Once we plot the logic function or

truth table on K-map, we have to use
the grouping technique for
simplifying the logic function.
Grouping means the combining the
terms in adjacent cells.
The grouping of either 1s or 0s
results in the simplification of
boolean expression.
Amit Nevase
3/12/17 52
Simplification of K-map

If we group the adjacent 1s then the

result of simplification is SOP form
If we group the adjacent 0s then the
result of simplification is POS form

Amit Nevase
3/12/17 53
Grouping

While grouping, we should group most

number of 1s.
The grouping follows the binary rule i.e we
can group 1,2,4,8,16,32,..number of 1s.
We cannot group 3,5,7,number of 1s
Pair: A group of two adjacent 1s is called as
Pair
Quad: A group of four adjacent 1s is called
as Quad
Octet: A group of eight adjacent 1s is called
as Octet
Amit Nevase
3/12/17 54
Grouping of Two Adjacent 1s :
Pair
A pair eliminates 1 variable
ABC ABC

BC BC BC BC BC
A 0 0 1 1
0 1 1 0
A 0 0 0 1 1 Y ABC ABC
A 1 0 0 0 0 Y AB (C C )
Y AB (Q C C 1)

Amit Nevase
3/12/17 55
 Grouping of Two Adjacent 1s :
Pair
BC BC BC BC BC BC BC BC BC BC
0 0 1 1 A 0 0 1 1
A
0 1 1 0 0 1 1 0
0 0 0 0 A 0 0 1 1 1
A 0

A 1 1 0 0 1 A 1 0 0 1 0

BC BC BC BC BC B B B
A 0 0 1 1 A 0 1
0 1 1 0
A 0 0 1 0 0 A 0 1 1

A 1 0 1 0 0 A 1 1 0

Amit Nevase
3/12/17 56
 Grouping of Two Adjacent 1s :
Pair
CD CD CD CD CD
A 0 0 1 1
B 0 1 1 0
AB 0 0 1 0 0
0
AB 0 0 0 0 0
1
AB 1 0 0 0 0
1
AB 1 0 1 0 0
0

Amit Nevase
3/12/17 57
 Possible Grouping of Four
Adjacent 1s : Quad
A Quad eliminates 2 variable

CD CD CD CD CD CD CD CD CD CD
A 0 0 1 1 A 0 0 1 1
B 0 1 1 0 B 0 1 1 0
AB 0 0 0 0 0 AB 0 0 1 0 0
0 0
AB 0 0 0 0 0 AB 0 0 1 0 0
1 1
AB 1 0 0 0 0 AB 1 0 1 0 0
1 1
AB 1 1 1 1 1 AB 1 0 1 0 0
0 0

Amit Nevase
3/12/17 58
 Possible Grouping of Four
Adjacent 1s : Quad
A Quad eliminates 2 variable

CD CD CD CD CD CD CD CD CD CD
A 0 0 1 1 A 0 0 1 1
B 0 1 1 0 B 0 1 1 0
AB 0 0 0 0 0 AB 0 0 1 1 0
0 0
AB 0 1 1 0 0 AB 0 0 0 0 0
1 1
AB 1 1 1 0 0 AB 1 0 0 0 0
1 1
AB 1 0 0 0 0 AB 1 0 1 1 0
0 0

Amit Nevase
3/12/17 59
 Possible Grouping of Four
Adjacent 1s : Quad
A Quad eliminates 2 variable

CD CD CD CD CD CD CD CD CD CD
A 0 0 1 1 A 0 0 1 1
B 0 1 1 0 B 0 1 1 0
AB 0 1 0 0 1 AB 0 0 0 0 0
0 0
AB 0 0 0 0 0 AB 0 1 0 0 1
1 1
AB 1 0 0 0 0 AB 1 1 0 0 1
1 1
AB 1 1 0 0 1 AB 1 0 0 0 0
0 0

Amit Nevase
3/12/17 60
 Possible Grouping of Four
Adjacent 1s : Quad
A Quad eliminates 2 variable

CD CD CD CD CD CD CD CD CD CD
A 0 0 1 1 A 0 0 1 1
B 0 1 1 0 B 0 1 1 0
AB 0 0 0 0 0 AB 0 0 0 0 0
0 0
AB 0 0 1 1 1 AB 0 0 1 1 0
1 1
AB 1 0 1 1 1 AB 1 0 1 1 0
1 1
AB 1 0 0 0 0 AB 1 0 1 1 0
0 0

Amit Nevase
3/12/17 61
 Possible Grouping of Eight
Adjacent 1s : Octet
A Octet eliminates 3 variable

CD CD CD CD CD CD CD CD CD CD
A 0 0 1 1 A 0 0 1 1
B 0 1 1 0 B 0 1 1 0
AB 0 0 0 0 0 AB 0 0 1 1 0
0 0
AB 0 0 0 0 0 AB 0 0 1 1 0
1 1
AB 1 1 1 1 1 AB 1 0 1 1 0
1 1
AB 1 1 1 1 1 AB 1 0 1 1 0
0 0

Amit Nevase
3/12/17 62
 Possible Grouping of Eight
Adjacent 1s : Octet
A Octet eliminates 3 variable

CD CD CD CD CD CD CD CD CD CD
A 0 0 1 1 A 0 0 1 1
B 0 1 1 0 B 0 1 1 0
AB 0 1 1 1 1 AB 0 1 0 0 1
0 0
AB 0 0 0 0 0 AB 0 1 0 0 1
1 1
AB 1 0 0 0 0 AB 1 1 0 0 1
1 1
AB 1 1 1 1 1 AB 1 1 0 0 1
0 0

Amit Nevase
3/12/17 63
Rules for K-map simplification
1. Groups may not include any cell
containing a zero.

A
A A A
A A
B 0 1 B 0 1

0 0
B 0 B 0

B 1 1 B 1 1 1

Not Accepted Accepted

Amit Nevase
3/12/17 64
Rules for K-map simplification
2. Groups may be horizontal or vertical, but may
not be diagonal

A
A A A
A A
B 0 1 B 0 1

0 1 0 1
B 0 B 0

B 1 1 0 B 1 1 1

Not Accepted Accepted

Amit Nevase
3/12/17 65
 Rules for K-map simplification
3. Groups must contain 1,2,4,8 or in general 2 n cells

BC BC BC BC BC BC BC BC BC BC
A 0 0 1 1 A 0 0 1 1
0 1 1 0 0 1 1 0
0 1 1 1 A 0 0 1 1 1
A 0

A 1 0 0 0 0 A 1 0 0 0 0

A
A A A
A A
B 0 1 B 0 1

1 1 1 1
B 0 B 0

B 1 0 1 B 1 0 1

Amit Nevase
3/12/17
Not Accepted Accepted 66
 Rules for K-map simplification
4. Each group should be as large as possible

BC BC BC BC BC BC BC BC BC BC
A 0 0 1 1 A 0 0 1 1
0 1 1 0 0 1 1 0
1 1 1 1 A 0 1 1 1 1
A 0

A 1 0 0 1 1 A 1 0 0 1 1

Not Accepted Accepted

Amit Nevase
3/12/17 67
Rules for K-map simplification

5. Each cell containing a one must be in at least one group

BC BC BC BC BC
A 0 0 1 1
0 1 1 0
A 0 0 0 0 1

A 1 0 0 1 0

Amit Nevase
3/12/17 68
Rules for K-map simplification

6. Groups may be overlap

BC BC BC BC BC
A 0 0 1 1
0 1 1 0
A 0 1 1 1 1

A 1 0 0 1 1

Amit Nevase
3/12/17 69
 Rules for K-map simplification

7. Groups may wrap around the table. The leftmost cell in

a row may be grouped with rightmost cell and the top
cell in a column may be grouped with bottom cell

CD CD CD CD CD
A 0 0 1 1
B 0 1 1 0 BC BC BC BC BC
AB 0 1 1 1 1 0 0 1 1
A
0 0 1 1 0
AB 0 0 0 0 0 A 0 1 0 0 1
1
AB 1 0 0 0 0 A 1 1 0 0 1
1
AB 1 1 1 1 1
0
Amit Nevase
3/12/17 70
 Rules for K-map simplification
8. There should be as few groups as possible, as long as
this does not contradict any of the previous rules.

BC BC BC BC BC BC BC BC BC BC
A 0 0 1 1 A 0 0 1 1
0 1 1 0 0 1 1 0
1 1 1 1 A 0 1 1 1 1
A 0

A 1 0 0 1 1 A 1 0 0 1 1

Not Accepted Accepted

Amit Nevase
3/12/17 71
Rules for K-map simplification

9. A pair eliminates one variable.

10. A Quad eliminates two variables.

11. A octet eliminates three variables

Amit Nevase
3/12/17 72
 Example 1

For the given K-map write simplified Boolean expression

AB AB AB AB AB
C 0 0 1 1
0 1 1 0
C 0 0 1 1 1

C 1 0 0 1 0

Amit Nevase
3/12/17 73
 Example 1
continue..

AB AB AB AB AB
C 0 0 1 1
0 1 1 0
C 0 0 1 1 1 AC

C 1 0 0 1 0

BC AB

Simplified Boolean expression

Y BC AB AC

Amit Nevase
3/12/17 74
 Example 2

For the given K-map write simplified Boolean expression

AB AB AB AB AB
C 0 0 1 1
0 1 1 0
C 0 1 1 0 1

C 1 1 0 0 1

Amit Nevase
3/12/17 75
 Example 2
continue..

AB AB AB AB AB
C 0 0 1 1
0 1 1 0
C 0 1 1 0 1

C 1 1 0 0 1

AC B

Simplified Boolean expression

Y B AC

Amit Nevase
3/12/17 76
Example 3

A logical expression in the standard

SOP form is as follows;
Y ABC ABC ABC ABC

Minimize it with using the K-map

technique

Amit Nevase
3/12/17 77
 Example 3
continue
Y ABC ABC ABC ABC

BC BC BC BC BC AB
A 0 0 1 1
0 1 1 0
A 0 1 0 1 1

A 1 0 1 0 0

AC
ABC

Simplified Boolean expression

Y AC AB ABC
Amit Nevase
3/12/17 78
Example 4

A logical expression representing a

logic circuit is;
Y m(0,1, 2, 5,13,15)

Draw the K-map and find the

minimized logical expression

Amit Nevase
3/12/17 79
 Example 4
continue..

Y m(0,1, 2, 5,13,15)

CD CD CD
CD CD
A 0 0 1 1 ABD
B 0 0 1 1 1 3 0 2
AB 0 1 1 0 1
0 4 7
5 6
AB 0 0 1 0 0
1 Simplified Boolean expression
AB 1 1 1 1
1 02 13 15 04
1 Y ABD ACD ABD
8 9 1 10
AB 1 0 0 01 0
0

ACD ABD
Amit Nevase
3/12/17 80
Example 5

Minimize the following Boolean

expression using K-map ;

f ( A, B, C , D ) m(1,3, 5, 9,11,13)

Amit Nevase
3/12/17 81
 Example 5
continue..
f ( A, B , C , D ) m(1, 3, 5, 9,11,13)

CD CD CD
CD CD
A 0 0 1 1
B 0 0 1 1 1 3 0 2
AB 0 0 1 1 0
0 4 7
5 6
AB 0 0 1 0 0
1 Simplified Boolean expression
AB 1 1 1 1
1 02 13 05 04
1 f BD CD
8 9 1 10
AB 1 0 1 11 0 f D( B C )
0

BD CD
Amit Nevase
3/12/17 82
Example 6

Minimize the following Boolean

expression using K-map ;
f ( A, B, C , D ) m(4,5,8,9,11,12,13,15)

Amit Nevase
3/12/17 83
 Example 6
continue..

f ( A, B, C , D ) m(4,5,8,9,11,12,13,15)

CD CD CD
CD CD
A 0 0 1 1
B 0 0 1 1 1 3 0 2 BC
AB 0 0 0 0 0
0 4 7
5 6
AB 0 1 1 0 0
1 Simplified Boolean expression
AB 1 1 1 1
1 12 13 15 04
1 f BC AC AD
8 9 1 10
AB 1 1 1 11 0
0

AC AD
Amit Nevase
3/12/17 84
Example 7

Minimize the following Boolean

expression using K-map ;
f 2( A, B, C , D) m(0,1, 2, 3,11,12,14,15)

Amit Nevase
3/12/17 85
 Example 7
continue..

f 2( A, B, C , D) m(0,1, 2,3,11,12,14,15)

CD CD CD
CD CD
A 0 0 1 1
B 0 0 1 1 1 3 0 2 AB
AB 0 1 1 1 1
0 4 7
5 6
AB 0 0 0 0 0
1 Simplified Boolean expression
AB 1 1 1 1
1 12 03 15 14
1 f 2 AB ABD ACD
8 9 1 10
AB 1 0 0 11 0
0

ABD ACD

Amit Nevase
3/12/17 86
Example 8

Solve the following expression with K-

maps;
f 1( A, B, C ) m(0,1,3, 4,5)
1. f 2( A, B, C ) m(0,1, 2,3, 6, 7)
2.

Amit Nevase
3/12/17 87
 Example 8
continue

f 1( A, B, C ) m(0,1, 3, 4, 5) f 2( A, B , C ) m(0,1, 2, 3, 6, 7)

AC
BC BC BC
BC BC BC BC BC
BC BC
A 0 0 1 1 A 0 0 1 1
0 0 1 1 1 3 0 2 0 0 1 1 1 3 0 2
1 1 1 0 A 0 1 1 1 1
A 0
4 5 7 6 4 5 7 6
A 1 1 1 0 0 A 1 0 0 1 1

A B
B
Simplified Boolean expression
Simplified Boolean expression
f 2 A B
f 1 AC B

Amit Nevase
3/12/17 88
Example 9

Simplify ;

f ( A, B, C , D) m(0,1, 4,5, 7,8,9,12,13,15)

Amit Nevase
3/12/17 89
 Example 9
continue..

f ( A, B, C , D) m(0,1, 4,5, 7,8,9,12,13,15)

CD CD CD
CD CD
A 0 0 1 1
B 0 0 1 1 1 3 0 2
AB 0 1 1 0 0
0 4 7
5 6
AB 0 1 1 1 0
1 Simplified Boolean expression
AB 1 1 1 1
1 12 13 15 04
1 f C BD
8 9 1 10
AB 1 1 1 01 0
0

C BD
Amit Nevase
3/12/17 90
Example 10

Solve the following expression with K-

maps;
f 1( A, B, C , D) m(0,1, 3, 4,5, 7)
1. f 2( A, B, C ) m(0,1,3, 4, 5, 7)
2.

Amit Nevase
3/12/17 91
 Example 10
continue

f 1( A, B, C , D) m(0,1,3, 4,5, 7) f 2( A, B, C ) m(0,1, 3, 4, 5, 7)

CD CD CD
CD CD
A 0 0 1 1
BC BC BC
BC BC
B 0 0 1 1 1 3 0 2
1 1 0 0 A 0 0 1 1
AB 0
0 0 1 1 1 3 0 2
0 4 7 1 1 1 0
5 6 A 0
AB 0 1 1 1 0
1 4 5 7 6
AB 1 1 1 1 A 1 1 1 1 0
1 02 03 05 04
1
8 9 1 10 B C
AB 1 0 0 01 0
0
Simplified Boolean expression

AC AD f 2 BC
Simplified Boolean expression
f 1 AC AD
Amit Nevase
3/12/17 92
K-map and dont care conditions

For SOP form we enter 1s

corresponding to the combinations of
input variables which produce a high
output and we enter 0s in the
remaining cells of the K-map.
For POS form we enter 0s
corresponding to the combinations of
input variables which produce a high
output and we enter 1s in the
remaining cells of the K-map.
3/12/17
Amit Nevase
93
K-map and dont care conditions

But it is not always true that the cells

not containing 1s (in SOP) will
contain 0s, because some
combinations of input variable do not
occur.
Also for some functions the outputs
corresponding to certain
combinations of input variables do
not matter.
Amit Nevase
3/12/17 94
K-map and dont care conditions

In such situations we have a freedom

to assume a 0 or 1 as output for each
of these combinations.
These conditions are known as the
Dont Care Conditions and in the K-
map it is represented as X, in the
corresponding cell.
The dont care conditions may be
assumed to be 0 or 1 as per the need
for simplification
3/12/17
Amit Nevase
95
K-map and dont care conditions -
Example

Simplify ;

f ( A, B, C , D) m(1,3, 7,11,15) d (0, 2,5)

Amit Nevase
3/12/17 96
K-map and dont care conditions -
Example
f ( A, B, C , D ) m(1, 3, 7,11,15) d (0, 2, 5)

CD CD CD
CD CD
A 0 0 1 1
B 0 0 1 1 1 3 0 2
AB 0 X 1 1 X
0 4 7
5 6
AB 0 0 X 1 0
1 Simplified Boolean expression
AB 1 1 1 1
1 02 03 15 04
1 f CD AB AD
8 9 1 10
AB 1 0 0 11 0
0

AB AD CD

Amit Nevase
3/12/17 97
Module III Combinational Logic Circuits

Introduction
(8 Marks)
Standard representation of canonical forms (SOP &
POS), Maxterm and Minterm , Conversion between
SOP and POS forms
K-map reduction techniques upto 4 variables (SOP &
POS form), Design of Half Adder, Full
Adder, Half Subtractor & Full Subtractor
using k-Map
Code Converter using K-map: Gray to Binary, Binary
to Gray Code Converter (upto 4 bit)
IC 7447 as BCD to 7- Segment decoder driver
IC 7483 as Adder
3/12/17
Amit& Subtractor, 1 Digit BCD Adder98
Nevase
 Half Adder

Half adder is a combinational logic

circuit with two inputs and two
outputs.
It is a basic building block for
addition of two single bit numbers.
A Sum

Inputs Half Outputs

Adder
B Carry

Amit Nevase
3/12/17 99
 Half Adder

Truth Table

Input Output
Sum
A B Carry (C)
(S)
0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Amit Nevase
3/12/17 100
 Half Adder
K-map for Sum Output:
A
A A
B 0 1
S AB AB
0 1
B 0
S A B
B 1 1 0

K-map for Carry Output:

A
A A
B 0 1

B 0 0 0 C AB

B 1 0 1

Amit Nevase
3/12/17 101
 Half Adder

Logic Diagram:

A
S A B
B

C AB

Amit Nevase
3/12/17 102
 Half Adder
gic Diagram using Basic Gates:
A B

S A B

C AB

Amit Nevase
3/12/17 103
 Full Adder

Full adder is a combinational logic

circuit with three inputs and two
outputs.

A Sum

Inputs B Full Outputs

Adder
Carry

Cin
Amit Nevase
3/12/17 104
 Full Adder

Truth Table
Inputs Outputs

A B Cin Sum (S) Carry (C)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
Amit Nevase
3/12/17 105
 Full Adder

K-map for Sum Output:

BC BC BC BC BC
A 0 0 1 1
S ABC ABC ABC ABC
0 1 1 0
A 0 0 1 0 1
S ABC ABC ABC ABC
A 1 1 0 1 0 S C ( AB AB ) C ( AB AB )
Let AB AB X
ABC
ABC ABC S C( X ) C( X )
ABC

S CX
Let X A B
Q S C A B
Amit Nevase
3/12/17 106
 Full Adder

K-map for Carry Output:

BC BC BC BC BC
A 0 0 1 1
0 1 1 0
A 0 0 0 1 0
C AB BC AC
A 1 0 1 1 1

BC
AB
AC

Amit Nevase
3/12/17 107
 Full Adder
Logic Diagram:
A B C

S A B C

C AB BC AC

Amit Nevase
3/12/17 108
Full Adder using Half Adders

A S0 S1 Sum
HA1 HA2
B C0 C1

C
Carry

Amit Nevase
3/12/17 109
 Half Subtractor

Half subtractor is a combinational

logic circuit with two inputs and two
outputs.
It is a basic building block for
subtraction of two single bit
numbers.
A Difference

Inputs Half Outputs

Subtractor
B Borrow

Amit Nevase
3/12/17 110
 Half Subtractor

Truth Table

Input Output
Differe
A B nce Borrow (B)
(D)
0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Amit Nevase
3/12/17 111
 Half Subtractor
-map for Difference Output:
A
A A
B 0 1
D AB AB
0 1
B 0
D A B
B 1 1 0

-map for Borrow Output:

A
A A
B 0 1

0 1
B 0 B AB
B 1 0 0

Amit Nevase
3/12/17 112
 Half Subtractor

Logic Diagram:

A
D A B
B

B AB

Amit Nevase
3/12/17 113
 Half Subtractor
gic Diagram using Basic Gates:
A B

D A B

B AB

Amit Nevase
3/12/17 114
 Full Subtractor

Full subtractor is a combinational

logic circuit with three inputs and two
outputs.

A Difference

Inputs B Full Outputs

Subtractor
Borrow

Bin
Amit Nevase
3/12/17 115
 Full Subtractor

Truth Table
Inputs Outputs

A B Bin (C) Difference (D) Borrow (B0)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
Amit Nevase
3/12/17 116
 Full Subtractor

-map for Difference Output:

BC BC BC BC BC
A 0 0 1 1
D ABC ABC ABC ABC
0 1 1 0
A 0 0 1 0 1
D ABC ABC ABC ABC
A 1 1 0 1 0 D C ( AB AB ) C ( AB AB )
Let AB AB X
ABC
ABC ABC D C( X ) C( X )
ABC

DCX
Let X A B
Q D C A B
Amit Nevase
3/12/17 117
 Full Subtractor

K-map for Borrow Output:

BC BC BC BC BC
A 0 0 1 1
0 1 1 0
A 0 0 1 1 1
B 0 AB BC AC
A 1 0 0 1 0

BC
AB
AC

Amit Nevase
3/12/17 118
 Full Subtractor
Logic Diagram:
A B C

D A B C

B 0 AB BC AC

Amit Nevase
3/12/17 119
Full Subtractor using Half
Subtractor

A D0 D1
Differenc
HS1 HS2 e

B B0 B1

C
Borrow

Amit Nevase
3/12/17 120
Module III Combinational Logic Circuits

Introduction
(8 Marks)
Standard representation of canonical forms (SOP &
POS), Maxterm and Minterm , Conversion between
SOP and POS forms
K-map reduction techniques upto 4 variables (SOP &
POS form), Design of Half Adder, Full Adder, Half
Subtractor & Full Subtractor using k-Map
Code Converter using K-map: Gray to
Binary, Binary to Gray Code Converter
(upto 4 bit)
IC 7447 as BCD to 7- Segment decoder driver
IC 7483 as Adder
3/12/17 & Subtractor, 1 Digit BCD Adder121
Amit Nevase
 Design of Binary to Gray Code
Converter
Block Diagram:

B3 G3
B2 Binary to Gray G2
Binary Code Gray
Inputs B1 G1 Outputs
converter
B0 G0

Amit Nevase
3/12/17 122
 Design of Binary to Gray Code
Converter
Truth Table :
Binary Inputs Gray Outputs Binary Inputs Gray Outputs

B3 B2 B1 B0 G3 G2 G1 G0 B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0

0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1

0 0 1 0 0 0 1 1 1 0 1 0 1 1 1 1

0 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0

0 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0

0 1 0 1 0 1 1 1 1 1 0 1 1 0 1 1

0 1 1 0 0 1 0 1 1 1 1 0 1 0 0 1

0 1
3/12/17 1 1 0 1 Amit0Nevase0 1 1 1 1 1 0 0123 0
 Design of Binary to Gray Code
Converter
K-map for G0:

B1B0 B1B 0 B1B 0 B1B 0 B1B 0

B3B2 0 0 1 1
0 0 1 1 1 3 0 2
B3 B 2 0 0 1 0 1
0 4
B 3B 2 0 0 1
5
0
7
1
6
G 0 B1B 0 B1B 0
1
1 1 1 1
B3 B 2 1 02 13 05 14 G 0 B 0 B1
1
8 9 1 10
B3 B 2 1 0 1 01 1
0

B1B 0 B1B 0
Amit Nevase
3/12/17 124
 Design of Binary to Gray Code
Converter
K-map for G1:

B1B0 B1B 0 B1B 0 B1B 0 B1B 0

B3B2 0 0 1 1
0 0 1 1 1 3 0 2
B3 B 2 0 0 0 1 1
0 4
B 3B 2 0 1 1
5
0
7
0
6
G1 B 2B1 B 2 B1
1
1 1 1 1
B3 B 2 1 12 13 05 04 G1 B 2 B1
1
8 9 1 10
B3 B 2 1 0 0 11 1
0

B 2 B1 B 2B1
Amit Nevase
3/12/17 125
 Design of Binary to Gray Code
Converter
K-map for G2:

B1B0 B1B 0 B1B 0 B1B 0 B1B 0

B3B2 0 0 1 1
0 0 1 1 1 3 0 2
B3 B 2 0 0 0 0 0
0 4
B 3B 2 0 1 1
5
1
7
1
6
G 2 B 3B 2 B 3 B 2
1
1 1 1 1
B3 B 2 1 02 03 05 04 G 2 B3 B 2
1
8 9 1 10
B3 B 2 1 1 1 11 1
0

B3 B 2 B 3B 2
Amit Nevase
3/12/17 126
 Design of Binary to Gray Code
Converter
K-map for G3:

B1B0 B1B 0 B1B 0 B1B 0 B1B 0

B3B2 0 0 1 1
0 0 1 1 1 3 0 2
B3 B 2 0 0 0 0 0
0
B 3B 2 0 0
4
0
5
0
7
0
6 G3 B3
1
1 1 1 1
B3 B 2 1 12 13 15 14
1
8 9 1 10
B3 B 2 1 1 1 11 1
0

B3
Amit Nevase
3/12/17 127
 Design of Binary to Gray Code
Converter
Logic Diagram:
B3 B2 B1 B0

G3

G 2 B3 B 2

G1 B2 B1

G 0 B1 B 0

Amit Nevase
3/12/17 128
 Design of Gray to Binary Code
Converter
Block Diagram:

G3 B3
G2 Gray to Binary B2 Binary
Gray
Inputs G Code B1
Outputs
1
converter
G0 B0

Amit Nevase
3/12/17 129
 Design of Gray to Binary Code
Converter
Truth Table :
Binary Binary
Gray Inputs Gray Inputs
Outputs Outputs
G3 G2 G1 G0 B3 B2 B1 B0 G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
1 0 0 0 1 1 0 0
0 0 0 1 0 0 0 1
1 0 0 1 1 1 0 1
0 0 1 0 0 0 1 1
1 0 1 0 1 1 1 1
0 0 1 1 0 0 1 0
1 0 1 1 1 1 1 0
0 1 0 0 0 1 1 0
1 1 0 0 1 0 1 0
0 1 0 1 0 1 1 1
1 1 0 1 1 0 1 1
0 1 1 0 0 1 0 1
1 1 1 0 1 0 0 1
0 1 1 1 0 1 Amit0Nevase0
3/12/17 1 1 1 1 1 0 0130 0
 Design of Gray to Binary Code
Converter
K-map for B0: G1G0 G1G 0 G1G 0 G1G 0 G1G 0
G3G2 0 0 1 1
0 0 1 1 1 3 0 2
G 3G 2 0 0 1 0 1
0 4 7
5 6
G 3G 2 0 1 0 1 0
1
1 1 1 1
G 3G 2 1 02 13 05 14
1
8 9 1 10
G 3G 2 1 1 0 11 0
0

B 0 G 3G 2G1G 0 G 3G 2G1G 0 G 3G 2G1G 0 G 3G 2G1G 0

G 3G 2G1G 0 G 3G 2G1G 0 G 3G 2G1G 0 G 3G 2G1G 0
B 0 G 3 G 2 G1 G 0

Amit Nevase
3/12/17 131
 Design of Gray to Binary Code
Converter
K-map for B1: G1G0 G1G 0 G1G 0 G1G 0 G1G 0
G3G2 0 0 1 1
0 0 1 1 1 3 0 2
G 3G 2 0 0 0 1 1
0 4 7
5 6
G 3G 2 0 1 1 0 0
1
1 1 1 1
G 3G 2 1 02 03 15 14
1
8 9 1 10
G 3G 2 1 1 1 01 0
0

B1 G 3G 2G1 G 3G 2G1 G 3G 2G1 G 3G 2G1

B1 G 3 G 2 G1

Amit Nevase
3/12/17 132
 Design of Gray to Binary Code
Converter
K-map for B2: G1G0 G1G 0 G1G 0 G1G 0 G1G 0
G3G2 0 0 1 1
0 0 1 1 1 3 0 2
G 3G 2 0 0 0 0 0
0 4 7
5 6
G 3G 2 0 1 1 1 1
1
1 1 1 1
G 3G 2 1 02 03 05 04
1
8 9 1 10
G 3G 2 1 1 1 11 1
0

B 2 G 3G 2 G 3G 2

B1 G 3 G 2

Amit Nevase
3/12/17 133
 Design of Gray to Binary Code
Converter
K-map for B3: G1G0 G1G 0 G1G 0 G1G 0 G1G 0
G3G2 0 0 1 1
0 0 1 1 1 3 0 2
G 3G 2 0 0 0 0 0
0 4 7
5 6
G 3G 2 0 0 0 0 0
1
1 1 1 1
G 3G 2 1 12 13 15 14
1
8 9 1 10
G 3G 2 1 1 1 11 1
0

B3 G 3

Amit Nevase
3/12/17 134
 Design of Gray to Binary Code
Converter
Logic Diagram:
G3 G2 G1 G0

B3

B2 G 3 G2

B1 G1 G 2 G 3

B 0 G 0 G1 G 2 G 3

Amit Nevase
3/12/17 135
Module III Combinational Logic Circuits

Introduction
(8 Marks)
Standard representation of canonical forms (SOP &
POS), Maxterm and Minterm , Conversion between
SOP and POS forms
K-map reduction techniques upto 4 variables (SOP &
POS form), Design of Half Adder, Full Adder, Half
Subtractor & Full Subtractor using k-Map
Code Converter using K-map: Gray to Binary, Binary
to Gray Code Converter (upto 4 bit)
IC 7447 as BCD to 7- Segment decoder
driver
IC 7483 as Adder
3/12/17 & Subtractor, 1 Digit BCD Adder136
Amit Nevase
Seven Segment Display

f b
g

e c

d d
p

Amit Nevase
3/12/17 137
 Seven Segment Display
Segments
Displa
Seven
y
Segment
a b c d e f g Numb
Display
er

ON ON ON ON ON ON OFF 0
OFF ON ON OFF OFF OFF OFF 1
ON ON OFF ON ON OFF ON 2
ON ON ON ON OFF OFF ON 3
OFF ON ON OFF OFF ON ON 4
ON OFF ON ON OFF ON ON 5
ON OFF ON ON ON ON ON 6
ON ON ON OFF OFF OFF OFF 7
ON ON ON ON ON ON ON 8
Amit Nevase
3/12/17 138
ON ON ON ON OFF ON ON 9
Types of Seven Segment Display

Common Cathode Display

Common Anode Display

Amit Nevase
3/12/17 139
Common Anode Display

+Vcc

R R R R R R R R

a b c d e f g dp

Amit Nevase
3/12/17 140
 Common Anode Display
+Vcc

R
b

R
R
c
d

R
BCD to
BCD e

R
7 Segment
Input Decoder
f

R
g
R
R

dp
Amit Nevase
3/12/17 141
Common Cathode Display

a b c d e f g dp

R R R R R R R R

Amit Nevase
3/12/17 142
 Common Cathode Display

R
b

R
c

R
BCD to d
7 Segment

R
BCD e
Decoder
Input

R
f

R
g

R
dp
R

Amit Nevase
3/12/17 143
BCD to 7 Segment Decoder Driver
ICs
Sr. No. IC Number Specifications

Active Low open collector outputs,

IC 7446,
1 maximum voltage 30 V,
IC 74246
maximum current sinking capability 40mA

Active Low open collector outputs,

IC 7447,
maximum voltage 15 V,
2 IC 74247
maximum current sinking capability 40mA

Active High open collector outputs,

Pull up resistor 2kohm,
IC 7448,
3 maximum voltage 5.5 V,
IC 74248
maximum current sinking capability 6.4mA

Amit Nevase
3/12/17 144
IC 7447

Pins Description

A,B,C,D BCD Inputs

a to g Active Low Outputs

LT Lamp Test

Ripple Blanking Input

RBI

BI Blanking Input

RBO Ripple Blanking output

Amit Nevase
3/12/17 145
 RBI - Ripple Blanking Input

For the normal decoding operation, this

input should be connected to logic 1.
If RBI is connected to ground, then it
switches off the display when BCD inputs
corresponding to 0.
For non-zero BCD inputs, the decoder
output will be normal and the BCD number
will be displayed.
RBI=0 is connected for blanking out the
leading zeros in multidigit displays.
Amit Nevase
3/12/17 146
 BI Blanking Input

If BI is connected to 0, then the

display will be switched off
irrespective of the BCD input.
This feature is used in the
multiplexed display in order to save
power.
In the non-multiplexed displays this
input is permanently connected to
Vcc
Amit Nevase
3/12/17 147
 RBO Ripple Blanking Output

This output is normally at logic 1. But

it goes to logic 0 during the zero
blanking interval when RBI is forced
to a low level.
RBO is used for cascading purpose
and it is connected to RBI of the next
stage.

Amit Nevase
3/12/17 148
LT - Lamp Test

This pin can be used to check

whether all the segments of the
display are working properly or not.
If LT is forced low with RBO at logic 1
or open , then all the output
terminals will be forced to their
active state

Amit Nevase
3/12/17 149
 Circuit Diagram
5V

16
3 13 R Common
LT Vcc
a a
5 RBI
12
R a
4 BI / RBO b b
11 R f b
IC 7447
c c g
10 R
LSB 1 A0
d d
9 R e c
2 A1 e e dp
BCD R
6 15
Inputs A2 f f d dp
7 14 R
A3
MSB Gnd g g
8

Amit Nevase
3/12/17 150
Display Configuration LTS 542

Common

g f a b

a
f b
g

e c

d dp

e d c dp
Common
Amit Nevase
3/12/17 151
Display Configuration

Amit Nevase
3/12/17 152
Module III Combinational Logic Circuits

Introduction
(8 Marks)
Standard representation of canonical forms (SOP &
POS), Maxterm and Minterm , Conversion between
SOP and POS forms
K-map reduction techniques upto 4 variables (SOP &
POS form), Design of Half Adder, Full Adder, Half
Subtractor & Full Subtractor using k-Map
Code Converter using K-map: Gray to Binary, Binary
to Gray Code Converter (upto 4 bit)
IC 7447 as BCD to 7- Segment decoder driver
IC 7483 as Adder & Subtractor, 1 Digit
BCD Adder Amit Nevase
3/12/17 153
 N Bit Parallel Adder

The full adder is capable of adding two single

digit binary numbers along with a carry input.
But in practice we need to add binary
numbers which are much longer than one bit.
To add two n-bit binary numbers we need to
use the n-bit parallel adder.
It uses a number of full adders in cascade.
The carry output of the previous full adder is
connected to the carry input of the next full
adder..

Amit Nevase
3/12/17 154
 N Bit Parallel Adder

An 1 Bn 1 A2 B2 A1 B1 A0 B0

FA-(n-1) FA-2 FA-1 FA-0

C0 Cin

Sn 1 S2 S1 S0

Amit Nevase
3/12/17 155
 4 Bit Parallel Adder using full
adder

A3 B3 A2 B2 A1 B1 A0 B0

FA-3 FA-2 FA-1 FA-0

C0 Cin

S3 S2 S1 S0

Amit Nevase
3/12/17 156
 IC 7483 4 Bit Binary
Parallel Adder

A3 B3 A2 B2 A1 B1 A0 B0

FA-3 FA-2 FA-1 FA-0

C0 Cin

S3 S2 S1 S0

Amit Nevase
3/12/17 157
IC 7483 4 Bit Binary
Parallel Adder
A Binary number B Binary number
A3 A2 A1 A0 B 3 B 2 B1 B 0

IC 7483 Cin
C0
Carry
Carry
Input
Output

S3 S 2 S1 S 0
Sum Output
Amit Nevase
3/12/17 158
 Cascading of IC 7483
want to add two 8 bit binary numbers using 4 bit binary parallel adder IC
e have to cascade the two ICs in following way

Lower nibble of Lower nibble of

Higher nibble of Higher nibble of
A Binary numberB Binary number
A Binary number B Binary number
A7 A6 A5 A4 B7 B6 B5 B 4 A3 A2 A1 A0 B 3 B 2 B1 B 0

Cin C0
C0 IC 7483-II IC 7483-I Cin

Carry Carry
Output Input
S7 S6 S5 S4 S3 S 2 S1 S0

Sum Output
Amit Nevase
3/12/17 159
Design of 1 Digit BCD Adder
Block Diagram: A BCD no. B BCD no.

C0
IC 7483-I
S 3 S 2 S1 S 0 Cin

Logic
Circuit

Add 0110
Command

IC 7483-II
C0 Cin

Amit Nevase S3 S 2 S1 S0
3/12/17 160
Design of 1 Digit BCD Adder

As we know BCD addition rules, we

understand that the 4 bit BCD adder should
consists of following:
A 4 bit binary adder to add the given two
(4 bit numbers).
A combinational logic circuit to check if
sum is greater than 9 or carry 1.
One more 4 bit binary adder to add 0110
to the invalid BCD sum or if carry is 1

Amit Nevase
3/12/17 161
 Design of 1 Digit BCD Adder

Logic Table for design of Logic circuit:

Inputs Y Inputs Y

S3 S2 S1 S0 S3 S2 S1 S0

0 0 0 0 0 1 0 0 0 0

0 0 0 1 0 1 0 0 1 0

0 0 1 0 0 1 0 1 0 1

0 0 1 1 0 1 0 1 1 1
Sum is
0 1 0 0 0 1 1 0 0 1
invalid
BCD
0 1 0 1 0 1 1 0 1 1
Number
1 1 1 0 1 Y=1
0 1 1 0 0

0 1
3/12/17 1 1 0Amit Nevase 1 1 1 1 1 162
 Design of 1 Digit BCD Adder

K-map for Logic circuit:

S1S0 S 1S 0 S 1S 0 S 1S 0 S 1S 0
S3s2 0 0 1 1
0 0 1 1 1 3 0 2
S 3S 2 0 0 0 0 0
0 4 7
5 6
S 3S 2 0 0 0 0 0
1
1 1 1 1 Y S 3S 2 S 3S 1
S 3S 2 1 12 13 15 14
1
8 9 1 10
S 3S 2 1 0 0 11 1
0

S 3S 2 S 1S 3

Amit Nevase
3/12/17 163
Design of 1 Digit BCD Adder
A BCD no. B BCD no.

Combinational
Logic Circuit
C0
IC 7483-I
S 3 S 2 S1 S 0 Cin

Y' Y

C0
IC 7483-II
Not used S3 S 2 S1 S0 Cin
Carry output Amit Nevase
3/12/17 164
BCD Output Sum
4 Bit Binary Parallel Subtractor
using IC 7483

A Binary number B Binary number

A3 A2 A1 A0 B 3 B 2 B1 B 0
NOT gates for 1s
complement of B

Vcc 5V

C0
Carry IC 7483 Cin 1
Output S3 S 2 S1 S 0 It adds 1 to 1s
complement of B

Difference Output

Amit Nevase
3/12/17 165
IC 7483 as Parallel
Adder/Subtractor
B Binary number
B3 B2 B1 B0
A Binary number
M
A3 A2 A1 A0 Mode
Select

C0
Carry IC 7483
Cin
Output S3 S 2 S1 S 0

Sum or Difference Mode Select

Output M=0 Addition
M=1 Subtraction
Amit Nevase
3/12/17 166
Module III Combinational Logic Circuits

Introduction
(8 Marks)
Standard representation of canonical forms (SOP &
POS), Maxterm and Minterm , Conversion between
SOP and POS forms
K-map reduction techniques upto 4 variables (SOP &
POS form), Design of Half Adder, Full Adder, Half
Subtractor & Full Subtractor using k-Map
Code Converter using K-map: Gray to Binary, Binary
to Gray Code Converter (upto 4 bit)
IC 7447 as BCD to 7- Segment decoder driver
IC 7483 as Adder & Subtractor, 1 Digit BCD Adder
Block Schematic
3/12/17
Amit Nevase of ALU IC 74181,167 IC
IC 74181 Arithmetic Logic Unit

A very popular & widely used

combinational circuit is ALU which is
capable of performing arithmetic as well
as logical operation.
Arithmetic Operating Modes:
Addition
Subtraction
Shift Operation
Magnitude Comparison
12 other arithmetic operations

Amit Nevase
3/12/17 168
IC 74181

Logical Function Modes:

Exclusive OR
Comparator
AND, NAND, OR, NOR
10 other arithmetic operations

Amit Nevase
3/12/17 169
IC 74181 Pin Diagram

Amit Nevase
3/12/17 170
IC 74181 Function Table

Amit Nevase
3/12/17 171
IC 74381 4 Bit Arithmetic Logic
Unit

Features:
Low input loading minimizes drive
requirements
Performs six arithmetic and logic
functions
Selectable LOW (clear) and HIGH
(preset) functions
Carry generate and propagate outputs
for use with carry look ahead generator

Amit Nevase
3/12/17 172
IC 74381 Pin Configuration

Amit Nevase
3/12/17 173
IC 74381 Function Table

Amit Nevase
3/12/17 174
Module III Combinational Logic Circuits

Necessity, Applications and Realization of

following
(8 Marks)
Multiplexers (MUX): MUX Tree
Demultiplexers (DEMUX): DEMUX Tree, DEMUX as
Decoder
Study of IC 74151, IC 74155
Priority Encoder 8:3, Decimal to BCD Encoder
Tristate Logic, Unidirectional & Bidirectional buffer
ICs: IC 74244 and IC 74245

Amit Nevase
3/12/17 175
Multiplexers

Multiplexer is a circuit which has a

number of inputs but only one
output.
Multiplexer is a circuit which
transmits large number of
information signals over a single line.
Multiplexer is also known as Data
Selector or MUX.

Amit Nevase
3/12/17 176
Necessity of Multiplexers

In most of the electronic systems, the digital

data is available on more than one lines. It is
necessary to route this data over a single line.
Under such circumstances we require a circuit
which select one of the many inputs at a time.
This circuit is nothing but a multiplexer. Which
has many inputs, one output and some select
lines.
Multiplexer improves the reliability of the
digital system because it reduces the number
of external wired connections.

Amit Nevase
3/12/17 177
Advantages of Multiplexers

It reduces the number of wires.

So it reduces the circuit complexity
and cost.
We can implement many
combinational circuits using Mux.
It simplifies the logic design.
It does not need the k-map and
simplification.
Amit Nevase
3/12/17 178
Applications of Multiplexers

It is used as a data selector to select

one out of many data inputs.
It is used for simplification of logic
design.
It is used in data acquisition system.
In designing the combinational circuits.
In D to A converters.
To minimize the number of connections.

Amit Nevase
3/12/17 179
 Block Diagram of Multiplexer

D0 D0
D1 D1
Data D2 D2
Inputs D3 Y
D3
. n:1 .
. .
. Mux Output .
. . Output
. .
Dn-1 Dn-1

E
Enable Input
.... ....

Sm-1 S2 S1 s0 Sm-1 S2 S1 s0
Select Lines

Fig. General Block Diagram Fig. Equivalent Circuit

Amit Nevase
3/12/17 180
Relation between Data Input Lines
& Select Lines

In general multiplexer contains , n

data lines, one output line and m
select lines.

To select n inputs we need m select

lines such that 2m=n.

Amit Nevase
3/12/17 181
Types of Multiplexers

2:1 Multiplexer
4:1 Multiplexer
8:1 Multiplexer
16:1 Multiplexer
32:1 Multiplexer
64:1 Multiplexer
and so on

Amit Nevase
3/12/17 182
 2:1 Multiplexer

Data D0
Inputs 2:1 Y
D1 Block Diagram
Mux
Output
E
Enable Input
s
Select Lines
Enable i/p Select Output
(E) i/p (S) (Y)

0 X 0

Truth Table 1 0 D0

1 1 D1

Amit Nevase
3/12/17 183
Realization of 2:1 Mux using gates

S D1 D0
S

SD 0
Y

Output
SD1
E
Enable Input

Amit Nevase
3/12/17 184
 4:1 Multiplexer

Truth Table

Outp
Enable
D0 Select i/p ut
i/p
D1
Data E S1 S0 Y
Y
Inputs D 4:1
2
Mux 0 X X 0
D3 Output
D0
1 0 0
E
Enable Input 1 0 1 D1
S1 S0
1 1 0 D2
Select Lines
D3
1 1 1
Block Diagram
Amit Nevase
3/12/17 185
Realization of 4:1 Mux using gates

S1 S0

S 1S 0D 0
D0
S 1S 0 D1
D1 Y

Output
D2 S 1S 0D 2

E
D3 S 1S 0 D 3 Enable Input

Amit Nevase
3/12/17 186
 8:1 Multiplexer

Truth Table
D0
Out
D1 Enabl
Select i/p put
e i/p
D2
D3 E S2 S1 S0 Y
Data
Y
Inputs D4 8:1 0 X X X 0
Mux 1 0 0 0 D0
Output
D5
1 0 0 1 D1
D6
1 0 1 0 D2
D7
1 0 1 1 D3

E 1 1 0 0 D4
Enable Input 1 1 0 1 D5
1 1 1 0 D6
S2 S1 S0
Amit Nevase 1 1 1 1 D7
3/12/17 Select Lines 187
Block Diagram
 16:1 Multiplexer

D0
D1
D2
D3
D4
D5
Data D6 Y
Inputs D7 16:
D8 1
D9 Output
D10
Mux
D11
D12
D13
D14
D15

E
Block Diagram
Enable Input

S3 S2 S1 S0
Amit Nevase
3/12/17 Select Lines 188
16:1 Enabl Select Lines Outpu
Multiplexer e t
E S3 S2 S1 S0 Y
0 X X X X 0
1 0 0 0 0 D0
1 0 0 0 1 D1
1 0 0 1 0 D2
1 0 0 1 1 D3
1 0 1 0 0 D4
Truth
1 0 1 0 1 D5
Table
1 0 1 1 0 D6
1 0 1 1 1 D7
1 1 0 0 0 D8
1 1 0 0 1 D9
1 1 0 1 0 D10
1 1 0 1 1 D11

3/12/17
1Amit Nevase1 1 0 0 D189
12
Mux Tree

The multiplexers having more

number of inputs can be obtained by
cascading two or more multiplexers
with less number of inputs. This is
called as Multiplexer Tree.
For example, 32:1 mux can be
realized using two 16:1 mux and one
2:1 mux.

Amit Nevase
3/12/17 190
 8:1 Multiplexer using 4:1
Multiplexer
D0
D1
Y1
D2 4:1
Mux
D3

S2 ES S0 Y
Select 1
Lines S1
S0 Output
S1 S0
D4
D5
4:1
D6 Mux
Y2
D7

E
Amit Nevase
3/12/17 191
8:1 Multiplexer using 4:1
Multiplexer
D0
D1
Y1
D2 4:1
Mux
D3

D0
ES S0 2:1 Y
1 D1
S1 Mux
S0 Output
E
S1 S0
D4
D5 S2
4:1
D6 Mux
Y2
D7

E
Amit Nevase
3/12/17 192
 D0
16:1 Mux using
D1
D2
4:1
Mux
Y1 4:1 Mux
D3
S1 S0
S1
S0
D4 S1 S0
D5 4:1 Y2
D6 Mux
D7
D0
4:1 Y
D1
D2 Mux
D3 S S0 Output
D8 1

D9 4:1 Y3
D10 Mux
D11
S1 S0 S3 S2

D12 S1 S0
D13 4:1 Y4
D14 Mux
Amit Nevase
3/12/17 D15 193
Realization of Boolean expression
using Mux

We can implement any Boolean

expression using Multiplexers.
It reduces circuit complexity.
It does not require any simplification

Amit Nevase
3/12/17 194
 Example 1

mplement following Boolean expression using multiplexer

f ( A, B, C ) m(0, 3, 5, 6)

Since there are three variables,

therefore a multiplexer with three
select input is required i.e. 8:1
multiplexer is required
The 8:1 multiplexer is configured as
below to implement given Boolean
expression
Amit Nevase
3/12/17 195
Example 1
continue..
+Vcc f ( A, B, C ) m(0, 3, 5, 6)

D0
D1

D2
D3
Y
D4 8:1
Mux
Output
D5

D6
D7

E S2 S1 S0

A B C
Amit Nevase
3/12/17 196
 Example 2

mplement following Boolean expression using multiplexer

f ( A, B, C , D ) m(0, 2, 3, 6, 8, 9,12,14)

Since there are four variables,

therefore a multiplexer with four
select input is required i.e. 16:1
multiplexer is required
The 16:1 multiplexer is configured as
below to implement given Boolean
expression
Amit Nevase
3/12/17 197
Example 2
continue..
+Vcc f ( A, B, C , D) m(0, 2, 3, 6, 8, 9,12,14)

D0
D1
D2
D3
D4
D5
D6 Y
D7 16:
D8 1
D9 Output
D10
Mux
D11
D12
D13
D14
D15
S3 S2 S1 S0
E

A B C D
Amit Nevase
3/12/17 198
Module III Combinational Logic Circuits

Necessity, Applications and Realization of

following
(8 Marks)
Multiplexers (MUX): MUX Tree
Demultiplexers (DEMUX): DEMUX Tree,
DEMUX as Decoder
Study of IC 74151, IC 74155
Priority Encoder 8:3, Decimal to BCD Encoder
Tristate Logic, Unidirectional & Bidirectional buffer
ICs: IC 74244 and IC 74245

Amit Nevase
3/12/17 199
De-multiplexer

A de-multiplexer performs the

reverse operation of a multiplexer i.e.
it receives one input and distributes
it over several outputs.
At a time only one output line is
selected by the select lines and the
input is transmitted to the selected
output line.
It has only one input line, n number
of output lines and m number of
3/12/17
Amit Nevase
200
 Block Diagram of De-multiplexer

Y0 Y0
Y1 Y1
Y2 Y2
Data Y3 Y3
Input 1:n . Data .
. .
De-mux . Outputs Input . Output
. .
. .
Yn-1 Yn-1
E
Enable
Input .... ....

Sm-1 S2 S1 s0 Sm-1 S2 S1 s0
Select Lines

Fig. General Block Diagram Fig. Equivalent Circuit

Amit Nevase
3/12/17 201
Relation between Data Output Lines
& Select Lines

In general de-multiplexer contains , n

output lines, one input line and m
select lines.

To select n outputs we need m select

lines such that n=2m.

Amit Nevase
3/12/17 202
Types of De-multiplexers

1:2 De-multiplexer
1:4 De-multiplexer
1:8 De-multiplexer
1:16 De-multiplexer
1:32 De-multiplexer
1:64 De-multiplexer
and so on

Amit Nevase
3/12/17 203
1: 2 De-multiplexer

Din Y0
Data 1:2
Block Diagram
Input De-
mux Y1
E
Enable
Input S
Select Lines

Enable Select
Outputs
i/p i/p

E S Y0 Y1

0 X 0 0
Truth Table Din
1 0 0
Amit Nevase
3/12/17 1 1 0 D204
in
1:2 De-mux using basic gates

E Din S
S

Y0

Y1

Amit Nevase
3/12/17 205
 1: 4 De-multiplexer

Y0
Din 1:4 Y1
Data Block Diagram
Input De- Y2
mux Y3
E
Enable
Input Enab
S1 S0 Select i/p Outputs
le i/p
Select Lines
E S1 S0 Y0 Y1 Y2 Y3

0 X X 0 0 0 0

Din
1 0 0 0 0 0
Truth Table
1 0 1 0 Din 0 0

1 1 0 0 0 Din 0
Amit Nevase
3/12/17 1 1 1 0 0 0 Din
206
1:4 De-mux using basic gates
E Din S 1 S0
S1 S0

Y0

Y1

Y2

Y3

Amit Nevase
3/12/17 207
1: 8 De-multiplexer

Y0
Y1
Din Y2
Data
1:8 Y3
Input Y4
De-
mux Y5
Y6
E Y7
Enable
Input
S2 S1 S0
Select Lines

Block Diagram

Amit Nevase
3/12/17 208
1: 8 De-multiplexer
Truth Table

Ena
ble Select i/p Outputs
i/p
E S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 Din
1 0 0 1 0 0 0 0 0 0 Din 0

1 0 1 0 0 0 0 0 0 Din 0 0

1 0 1 1 0 0 0 0 Din 0 0 0

1 1 0 0 0 0 0 Din 0 0 0 0

1 1 0 1 0 0 Din 0 0 0 0 0

1 1 1 0 0 Din 0 0 0 0 0 0
Amit Nevase
1 3/12/171 1 1 Din 0 0 0 0 0 0 209
 1: 16 De-multiplexer

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Din
Data Y7
Input 1:16 Y8
De- Y9
mux Y10
Y11
Block Diagram Y12
Y13
Y14
E Y15
Enable
Input Amit Nevase
3/12/17 S3 S2 S1 S0 210
De-mux Tree

Similar to multiplexer we can

construct the de-multiplexer with
more number of lines using de-
multiplexer having less number of
lines. This is call as De-mux Tree.

Amit Nevase
3/12/17 211
1:4 De-mux using 1:2 De-mux

Data Y0 Y0
1:2
Input Din
De-
mux Y1 Y1
S1 E S0
Select
Lines
S0

S0
Y0 Y2
1:2
Din
De-
mux Y1 Y3
E

Amit Nevase
3/12/17 212
1:16 De-mux Y0
1:4 Y1
using 1:4 De-mux Din De- Y2
Y3
S muxS
1 0

S1 S0 Y4
1:4 Y5
Din Y6
Data Y0 De-
D Y7
Input in 1:4 Y1 mux
De- Y2
Y3
Smux
1 S0
Y8
1:4 Y9
Din De-
Y10
S3 S2 S mux S
1 0
Y11

S1 S0 Y12
Din 1:4 Y13
De- Y14 S1 S0
Amit Nevase
3/12/17 Y15 213
mux
Decoder

Decoder is a combinational circuit.

It converts n bit binary information at
its input into a maximum of 2n output
lines.
For example, if n=2 then we can
design upto 2:4 decoder

Amit Nevase
3/12/17 214
 2:4 Decoder

Y0
A
2:4 Y1
Inputs Block Diagram
Decod Y2
B
er Y3

E Enable Enab Data

Input Outputs
le i/p Inputs

E A B Y0 Y1 Y2 Y3

0 X X 0 0 0 0

1
1 0 0 0 0 0

1 0 1 0 1 0 0

Truth Table 1 1 0 0 0 1 0
Amit Nevase
3/12/17 1 1 1 0 0 0 215 1
De-multiplexer as Decoder

It is possible to operate a de-

multiplexer as a decoder.
Let us consider an example of 1:4 de-
mux can be used as 2:4 decoder

Amit Nevase
3/12/17 216
 1:4 De-multiplexer as 2:4 Decoder
Vcc

Y0 Din Y0
Din A S1
Data 1:4 Y1 1:4 Y1
Inputs
Input De- Y2 S0 De- Y2
B
mux Y3 mux Y3
E
Enable E Enable
Input
S1 S0 Input
Select Lines

1: 4 De-multiplexer 1: 4 De-multiplexer as 2:4 Decod

Amit Nevase
3/12/17 217
Realization of Boolean expression
using De-mux

We can implement any Boolean

expression using de-multiplexers.
It reduces circuit complexity.
It does not require any simplification

Amit Nevase
3/12/17 218
 Example 1

plement following Boolean expression using de-multiplexer

f ( A, B, C ) m(0, 3, 5, 6)

Since there are three variables,

therefore a de-multiplexer with three
select input is required i.e. 1:8 de-
multiplexer is required
The 1:8 de-multiplexer is configured
as below to implement given Boolean
expression
Amit Nevase
3/12/17 219
Example 1
continue..
f ( A, B, C ) m(0, 3, 5, 6)

+Vcc Y0
Y1
Data Y2
Din 1:8 Y3 Y
Input
De- Y4
mux Y5
Y6
E S2 S1 S0Y7
Enable
Input
A B C

Amit Nevase
3/12/17 220
 Example 2

plement following Boolean expression using de-multiplexer

f ( A, B, C , D ) m(0, 2, 3, 6, 8, 9,12,14)

Since there are four variables,

therefore a de-multiplexer with four
select input is required i.e. 1:16 de-
multiplexer is required
The 1:16 de-multiplexer is configured
as below to implement given Boolean
expression
Amit Nevase
3/12/17 221
Example 2
continue..
Y0
Y1
Y2
+Vcc Y3
Y4
Y5
Y6
Data 1:16 Y7 Y
Input De- Y8
Din
mux Y9
Y10
Y11
Y12
Y13
Y14
E S3 S2 S1 SY015
Enable
Input f ( A, B, C , D ) m(0, 2, 3, 6, 8, 9,12,14)
A B C D
Amit Nevase
3/12/17 222
Module III Combinational Logic Circuits

Necessity, Applications and Realization of

following
(8 Marks)
Multiplexers (MUX): MUX Tree
Demultiplexers (DEMUX): DEMUX Tree, DEMUX as
Decoder
Study of IC 74151, IC 74155
Priority Encoder 8:3, Decimal to BCD Encoder
Tristate Logic, Unidirectional & Bidirectional buffer
ICs: IC 74244 and IC 74245

Amit Nevase
3/12/17 223
Multiplexer ICs

IC Number Description Output

IC 74157 Quad 2:1 Mux Same as input

IC 74158 Quad 2:1 Mux Inverted Output

IC 74153 Dual 4:1 Mux Same as input

IC 74352 Dual 4:1 Mux Inverted Output

IC 74151 8:1 Mux Inverted Output

IC 74152 8:1 Mux Inverted Output

IC 74150 16:1 Mux Inverted Output

Amit Nevase
3/12/17 224
 IC 74151 General Description

This Data Selector/Multiplexer contains full on-chip

decoding to select one-of-eight data sources as a
result of a unique three-bit binary code at the Select
inputs.
Two complementary outputs provide both inverting
and non-inverting buffer operation.
A Strobe input is provided which, when at the high
level, disables all data inputs and forces the Y
Y
output to the low state and the output to the
high state.
The Select input buffers incorporate internal overlap
features to ensure that select input changes do not
cause invalid output transients.
Amit Nevase
3/12/17 225
IC 74151 - Features

Advanced oxide-isolated, ion-implanted

Schottky TTL process
Switching performance is guaranteed
over full temperature and VCC supply
range
Pin and functional compatible with LS
family counterpart
Improved output transient handling
capability
Amit Nevase
3/12/17 226
IC 74151 Pin Diagram VCC GND

D0
D1

D2 Y
Data D3
Inputs D4 8:1
Mux
D5 Y
D6
D7

E
Enable Input
Pin Diagram
S2 S1 S0
Select Lines
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3/12/17 227
Equivalent Diagram
De-multiplexer ICs

IC Number Description

IC 74138 1:8 De-multiplexer

IC 74139 Dual 1:4 De-multiplexer

IC 74154 1:16 De-multiplexer

IC 74155 Dual 1:4 De-multiplexer

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IC 74155 General Description

These monolithic TTL circuits feature

dual 1 line to 4 line de-multiplexers
with individual strobes and common
binary address inputs in a single 16
pin package.
The individual strobes permit
activating or inhibiting each of the 4-
bit sections as desired.

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IC 74155 - Features

Input clamping diodes simplify system

design.
Choice of outputs : Totem pole (LS155A) or
open collector (LS156).
Individual strobes simplify cascading for
decoding or de-multiplexing larger words.
Applications:
Dual 2 to 4 Line Decoder
Dual 1: 4 De-multiplexer
3 to 8 line Decoder
1 to 8 line de-multiplexer
Amit Nevase
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IC 7155 Pin Diagram

Amit Nevase
3/12/17 231
Module III Combinational Logic Circuits

Necessity, Applications and Realization of

following
(8 Marks)
Multiplexers (MUX): MUX Tree
Demultiplexers (DEMUX): DEMUX Tree, DEMUX as
Decoder
Study of IC 74151, IC 74155
Priority Encoder 8:3, Decimal to BCD
Encoder
Tristate Logic, Unidirectional & Bidirectional buffer
ICs: IC 74244 and IC 74245
Amit Nevase
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Encoder

Encoder is a combinational circuit which is

designed to perform the inverse operation
of decoder.
An encoder has n number of input lines
and m number of output lines.
An encoder produces an m bit binary code
corresponding to the digital input number.
The encoder accepts an n input digital
word and converts it into m bit another
digital word
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 Encoder

n m
. Encoder .
inputs . .
outputs
. .

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Types of Encoders

Priority Encoder

Decimal to BCD Encoder

Octal to BCD Encoder

Hexadecimal to Binary Encoder

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Priority Encoder

This is a special type of encoder.

Priorities are given to the input lines.

If two or more input lines are 1 at
the same time, then the input line
with highest priority will be
considered.

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 Priority Encoder 8:3

Highest Priority

D0
D1 Y2
D2 Priority 3
8 D3 Y1 outputs
Encoder
inputs
D4 8:3 Y0
D5
D6
D7

Lowest Priority

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3/12/17 237
 Priority Encoder 8:3
Truth Table:
Inputs Outputs

D7 D6 D5 D4 D3 D2 D1 D0 Y2 Y1 Y0

0 0 0 0 0 0 0 0 X X X

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 X 0 0 1

0 0 0 0 0 1 X X 0 1 0

0 0 0 0 1 X X X 0 1 1

0 0 0 1 X X X X 1 0 0

0 0 1 X X X X X 1 0 1

0 1 X X X X X X 1 1 0
Amit Nevase
13/12/17 X X X X X X X 1 1 238 1
Decimal to BCD Encoder

D1
D2 A
D3
D4 Decimal to B BCD
9 D5 BCD C outputs
inputs D6 Encoder
D7 D
D8
D9

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 Decimal to BCD Encoder
Truth Table:
Inputs Outputs
D9 D8 D7 D6 D5 D4 D3 D2 D1 D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 0 1 X 0 0 1 0
0 0 0 0 0 0 1 X X 0 0 1 1
0 0 0 0 0 1 X X X 0 1 0 0
0 0 0 0 1 X X X X 0 1 0 1
0 0 0 1 X X X X X 0 1 1 0
0 0 1 X X X X X X 0 1 1 1
0 1 X X X X X X X 1 0 0 0
1 X X X X X X X X 1 0 0 1
Amit Nevase
3/12/17 240
Module III Combinational Logic Circuits

Necessity, Applications and Realization of

following
(8 Marks)
Multiplexers (MUX): MUX Tree
Demultiplexers (DEMUX): DEMUX Tree, DEMUX as
Decoder
Study of IC 74151, IC 74155
Priority Encoder 8:3, Decimal to BCD Encoder
Tristate Logic, Unidirectional &
Bidirectional buffer ICs: IC 74244 and IC
74245
Amit Nevase
3/12/17 241
Tristate Logic

In digital electronics three-state,

tri-state, or 3-state logic allows an
output port to assume a high
impedance state in addition to the 0
and 1 logic levels, effectively
removing the output from the circuit.

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3/12/17 242
Digital Buffer

Sometimes in digital electronic

circuits we need to isolate logic gates
from each other or have them drive
or switch higher than normal loads,
such as relays, solenoids and lamps
without the need for inversion.
One type of single input logic gate
that allows us to do just that is called
the Digital Buffer.
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3/12/17 243
Digital Buffer

Symbol Truth Table

A Q

0 0

The Digital Buffer 1 1

Read as: A gives

Boolean Expression Q=A
Q

Amit Nevase
3/12/17 244
Digital Buffer
Unlike the single input, single output inverter or NOT
gate such as the TTL 7404 which inverts or
complements its input signal on the output, the
Buffer performs no inversion or decision making
capabilities (like logic gates with two or more inputs)
but instead produces an output which exactly
matches that of its input. In other words, a digital
buffer does nothing as its output state equals its
input state.
Then digital buffers can be regarded as Idempotent
gates applying Booles Idempotent Law because
when an input passes through this device its value is
not changed. So the digital buffer is a non-inverting
device and will therefore give us the Boolean
expression of:Q=A.
Amit Nevase
3/12/17 245
Tri-state Buffer
As well as the standard Digital Buffer seen above,
there is another type of digital buffer circuit whose
output can be electronically disconnected from its
output circuitry when required. This type of Buffer is
known as a 3-State Buffer or more commonly a Tri-
state Buffer.
A Tri-state Buffer can be thought of as an input
controlled switch with an output that can be
electronically turned ON or OFF by means of an
external Control or Enable (EN) signal input.
This control signal can be either a logic 0 or a logic
1 type signal resulting in the Tri-state Buffer being
in one state allowing its output to operate normally
producing the required output or in another state
were its output is blocked or disconnected.
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Tri-state Buffer - Equivalent

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3/12/17 247
Active High Tri-state Buffer

Symbol Truth Table

Enable IN OUT

0 0 Hi-Z

0 1 Hi-Z

1 0 0
Tri-state Buffer
1 1 1

Read as Output = Input if Enable is equal to 1

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3/12/17 248
Active Low Tri-state Buffer

Symbol Truth Table

Enable IN OUT

0 0 0

0 1 1

1 0 Hi-Z

Tri-state Buffer 1 1 Hi-Z

Read as Output = Input if Enable is NOT equal to 1

Amit Nevase
3/12/17 249
Tri-state Buffer Control

Amit Nevase
3/12/17 250
Buffer ICs
Sr. IC
Description
No. Number

1 IC 7407 TTL Hex non inverting Buffer

2 IC 7417 TTL Hex Buffer/Driver

3 IC 74244 TTL Octal Unidirectional Buffer

4 IC 74245 TTL Octal Bi-directional Buffer

5 IC 4050 CMOS Hex Non-inverting Buffer

6 IC 4503 CMOS Hex Tri-state Buffer

7 IC 40244 CMOS Octal Tri-state Buffer

Amit Nevase
3/12/17 251
IC 74244 - Features

ESD protection: HBM EIA/JESD22-A114-A

exceeds 2000 V MM EIA/JESD22-A115-A
exceeds 200 V CDM EIA/JESD22-C101 exceeds
1000 V
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than VCC
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from 40 to +85 and +125C

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3/12/17 252
IC 74244 Internal Diagram

Amit Nevase
3/12/17 253
Bi-directional Buffer

It is also possible to connect Tri-state Buffers back-

to-back to produce what is called a Bi-directional
Buffer circuit with one active-high buffer
connected in parallel but in reverse with one
active-low buffer.

Here, the enable control input acts more like a

directional control signal causing the data to be
both read from and transmitted to the same
data bus wire. In this type of application a tri-state
buffer with bi-directional switching capability such
as the TTL 74245 can be used.
Amit Nevase
3/12/17 254
IC 74245 - Description

These octal bus transceivers are designed for

asynchronous two-way communication between
data buses.
The control function implementation minimizes
external timing requirements.
The device allows data transmission from the A
Bus to the B Bus or from the B Bus to the A Bus
depending upon the logic level at the direction
control (DIR) input.
The enable input (G) can be used to disable the
device so that the buses are effectively isolated.

Amit Nevase
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IC 74245 - Features

Bi-Directional bus transceiver in a high-density

20-pin package
3-STATE outputs drive bus lines directly
PNP inputs reduce DC loading on bus lines
Hysteresis at bus inputs improve noise margins
Typical propagation delay times, port-to-port 8
ns
Typical enable/disable times 17 ns
IOL (sink current) - 24 mA
IOH (source current) - -15 mA

Amit Nevase
3/12/17 256
IC 74245 Internal Diagram

Amit Nevase
3/12/17 257
References

Digital Principles by
Malvino Leach
Modern Digital
Electronics by R.P. Jain
Digital Electronics,
Principles and
Integrated Circuits by
Anil K. Maini
Digital Techniques by A.
Anand Kumar
Amit Nevase
3/12/17 258
Online Tutorials

http://
nptel.ac.in/video.
php?subjectId=1171
06086
http://
www.electronics-tut
orials.ws/combinati
on/comb_1.html
http://
www.electronics-tut
Amit Nevase
3/12/17
orials.ws/combinati
259
 Thank
You
Amit Nevase
Amit Nevase
3/12/17 260