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ECEN474/704: (Analog) VLSI Circuit Design

Spring 2016

Lecture 14: Two Stage Miller OTA

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements & Agenda
HW5 (Preliminary Project Report) Due Apr. 18

Two Stage Miller OTA


OpAmp Characterization

2
Multi-Stage Amplifiers

Single-stage amplifiers typically have to trade-off gain and


swing range
Multi-stage amplifiers allow for higher gain without
sacrificing swing range
The major challenge with multi-stage amplifiers is achieving
adequate phase margin to insure stability in a feedback
configuration
3
Two Stage Miller OTA

g m 2 g m8 g m 2 g m8
DC Gain AVDC Av1 Av 2
g o 2 g o 4 g o8 g o 7 g o 2 g o 4 g o8 g o 7
AVDC Gm Rout
1
Rout
g o8 g o 7
g m8 g m 2
Gm g m8 Av1
go2 go4 4
Two-Stage Miller OTA Frequency Response

Stage 1 is a differential amplifier with


an active load
Stage 2 is a common-source amplifier
with a large miller capacitor
Using a Thevenin equivalent for Stage
1, we can use the common-source
equations from Lecture 8

5
Two-Stage Miller OTA Frequency Response

The amplifier should be designed to


yield one dominant pole, so we use the
dominant pole approximation equations
Neglecting Transistor Capacitances
1 1
p1
Rout1 1 g m8 Rout 2 CC Rout 2 CC C L Rout1g m8 Rout 2CC
Rout1 1 g m8 Rout 2 CC Rout 2 CC C L g m8
p2
Rout1Rout 2CC C L CL
where Rout1 rO 2 rO 4 and Rout 2 rO 7 rO8 6
Frequency Response No Compensation ELEN-474
VDD
M2 M2 M3

As
i01 2i01 i02 AVDC
s s
-v0
1 1
i01
i01 R1 C1 p1 p2
RL CL
vd -vd
M1 M1

VSS
Main equations

g m1 g m 3
AVDC
g1 g L
Phase Margin < 45 degrees
g AVDC
p1 1 (LHP)
C1
gL Phase
p2 (LHP)
CL
GBW AVDC * min p1 , p 2 (if dominant pole system, valid?)
u
1 1 u
Phase _ m arg in 180 tan tan p1 p2 u
GBW
p1 p2

Jose Silva-Martinez -7- Texas A&M University


TAMU-Elen-474 Frequency Response Miller Compensation (Ignoring z) Jose Silva-Martinez-08
VDD
M2 M2 M3
i01 i02
2i01
-v0
i01 i01 R1 C1 CM
RL CL
vd -vd
M1 M1

g m1 g m 3 VSS
AVDC
g1 g L Phase compensation Pole splitting techniques!!
g1
p1 (LHP)
g m3 After compensation
C1 CM Phase Margin > 45 degrees
gL AVDC
Bandwidth is reduced!!!
g m3
p2 (LHP)
C1 C L

GBW AVDC * p1
g m1
CM GBW

GBW
Phase _ m arg in 180 tan 1 tan 1 GBW p1 p1 p2
u p2
p1 p2
-8-
TAMU-Elen-474 z)Silva-Martinez-08
Frequency Response Miller Compensation (Considering Jose
VDD
M2 M2 M3
s
i01 2i01
i02
AVDC 1
z
-v0 As

i01 i01 R1 C1 CM 1 s 1 s
RL CL
vd -vd p1 p2
M1 M1
Parasitic (bad) RHP zero!!

g m3
VSS
ZERO (RHP)
g m1 g m 3 CM
AVDC
g1 g L
g1
p1 (LHP) After compensation
g m3 AVDC Phase Margin > 45 degrees
C1 CM Bandwidth is reduced!!!
gL
g m3
p2 (LHP)
C1 C L

GBW AVDC * p1
g m1
GBW
CM

GBW p1 p1
p2
Phase _ m arg in 180 tan 1 tan 1 GBW tan 1 GBW
ZER
p1 p2 ZERO
GBW p2 O

-9-
TAMU-Elen-474 z Impact on Frequency Response Jose Silva-Martinez-08

Parasitic (bad) RHP zero!! M2 M2 M3


VDD

Can be catastrophic if close or i01 2i01


i02
below wu! -v0
i01 i01 R1 C1 CM
g m3
ZERO
RL CL
vd -vd
CM M1 M1

VSS

1 u

1 u
u
Phase _ m arg in 180 tan tan tan 1

p1 ' p2 ' ZERO
After compensation
Phase Margin << 45 degrees
Phase is equivalent to having 3 poles
After compensation AVDC below unity gain frequency Unstable!
AVDC
Phase Margin > 45 degrees
Bandwidth is reduced!!!

GBW GBW

p1 p1 p2 p1 p1 p2
ZER ZERO
- 10 - u
GBW p2 O p2
TAMU-Elen-474 Jose Silva-Martinez-08

Adding a series resistance


s
VDD AVDC 1
As z
M2 M2 M3
i01 i02 1 s 1 s 1 s
2i01
p1 p 2 p3
-v0
RZ
i01 i01 1
p3 (Generally high frequency &
R1 C1 CM
RL CL can be ignored)
vd -vd RZ C1
M1 M1
1
IB2
z
IB1 M4 1
RZ CM
VB

VSS
g m3
Can design R Z to improve phase margin
Non - zero R Z will push RHP to a higher frequency (initially)
1
RZ pushes the RHP zero to infinity
g m3
1
RZ pushes zero from RHP to LFP
g m3
C L CM C1
RZ can cancel p2
g m 3C M

- 11 -
Two Stage Miller OTA Noise

Output - Referred Noise Current PSD

io2 8kT g m8
2 2
g m8
g m8 g m 7 2 g m 2 2 g m 4
f 3 o2
g g o4 o2
g g o4

Input - Referred Noise Voltage PSD

2

2
vi i 1 8kT g m8 g m 7
o 2 2 2 gm4
f f Gm 3 g m 2 g
2
g m 2 m8
g o 2 g o 4
12
ELEN-474

OPAMP Characterization

Main parameters to be measured:

DC gain (104-106) V/V)


Frequency Limitations
Bandwith (Few Hertz~1kHz)
Gain-Bandwidth product (1~100 Mhz)
Output resistance
Input Impedance
Signal Swing
Common-mode input range
Output swing
Stability
DC Offset
Slew-rate
CMRR For this section, see:
CMOS Analog design, Allen & Holberg
PSRR
2nd edition, HPR, 2002.
Jose Silva-Martinez -13- Texas A&M University
ELEN-474

OPAMP Characterization

DC gain (104-106) V/V) : How to measure/characterize it?

Very difficult to measure in open- Stabilize for DC


loop due to DC offsets.
Vi +
V0
+
V00 -
-

CC RC

For DC, the OPAMP operates in closed loop!!


For frequencies higher than 1/RCCC, the
OPAMP operates in open-loop with a
grounded load given by RC.

Jose Silva-Martinez -14- Texas A&M University


ELEN-474

OPAMP: DC Characterization
Vi How to measure/characterize it?
+
A(s) V0
- At DC vo A(s)
1
v i 1 A(s)
CC RC
If A(s)B(s) <<1 then the measured gain is
dominated by the OPAMP transfer function!
vo
vo

A(s) A(s)
v i 1 A(s)B(s)
AVDC vi
1 OPAMP
(open-loop)
sC C 1
B(s)
RC
1 1 sR C C C
sC C
Make sure 1
to set RCCC P1 A DC P1
C C
R C 1
such that GBW
R CCC
Jose Silva-Martinez -15- Texas A&M University
ELEN-474

OPAMP Characterization

DC Offset

Voffset
+
A(s) V0~Voffset
-

Jose Silva-Martinez -16- Texas A&M University


ELEN-474

OPAMP Characterization: GBW and stability

Vin
Vin
+
+ V0
V0 A(s)
A(s) -
-

AVDC
Vi
OPAMP
(open-loop)


P1
GBW
Enough phase margin

Jose Silva-Martinez -17- Texas A&M University


ELEN-474

OPAMP Characterization: GBW and stability


Vin
Vin
+
+ V0
V0 A(s)
A(s) -
-

AVDC
Vi
OPAMP
(open-loop)


P1

Not enough phase margin

Jose Silva-Martinez -18- Texas A&M University


ELEN-474

OPAMP Characterization: Slew-Rate (max speed)

Vin
+
A(s) V0
-

Max output level


VDD

Slew-Rate
d
max Vo( t ) t
dt

VSS
Min output level

Jose Silva-Martinez -19- Texas A&M University


ELEN-474

OPAMP Characterization: Output Swing


Vin
+
A(s) Low-Frequency Gain
-
Vo
Vmax A lowfreq
Vi

vi vo
Use a slow triangular input t Output
signal such that the raising swing
and falling edges are not
determined by slew rate Vmin
limitations
Small signal (~ 10 mV)

vo
vi

DC Offset

Jose Silva-Martinez -20- Texas A&M University


ELEN-474

OPAMP Characterization: Input and Output impedance


iin
iin
+ +
A(s)
Vin A(s) -
Vin
-

CC RC
Zin

R
RC and CC as large as possible!!

At Low frequencies:
C R C Zmeasured Zo (Why????)

At medium frequencies:
Zmeasured = Zo||RC

Be sure that the OPAMP (all internal


transistors) is properly biased during
characterization!!

Jose Silva-Martinez -21- Texas A&M University


Next Time
OpAmp Feedback & Stability
Common-Mode Feedback Techniques

22