Quanta Ze6-Rev1b PDF

1 2 3 4 5 6 7 8
01
ZE6 Block Diagram

A A
CK505
P2
INT_LVDS 10.1 "Panel
DDR SYSTEM MEMORY

Pineview Up to 1280*800 or 1366*768
Graphics Interfaces
P14
DDRIII-SODIMM 667 MT/s
P3
CPU
P4,5,6,7 CRT CRT
DMI
P14
N570 1.66G: AJSLBXEVT05
N475 1.83G: AJSLBX5UT08
N455 1.66G: AJSLBX9VT05
DMI(x2) Charger
P27
B B
+3VPCU
SATA 0 DMI +5VPCU
SATA - HDD SATA PCIE-4
P19 SIM Card +3V_S5
USB-5 3G/WiMAX
P20 USB-4
P20 +5V_S5
+3VSUS
+3V
PCI-Express(Port1~4) PCIE-2 +5V P28
Tigerpoint
USB-7 WLAN/WiMAX
P20 VCC_CORE
USB 2.0 (Port0~7) P29
USB-0,1,3
USB port*3 USB PCI-E
P17 SB +1.5VSUS
PCIE-1
USB-2 P8,9,10,11,12,13 LAN +SMDDR_VREF
CCD +0.75V_DDR_VTT
P14 RTL8105TAP18
RTC +1.5V P30
USB-6
C
Bluetooth module C
P15 PN : AJSLGXX0T14
BATTERY +1.05V
PCIE-3 P31
USB-5 Card Reader
3G P11
P20 RTS5209-GRP21 +1.5V
Intel High Definition Audio
USB-7
IHDA
Discharge
WLAN
P20 LPC VCCGFX
P32
LPC
Audio Codec Realtek ALC271X EC NPCE791L

P16 P22
D D
Touch Pad /B
K/B Con. SPI Flash Charger
Int. SPK Int. AMIC MIC Combo Con.
CONN CONN Jack Jack P15 P15 P22 P24
Quanta Computer Inc.

PROJECT : ZE6
Size Document Number Rev
Block Diagram 1B
Date: Friday, March 11, 2011 Sheet 1 of 35

1 2 3 4 5 6 7 8
5 4 3 2 1
CLK GEN (CLK) 02

VDD_CLK_3.3V VDD_CLK_1.5V +1.5V
+3V R212 2.2/J_6
1 2 L22 +3V
PBY160808T-301Y-N/2A/300ohm_6
L20
PBY160808T-301Y-N/2A/300ohm_6 C191 C146 C195 PM_STPPCI#_R R163 10K/J_4
D <20100819_FAE Poyueh> Add 2.2ohm resistor for noise suppress D
Place close to L8 .1U/10V_4 .1U/10V_4 4.7U/10V/8
C188 C157 C163 PM_STPCPU# R153 10K/J_4
Place close to L13
C185 .1U/10V_4 .1U/10V_4 .1U/10V_4
0.1uF near every power pin CLKREQ_MPC#_R R149 10K/J_4
4.7U/10V/8
CLKREQ_MNC#_R R202 10K/J_4

U9
0.1uF near every power pin
CLKREQ_LAN#_R R148 10K/J_4
5 23 1/19 : 439549_439549_CorbettPark_Schm_Rev0.5: If this pin is
VDD_REF_3.3 VDD_CORE_1.5 used as PCI_STOP#, it is required to provide a 10-k pull-up to
9 45 Vcc3_3. It is not recommended to connect this signal to the USB_48M R374 20K/F_4
VDD_IO can be ranging VDD_PCI_3.3 VDD_CORE_1.5 Tiger Point(NM10) as it may cause unexpected system behavior.
from 1.05V to 3.3V. 14 CFG input hardware strapping to allocate PLL assignment.
VDD_48M_3.3 LOW = Both CPU and SRC clock drive from PLL3
36 PM_STPPCI#_R R164 *0/J_4 HIGH = CPU clock drive from PLL1, SRC clock drive from PLL3.
+1.05V PCI_STOP# PM_STPPCI# [11] Contains 100k pull-down resistor.
30 42 PM_STPCPU#_R R157 *0/short_J_4 PM_STPCPU# [11] To SB
VDD_SRC_IO_1.05 CPU_STOP#
VDD_CLKIO_1.05V 35 53
VDD_SRC_IO_1.05 CPU_0 CLK_CPU_BCLK [4]
CPU_0# 52 CLK_CPU_BCLK# [4] To CPU (Core CLK) 166 MHz
R209 0_6 L21 48
PBY160808T-301Y-N/2A/300ohm_6 VDD_CPU_IO_1.05
CPU_1 50 CLK_MCH_BCLK [4]
CPU_1# 49 CLK_MCH_BCLK# [4] To CPU (Host CLK) 166 MHz
Place close to L18 1 NC
C178 C145 C162 C171 2 44
NC SRC_1/CPU_ITP CLK_PCIE_LANP [18]
C 13
NC SRC_1/CPU_ITP#
43 CLK_PCIE_LANN [18] To LAN (LAN) <EMI> C
4.7U/10V/8 .1U/10V_4 .1U/10V_4 .1U/10V_4 54 100 MHz
NC
41 USB_48M C190 *10P/50V_4
SRC_2 PE4CLK+ [20]
CG_XOUT 3 40 To Mini Card 2 (3G/Wimax) 100 MHz
XTAL_OUT SRC_2# PE4CLK- [20]
CG_XIN 4
C154 XTAL_IN ITP_EN C192 *10P/50V_4
0.1uF near every power pin SRC_3 38 PE2CLK+ [20]
33P/50V_4 CG_XIN 37 To Mini Card 1 (WLAN) 100 MHz
SRC_3# PE2CLK- [20]
SMBDT1 7
[3,20] SMBDT1 SDA
2
Y2 SMBCK1 8 34 FSB C189 *10P/50V_4

[3,20] SMBCK1 SCL SRC_4 CLK_PCIE_DMIP [4]
CL=20p SRC_4#
33 CLK_PCIE_DMIN [4] To CPU (DMI CLK) 100 MHz
14.318MHZ
C152 CLK_BSEL1_FSB R217 1K_4 FSB 15 32 FSC C176 *10P/50V_4
CLK_CARDREADER [21]
1
33P/50V_4 CG_XOUT USB48_1/FSB SRC_5

SRC_5# 31 CLK_CARDREADER# [21] To Card Reader 100 MHz
R218 33/J_4 USB_48M 17
[8] CLKUSB_48 USB48_2 33M_SEL C172 *10P/50V_4
28 CLK_PCIE_ICH [8]
R191 33/J_4 SRC_6
[11] 14M_ICH SRC_6#
27 CLK_PCIE_ICH# [8] To SB (DMI CLK) 100 MHz
<Layout note> FSC 6
CLK_BSEL2_FSC R190 10K_4 REF/FSC DREFCLK
Crystal place within 500mil of CK505 DOT96/SRC7 18 DREFCLK [4]
19 DREFCLK# To CPU (PLL CLK) 96 MHz
DOT96#/SRC7# DREFCLK# [4]
R205 22/J_4 ITP_EN 10
[10] PCLK_ICH PCIF/ITP_EN
R204 22/J_4 20
[22] LCLK_EC LCD_CLK DREFSSCLK [4]
Follow Silegro schematic R219 33/J_4 33M_SEL 11 21 To CPU (DPLSS CLK) 100 MHz
[20] PCLK_DEBUG 25MHz/PCI_2/SEL_33MHz LCD_CLK# DREFSSCLK# [4]
26 CLK_PCIE_SATA [9]
SATA
12
VSS_PCI SATA#
25 CLK_PCIE_SATA# [9] To SB (SATA CLK) 100 MHz
16 VSS_48M
22
B
24
39
VSS_LCD
VSS_SATA CLKREQ_A#
47
46
CLKREQ_LAN#_R
CLKREQ_MPC#_R
R141
R142
475/F_4
475/F_4
CLKREQ_LAN# [18]
Control SRC_1 Register B5b6 for CLKREQ_A#
0 = SRC1, 1=SRC2
Clock Gen I2C B
VSS_SRC CLKREQ_B# CLKREQ_WLAN# [20]

51 29 CLKREQ_MNC#_R R201 475/F_4 Control SRC_3 Register B5b4 for CLKREQ_B#
VSS_CPU CLKREQ_C# CLKREQ_CARD# [21] +3V
56 0 = SRC3, 1=SRC4
VSS_REF Control SRC_5 Register B5b3 for CLKREQ_C#
55 VR_PWRGD_CK410 [11]
CKPWRGD/PD# 0 = SRC5, 1=SRC6
57 Thermal Pad
<20100819> Add 475 ohm for current leakage R203
SLG8LV631V 2.2K_4
2
3 1 SMBCK1
[11,20] PCLK_SMB SMBCK1 [3,20]
2N7002K
+3V
FSC FSB Frequency Q16
R206 *10K/J_4 0 0 133MHz VR PWRGD

+3V
1 = Pin 43/44 as CPU_ITP 0 1 166MHz
R207 10K/J_4 ITP_EN 0 = Pin 43/44 as SRC_1 1 1 200MHz R186
2.2K_4
1 0 100MHz [23,26] VR_PWRGD_CK410#
2
pin 10 has internal pull down resistor.
R146 *10K_4
3 1 SMBDT1
no connect FSA to CPU, due to there is no FSA PIN for CPU. [11,20] PDAT_SMB SMBDT1 [3,20]
2
need to check check how to handle it in CPU CLK_BESEL0
2N7002K
A 0221 : follow vendor's suggestion, change from 10K to 4.7K +1.05V R215 *1K_4 1 3 R147 10K_4 Q15 A
+3V
R214 0_4 CLK_BSEL1_FSB
[4] CPU_BSEL1
2N7002K VR_PWRGD_CK410
VR_PWRGD_CK410 [11]
+3V R208 4.7K/J_4 R216 *0_4 Q9
C182
R197 *10K/J_4 33M_SEL 1 = Pin 11 as 33MHz
0= Pin 11 as 25MHz R188 *1K_4 .1U/10V_4
+1.05V
R187 0_4 CLK_BSEL2_FSC PROJECT : ZE6
[4] CPU_BSEL2
R189 *0_4 <20090721(B2A)> 1C
Change Q3,Q5,Q6 from BAM700200F6 to BAM70020002 (with ESD protection function) CLOCK GENERATOR
5 4 3 2 1
5 4 3 2 1
DDR_STD(DDR) +1.5VSUS
JDIM1B
JDIM1A M_A_DQ[63:0] [5]
[5] M_A_A[14:0] 75 VDD1 VSS16 44
M_A_A0 M_A_DQ7
M_A_A1
98
97
A0 DQ0 5
7 M_A_DQ6
2.48A 76
81
VDD2 VSS17 48
49
M_A_A2 A1 DQ1 M_A_DQ3 VDD3 VSS18
96 A2 DQ2 15 82 VDD4 VSS19 54
M_A_A3 95 17 M_A_DQ2 87 55
92 A4 DQ4 4 88 VDD6 VSS21 60
M_A_A5 91 6 M_A_DQ5 93 61
90 16 94 65
86 18 99 66
D 89 21 100 71 D
85 23 105 72
107 33 106 127
PC2100 DDR3 SDRAM SO-DIMM

M_A_A11 A10/AP DQ10 M_A_DQ11 VDD12 VSS27
84 A11 DQ11 35 111 VDD13 VSS28 128
M_A_A12 83 22 M_A_DQ12 112 133
M_A_A13 A12/BC# DQ12 M_A_DQ13 VDD14 VSS29
119 A13 DQ13 24 117 VDD15 VSS30 134
M_A_A14 80 34 M_A_DQ14 118 138
A14 DQ14 M_A_DQ15 VDD16 VSS31
78 A15 DQ15 36 123 VDD17 VSS32 139
M_A_DQ24
PC2100 DDR3 SDRAM SO-DIMM

DQ16 39 124 VDD18 VSS33 144
109 41 M_A_DQ25 145
[5] M_A_BS0 BA0 DQ17 VSS34
108 51 M_A_DQ27 199 150
[5] M_A_BS1 BA1 DQ18 +3V VDDSPD VSS35
79 53 M_A_DQ26 151
[5] M_A_BS2 BA2 DQ19 VSS36
114 40 M_A_DQ29 77 155
[5] M_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ28 122 156
[5] M_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ30 R119 *10K_4 125 161
[5] M_CLK0 CK0 DQ22 +3V NCTEST VSS39
103 52 M_A_DQ31 162
[5] M_CLK0# CK0# DQ23 VSS40
102 57 M_A_DQ18 198 167
[5] M_CLK1 CK1 DQ24 [4] PM_EXTTS#0 EVENT# VSS41
104 59 M_A_DQ23 30 168
[5] M_CLK1# CK1# DQ25 [5] DDR3_DRAMRST# RESET# VSS42
73 67 M_A_DQ22 172
[5] M_CKE0 CKE0 DQ26 VSS43
74 69 M_A_DQ19 173
[5] M_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ21 +SMDDR_VREF_DQ0 1 178
[5] M_A_CAS# CAS# DQ28 VREF_DQ VSS45
110 58 M_A_DQ17 +SMDDR_VREF_DIMM 126 179
[5] M_A_RAS# RAS# DQ29 VREF_CA VSS46
113 68 M_A_DQ16 184
[5] M_A_WE# WE# DQ30 VSS47
R130 10K_4 DIMM0_SA0 197 70 M_A_DQ20 185
R129 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ33 VSS48
201 129 2 189
SMBCK1 SA1 DQ32 M_A_DQ32 VSS1 VSS49
202 131 3 190
[2,20] SMBCK1 SMBDT1 SCL DQ33 M_A_DQ35 VSS2 VSS50
200 141 8 195
(204P)
[2,20] SMBDT1 SDA DQ34 M_A_DQ34 VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196 C
116 130 M_A_DQ37 13
[5] M_ODT0 ODT0 DQ36 VSS5
120 132 M_A_DQ36 14
[5] M_ODT1 ODT1 DQ37 VSS6
140 M_A_DQ38 19
[5] M_A_DM[7:0] DQ38 VSS7
M_A_DM0 11 142 M_A_DQ39 20
M_A_DM1 DM0 DQ39 M_A_DQ44 VSS8
28 DM1 DQ40 147 25 VSS9
M_A_DM3 46 149 M_A_DQ45 26 203 +0.75V_DDR_VTT
M_A_DM2 63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ42 31
VSS10
VSS11
VTT1
VTT2 204
M_A_DM4 136 159 M_A_DQ46 32
M_A_DM5 DM4 DQ43 M_A_DQ40 VSS12
153 146 37 205
M_A_DM6 DM5 DQ44 M_A_DQ41 VSS13 GND
170 148 38 206
M_A_DM7 DM6 DQ45 M_A_DQ47 VSS14 GND
187 158 43
DM7 DQ46 M_A_DQ43 VSS15
[5] M_A_DQS[7:0] 160
M_A_DQS0 DQ47 M_A_DQ48
12 DQS0 DQ48 163
M_A_DQS1 29 165 M_A_DQ49 DDR3-DIMM0_H=4_RVS
M_A_DQS3 DQS1 DQ49 M_A_DQ55 +1.5VSUS
47 DQS2 DQ50 175
M_A_DQS2 64 177 M_A_DQ54
M_A_DQS4 DQS3 DQ51 M_A_DQ53
137 DQS4 DQ52 164
M_A_DQS5 154 166 M_A_DQ52
M_A_DQS6 DQS5 DQ53 M_A_DQ51 R116
171 DQS6 DQ54 174
M_A_DQS7 188 176 M_A_DQ50 1K/F_4
[5] M_A_DQS#[7:0] DQS7 DQ55 +SMDDR_VREF_DIMM
M_A_DQS#0 10 181 M_A_DQ61
M_A_DQS#1 DQS#0 DQ56 M_A_DQ56
27 183
M_A_DQS#3 DQS#1 DQ57 M_A_DQ63 R115 *0_6 +SMDDR_VREF_DIMM
45 191 +SMDDR_VREF
62 193
135 DQS#4 DQ60 180
M_A_DQS#5 152 182 M_A_DQ60 R117 C109
B 169 DQS#6 DQ62 192 1K/F_4 470p/50V_4 B
M_A_DQS#7 186 194 M_A_DQ62
DQS#7 DQ63
DDR3-DIMM0_H=4_RVS +1.5VSUS
R138
Place these Caps near So-Dimm0. 1K/F_4
+SMDDR_VREF R140 *0_6 +SMDDR_VREF_DQ0
+1.5VSUS
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0 R139
C112 C126 C124 C114 C127 1K/F_4
4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.1u/10V_4 0.1u/10V_4
C115 + C108 C110 C107 C132 C131

220u/2V_7343
4.7U/6.3V_6 0.1u/10V_4 0.1u/10V_4 2.2u/6.3V_6
C116 C125 C113 C111 C128 2.2u/6.3V_6

4.7U/6.3V_6 4.7U/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
A A
+3V +0.75V_DDR_VTT
C118 C117 C122 C119

C129
2.2u/6.3V_6
C123
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
PROJECT : ZE6
1A
DDRIII SO-DIMM-0
5 4 3 2 1
5 4 3 2 1
PINEVIEW_M
04
U21C <Layout note>
Place within 750mil from CPU
U21D PINEVIEW_M
D12 REV = 1.1
XDP_RSVD_00
A7 M30 VGA_HSYNC_R R81 15/F_4
CRT_HSYNC [14]
XDP_RSVD_01 CRT_HSYNC
D6 M29 VGA_VSYNC_R R80 15/F_4
CRT_VSYNC [14] REV = 1.1
XDP_RSVD_02 CRT_VSYNC
C5 [14] INT_TXLCLKN U25 E7 H_SMI# [9]
XDP_RSVD_03 <Layout note> LVD_A_CLKM SMI_B
C7 [14] INT_TXLCLKP U26 H7 H_A20M# [9]
T34 XDP_RSVD_04 CRT_R LVD_A_CLKP A20M_B
VGA
C6 N31 Close to pin within 250mil R23 H6
XDP_RSVD_05 CRT_RED CRT_R [14] [14] INT_TXLOUTN0 LVD_A_DATAM_0 FERR_B H_FERR# [9]
D8 P30 CRT_G R24 F10 H_INTR [9]
XDP_RSVD_06 CRT_GREEN CRT_G [14] [14] INT_TXLOUTP0 LVD_A_DATAP_0 LINT00
ICH
B7 P29 CRT_B CRT_R CRT_G CRT_B N26 F11 H_NMI [9]
XDP_RSVD_07 CRT_BLUE CRT_B [14] [14] INT_TXLOUTN1 LVD_A_DATAM_1 LINT10
A9 N30 [14] INT_TXLOUTP1 N27 E5 H_IGNNE# [9]
R292 1K/F_4 D9 XDP_RSVD_08 CRT_IRTN LVD_A_DATAP_1 IGNNE_B
[14] INT_TXLOUTN2 R26 F8 H_STPCLK# [9]
XDP_RSVD_09 R94 R95 R92 LVD_A_DATAM_2 STPCLK_B
C8 [14] INT_TXLOUTP2 R27
T29 XDP_RSVD_10 150/F_4 150/F_4 150/F_4 LVD_A_DATAP_2
D B8 D
XDP_RSVD_11
C10 L31 CRT_SDA [14] G6 ICH_DPRSTP# [11,26]
XDP_RSVD_12 CRT_DDC_DATA R90 2.37K/F_4
LIBG R22 DPRSTP_B
D10 L30 CRT_SCL [14] G10 H_DPSLP# [11]
XDP_RSVD_13 CRT_DDC_CLK LVD_IBG DPSLP_B
LVDS
B11 J28 G8 H_INIT# [9]
XDP_RSVD_14 LVD_VBG INIT_B
B10 P28 VGA_IREF R96 665/F_4 <Layout note> N22 E11 T30
XDP_RSVD_15 DAC_IREF LVD_VREFH PRDY_B
B12 Close pin < 500mil Close to pin within 500mil N23 F15 H_PREQ#
T40 XDP_RSVD_16 LBKLT_EN LVD_VREFL PREQ_B
C11 Y30 DREFCLK [2] L27
XDP_RSVD_17 DPL_REFCLKINP LBKLT_EN
Y29 DREFCLK# [2] [14] INT_LVDS_PWM L26
DPL_REFCLKINN R89 *2.2K/J_4 LCTLA_CLK L23 LBKLT_CTL
AA30 DREFSSCLK [2] +3V E13 H_THRMTRIP#
DPL_REFSSCLKINP R88 *2.2K/J_4 LCTLB_DATAK25 LCTLA_CLK THERMTRIP_B
AA31 DREFSSCLK# [2]
DPL_REFSSCLKINN LCTLB_CLK R295 68_4 <20090511(A1A)_Checklist Rev0.7>
[14] LVDS_CLK K23 +1.05V
LDDC_CLK PROCHOT_B:68ohm5% pull-up to Vcc1_05
L11 [14] LVDS_DATA K24
RSVD LDDC_DATA (VCCP) at both CPU side and Intel MVP
[14] INT_LVDS_DIGON H26
LVDD_EN
C18 H_PROCHOT# [26]
PROCHOT_B H_PWRGD
W1 H_PWRGD [11]
R79 *0/short_4 CPUPWRGOOD
K29 PM_DPRSLPVR [11,26]
PM_EXTTS#_1/DPRSLPVR
J30 PM_EXTTS#0 [3]
PM_EXTTS#_0
L5 IMVP_PWRGD [11,23,26]
PWROK
AA3 PLTRST# [11,18,20,21,22,23] A13 H_GTLREF
RSTINB GTLREF
H27
MISC
VSS
W8 CLK_MCH_BCLK# [2]
HPL_CLKINN <20090610(A1A)_Sighting Report Rev002_Number:3359187>
W9 CLK_MCH_BCLK [2]
HPL_CLKINP
Avoid a glitch during system power up L6
RSVD
AA7 E17
RSVD_TP T8 RSVD
AA6 G11
R5
RSVD_TP
RSVD_TP
LCD Panel Backlight T39
T13
E15
BPM_1B_0
BPM_1B_1 BCLKN
H10 CLK_CPU_BCLK# [2]
R6 G13 J10 CLK_CPU_BCLK [2]
RSVD_TP +3V T10 BPM_1B_2 BCLKP
F13
C82 0.1u/10V_4 BPM_1B_3 CPU_BSEL0
CPU
AA21 K5
RSVD_TP T33 BSEL_0 CPU_BSEL1
W21 B18 H5 CPU_BSEL1 [2]
RSVD_TP U5 T41 BPM_2_0#/RSVD BSEL_1 CPU_BSEL2
T21 B20 K6 CPU_BSEL2 [2]
5
RSVD_TP 3 OF 6 T36 BPM_2_1#/RSVD BSEL_2
V21 C20
RSVD_TP IMVP_PWRGD TC7SH08FU T37 BPM_2_2#/RSVD
2 B21 H30 VID0 [26]
BPM_2_3#/RSVD VID_0
4 INT_LVDS_BLON [14] H29 VID1 [26]
C
Pineview-M 1.66G LBKLT_EN VID_1 C
1 H28 VID2 [26]
VID_2
G30 VID3 [26]
T9 VID_3
G5 G29
3
RSVD VID_4 VID4 [26]
R93 XDP_TDI D14 F29
TDI VID_5 VID5 [26]
T35 D13 E29
TDO VID_6 VID6 [26]
100K_4 XDP_TCK B14
XDP_TMS TCK
C14 L7
PINEVIEW_M XDP_TRST# TMS RSVD CLK GEN no FSA pin for CPU_BSEL0,
C16 D20
U21A R99 *0_4 TRST_B RSVD so just pull high to fix it.
H13
RSVD
D18
REV = 1.1 H_THERMDA RSVD
D30
H_THERMDC THRMDA_1
[8] DMI_TXP0 F3 G2 DMI_RXP0 [8] E30 K9
DMI_RXP_0 DMI_TXP_0 THRMDC_1 RSVD_TP
[8] DMI_TXN0 F2 G1 D19
DMI
DMI_RXN_0 DMI_TXN_0 DMI_RXN0 [8] RSVD_TP

[8] DMI_TXP1 H4 H3 DMI_RXP1 [8] K7 H_EXBGREF
DMI_RXP_1 DMI_TXP_1 EXTBGREF
[8] DMI_TXN1 G3 J2 DMI_RXN1 [8]
DMI_RXN_1 DMI_TXN_1
+1.05V
<Layout note>
Place within 500mil from CPU pin
C30 CPU_BSEL0 R65 470/J_4
EXP_COMP R91 49.9/F_4 <Layout note> RSVD_C30 4 OF 6 CPU_BSEL1 R66 470/J_4
[2] CLK_PCIE_DMIN N7 L10 D31
EXP_CLKINN EXP_RCOMPO PLACE TCK/TDI/TMS TERMINATION NEAR CPU RSVD_D31 CPU_BSEL2 R64 470/J_4
[2] CLK_PCIE_DMIP N6 L9
EXP_CLKINP EXP_ICOMPI EXP_RBIAS R310 750/F_4
L8
EXP_RBIAS Pineview-M 1.66G
R10
RSVD <Layout note>
R9 N11
N10
RSVD
RSVD
RSVD_TP
RSVD_TP
P11 Place within 500mil from CPU pin XDP PU +1.05V <Layout note> <Layout note>
N9 Place within 500mil from CPU pin and 5mil spacing Place within 500mil from CPU pin
RSVD
+1.05V +1.05V
K2 K3 XDP_TMS R63 51/J_4
RSVD_K2 RSVD_K3 R74 2.2K/J_4 LVDS_CLK Max 500mil Near CPU pin
J1 L2 +3V
RSVD_J1 RSVD_L2 XDP_TDI R62 51/J_4
M4 M2
RSVD_M4 RSVD_M2 R69 2.2K/J_4 LVDS_DATA R51 R280
L3 N2
RSVD_L3 1 OF 6 RSVD_N2 H_PREQ# R294 51/J_4 976/F_4 1K/F_4
B +3V <EMI> 1D: No Stuff C8007 (CRB v1.0) B
XDP_TCK R293 51/J_4 C52 C61
Pineview-M 1.66G H_EXBGREF H_GTLREF
PM_EXTTS#0 R77 10K_4 XDP_TRST# R61 51/J_4 *220P/50V_4 *220P/50V_4
XDP_BPM#5 : Length<200mil R55 C36 R281 C251 C257

3.32K/F_4 1U/6.3V_4 2K/F_4 1U/6.3V_4 *220P/50V_4
CPU FAN CTRL(THM) CPU Thermal monitor(THM) +3V

+1.05V
125 Degree Protection(CPU)
3
8/11 B-test : for EMI +3V
Q2
2N7002K
R76 R52 R75 *0/short_4 C54 0.1u/10V_4 IMVP_PWRGD 2
<20090721(B2A)>
FAN_PWM_CN FAN_SIG 10K_4 *10K_4 U4 Change Q7 from BAM700200F6
H_THERMDA to BAM70020002 (with ESD
[22] 2ND_MBCLK 8 1 protection function)
1
C130 C121 SCLK VCC
*220p/50V_6 *220p/50V_6 +3V [22] 2ND_MBDATA 7 2 C40
SDA DXP +1.05V
[11,22] THERM_ALERT# R59 *0_4 THERM_ALERT#_R 6 3 2200p/50V_4 R47
+3V +5V ALERT# DXN 1K_4
R126 FAN_ON# 4 5 H_THERMDC R60
OVERT# GND
2
R133 R137 10K_4 <Layout Note> CPU 56_4
+3V IC CTRL(8P) EMC1412-1-ACZL-TR Routing 10:10 mils and Q1
FAN_SIG away from noise source H_THRMTRIP# 1 3
A FAN_SIG [22] SYS_SHDN# [25,26,30] A
10K_4 10K_4 ALERT#:pull up at SB side SMSC ADDRESS: 98H with ground gard MMBT3904
+5V
R128 CN16 SMSC : AL001412003
Q8 R67 *0_4
PM_THRMTRIP# [9]
2
10K_4 4 6
MMBT3904 3 5 Tigerpoint
FAN_PWM_E FAN_PWM_CN 2
1 3
1
FAN
3
FAN_ON# R124 10K_4 FAN_PWM_B 2 Q6

MMBT3904 PROJECT : ZE6
1
CPUFAN# Size Document Number Rev

[22] CPUFAN# 1B
Pineview DMI/Display
5 4 3 2 1
5 4 3 2 1
PINEVIEW_M
05
U21B REV = 1.1 M_A_DQ[63..0] [3]
[3] M_A_A[14..0]
M_A_A0 AH19 AD3 M_A_DQS0
M_A_A1 DDR_A_MA_0 DDR_A_DQS_0 M_A_DQS#0
AJ18 AD2 M_A_DM[7..0] [3]
M_A_A2 DDR_A_MA_1 DDR_A_DQSB_0 M_A_DM0
AK18 AD4
M_A_A3 DDR_A_MA_2 DDR_A_DM_0
AK16 DDR_A_MA_3
M_A_A4 AJ14 AC4 M_A_DQ0
DDR_A_MA_4 DDR_A_DQ_0 M_A_DQS[7..0] [3]
M_A_A5 AH14 AC1 M_A_DQ1
M_A_A6 DDR_A_MA_5 DDR_A_DQ_1 M_A_DQ2 M_A_DQS#[7..0] [3]
AK14 AF4
M_A_A7 DDR_A_MA_6 DDR_A_DQ_2 M_A_DQ3
D
AJ12 DDR_A_MA_7 DDR_A_DQ_3 AG2 D
M_A_A8 AH13 AB2 M_A_DQ4
AK12 AB3
AK20 AE2
AH12 AE3
M_A_A12 DDR_A_MA_11 DDR_A_DQ_7
AJ11 DDR_A_MA_12
M_A_A13 AJ24 AB8 M_A_DQS1
M_A_A14 DDR_A_MA_13 DDR_A_DQS_1 M_A_DQS#1
AJ10 AD7
DDR_A_MA_14 DDR_A_DQSB_1 M_A_DM1
DDR_A_DM_1 AA9
M_A_WE# AK22 AB6 M_A_DQ8
[3] M_A_WE# DDR_A_WEB DDR_A_DQ_8
M_A_CAS# AJ22 AB7 M_A_DQ9
[3] M_A_CAS# DDR_A_CASB DDR_A_DQ_9
M_A_RAS# AK21 AE5 M_A_DQ10
[3] M_A_RAS# DDR_A_RASB DDR_A_DQ_10
AG5 M_A_DQ11
M_A_BS0 DDR_A_DQ_11 M_A_DQ12
[3] M_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
M_A_BS1 AH20 AB5 M_A_DQ13
[3] M_A_BS1 DDR_A_BS_1 DDR_A_DQ_13
M_A_BS2 AK11 AB9 M_A_DQ14
[3] M_A_BS2 DDR_A_BS_2 DDR_A_DQ_14
AD6 M_A_DQ15
DDR_A_DQ_15
AD8 M_A_DQS2
M_CS#0 DDR_A_DQS_2 M_A_DQS#2
[3] M_CS#0 AH22 AD10
M_CS#1 DDR_A_CSB_0 DDR_A_DQSB_2 M_A_DM2
[3] M_CS#1 AK25 DDR_A_CSB_1 DDR_A_DM_2 AE8
AJ21 DDR_A_CSB_2
AJ25 AG8 M_A_DQ16
DDR_A_CSB_3 DDR_A_DQ_16 M_A_DQ17
AG7
M_CKE0 DDR_A_DQ_17 M_A_DQ18
[3] M_CKE0 AH10 AF10
M_CKE1 DDR_A_CKE_0 DDR_A_DQ_18 M_A_DQ19
[3] M_CKE1 AH9 DDR_A_CKE_1 DDR_A_DQ_19 AG11
AK10 AF7 M_A_DQ20
DDR_A_CKE_2 DDR_A_DQ_20 M_A_DQ21
AJ8 AF8
DDR_A_CKE_3 DDR_A_DQ_21 M_A_DQ22
AD11
M_ODT0 DDR_A_DQ_22 M_A_DQ23
C
[3] M_ODT0 AK24 DDR_A_ODT_0 DDR_A_DQ_23 AE10 C
M_ODT1 AH26
[3] M_ODT1 DDR_A_ODT_1
AH24 AK5 M_A_DQS3
DDR_A_ODT_2 DDR_A_DQS_3 M_A_DQS#3
AK27 AK3
DDR_A_ODT_3 DDR_A_DQSB_3 M_A_DM3
AJ3
DDR_A_DM_3
AH1 M_A_DQ24
M_CLK0 DDR_A_DQ_24 M_A_DQ25
[3] M_CLK0 AG15 AJ2
M_CLK0# DDR_A_CK_0 DDR_A_DQ_25 M_A_DQ26
[3] M_CLK0# AF15 AK6
M_CLK1 DDR_A_CKB_0 DDR_A_DQ_26 M_A_DQ27
[3] M_CLK1 AD13 AJ7
M_CLK1# DDR_A_CK_1 DDR_A_DQ_27 M_A_DQ28
[3] M_CLK1# AC13 DDR_A_CKB_1 DDR_A_DQ_28 AF3
AH2 M_A_DQ29
+3V_S5 DDR_A_DQ_29 M_A_DQ30
DDR3 PWROK DDR_A_DQ_30
AL5
M_A_DQ31
AC15 DDR_A_CK_3 DDR_A_DQ_31 AJ6
AD15 DDR_A_CKB_3
AF13 AG22 M_A_DQS4
DDR_A_CK_4 DDR_A_DQS_4
5
[22,23,27,29] SUSON 1 AG13 AG21 M_A_DQS#4

DDR_A_CKB_4 DDR_A_DQSB_4 M_A_DM4
4 AD19
DDR_A_DM_4
[22,23,27] HWPG_1.5V 2
U7 AE19 M_A_DQ32
3
TC7SH08FU R121 DDR_A_DQ_32 M_A_DQ33

AD17 AG19
RSVD_AD17 DDR_A_DQ_33 M_A_DQ34
AC17 AF22
12.1K/F_4 +1.5VSUS RSVD_AC17 DDR_A_DQ_34 M_A_DQ35
AB15 AD22
RSVD_AB15 DDR_A_DQ_35 M_A_DQ36
AB17 AG17
DDRAM_PWROK RSVD_AB17 DDR_A_DQ_36 M_A_DQ37
AF19
DDR_A_DQ_37 M_A_DQ38
DDR_A_DQ_38 AE21
R350 AD21 M_A_DQ39
R120 DDR_A_DQ_39
*10K_4 AE26 M_A_DQS5
10K_4 DDRAM_PWROK DDR_A_DQS_5 M_A_DQS#5
AB4 AG27
B VSS DDR_A_DQSB_5 M_A_DM5
B
[3] DDR3_DRAMRST# AK8 AJ27
RSVD DDR_A_DM_5
AE24 M_A_DQ40
DDR_A_DQ_41 AG25
AB11 AD25 M_A_DQ42
C294 0.1U/10V_4 RSVD_TP DDR_A_DQ_42 M_A_DQ43
AB13 AD24
<Layout note> RSVD_TP DDR_A_DQ_43 M_A_DQ44
DDR_A_DQ_44 AC22
Close to pin DDR_VREF AL28 AG24 M_A_DQ45
R348 80.6/F_4 SM_RCOMP DDR_VREF DDR_A_DQ_45 M_A_DQ46
AK28 AD27
R349 80.6/F_4 SM_RCOMP# DDR_RPD DDR_A_DQ_46 M_A_DQ47
+1.5VSUS AJ26 AE27
DDR_RPU DDR_A_DQ_47
C295 0.01U/25V_4 AK29 AE30 M_A_DQS6
RSVD DDR_A_DQS_6 M_A_DQS#6
DDR_A_DQSB_6 AF29
AF30 M_A_DM6
DDR_A_DM_6
DDR_A
AG31 M_A_DQ48
AG30
+1.5VSUS DDR_A_DQ_49 M_A_DQ50
AD30
AD29
DDR_A_DQ_52 AJ30
<Layout note> AJ29 M_A_DQ53
Close to DDR_VREF pin R351 DDR_A_DQ_53 M_A_DQ54
AE29
1K/F_4 AD28
DDR_A_DQ_55
AB27 M_A_DQS7
R352 *0_4 DDR_VREF DDR_A_DQS_7 M_A_DQS#7
+SMDDR_VREF AA27
DDR_A_DQSB_7 M_A_DM7
DDR_A_DM_7 AB26
R353 C296 AA24 M_A_DQ56

A 1K/F_4 AB25 A
<EMI> C297 0.1u/16V_6 DDR_A_DQ_57 M_A_DQ58
W24
W22
*1000p/50V_4 DDR_A_DQ_59 M_A_DQ60
DDR_A_DQ_60 AB24
AB23 M_A_DQ61
AA23
2 OF 6 DDR_A_DQ_62 M_A_DQ63
W27
DG 2.1 : It is strongly recommended that the SODIMM VREF motherboard traces, going from
their VREF resistor dividers to their specified SODIMM VREF pins, be ground referenced
DDR_A_DQ_63 Quanta Computer Inc.
on the motherboard where ever possible to help minimize risks of any possible noise Pineview-M 1.66G
being coupled onto VREF. If they can't be referenced to ground we recommend placing PROJECT : ZE6
a site for a 0603 capacitor near the VREF divider. These 0603 capacitor sites must be Size Document Number Rev
connected on one end to the non ground reference plane the VREF trace is referenced 1B
to and the other end must be connected to ground. Pineview DDR
5 4 3 2 1
1 2 3 4 5 6 7 8
VCCGFX U21E VCORE

06
PINEVIEW_M
C84 2.2U/6.3V_6 A23
VCC
A25
C85 1U/6.3V_4 REV = 1.1 VCC
A27
VCC C69 1U/6.3V_4
3.5A VCC
B23
C74 1U/6.3V_4 T13 B24
VCCGFX VCC C58 1U/6.3V_4
T14
VCCGFX 1.38A VCC
B25
C72 1U/6.3V_4 T16 B26
GFX/MCH
T18 B27
C77 1U/6.3V_4 VCCGFX VCC
A T19 C24 A
V13 C26
V19 D23
VCCGFX VCC C32 22u/6.3V_8
W14 D24
W16 D26
W18 D28
CPU
W19 E22
E24
VCC
E27
VCC
F21
VCC
F22
VCC
F25
VCC
G19
+1.5VSUS VCC
G21
R111 *0/short_8 VCC
G24
VCC
H17
VCC
H19
VCC
H22
C101 2.2U/6.3V_6 VCC
H24
VCC
J17
C100 1U/6.3V_4 VCC
AK13 J19
VCCSM VCC
AK19 J21
C99 1U/6.3V_4 VCCSM VCC
AK9 J22
VCCSM VCC
AL11 K15
AL16 K17
VCCSM VCC
AL21 K21
AL25 L14
VCCSM VCC
B L16 B
<Layout note> VCC
L19
Close to pin VCC
2.27A VCC
L21
POWER
N14
VCC
N16
R112 *0/short_6 VCC1.5_VCCCK_DDR VCC
+1.5VSUS AK7 N19
VCCCK_DDR VCC
DDR
AL7 N21
C102 VCCCK_DDR VCC
C106
22U/6.3V_8 1U/6.3V_4 U10
+1.05V VCCA_DDR
U5
VCCA_DDR
U6
VCCA_DDR VCORE
U7
VCCA_DDR
U8
VCCA_DDR
U9
VCCA_DDR 1.32A
V2
C278 22u/6.3V_8 VCCA_DDR R56
V3
VCCA_DDR
V4 100/F_4
C81 4.7U/6.3V_6 VCCA_DDR
W10
VCCA_DDR
W11
C76 1U/6.3V_4 VCCA_DDR
C29 VCC_SENSE [26]
VCCSENSE
AA10 B29 VSS_SENSE [26]
VCCACK_DDR VSSSENSE VCC1.5_VCCA R322 *0/short_6
AA11 Y2 +1.5V
VCCACK_DDR VCCA C280 0.01U/25V_4
0.08A
<Layout note> R57
Close to pin 100/F_4
D4 +1.05V
<Layout note> VCC C255 *0.1u/10V_4 <20090526(A1A)_EDS Rev0.7>
C C
Close to pin AA19 B4 D4 pin is VCCP, not VCC
VCCP VCCP_VCCP R291 *0/short_4
B3 +1.05V
<Layout note> VCCP
VCCA_DDR and VCCACK_DDR rails can be C80 *0.1u/10V_4 AA19
on the same source but make sure the VCCD_AB_DPL
plane shapes are split near Pineview-M C94 *0.1u/10V_4
to avoid noise coupling
V11 0.06A
EXP\CRT\PLL
VCCD_HMPLL
VCC1.8_LCCALVD R100 0.1uH/300mA_6
+1.8V
+1.8V AC31
C91 1U/6.3V_4 VCCSFR_AB_DPL LVDS V30
C93 1U/6.3V_4 VCCALVD C87 C92
W31
VCCDLVD 22U/6.3V_8 1u/6.3V_4
0.154A
R98
VCC1.8_VCCACRTDAC T30
+1.8V VCCACRTDAC
0.2A/600ohm_6 +3V
C79 C323 0.006A 0.33A 0.48A
1u/6.3V_4 *22U/6.3V_8 C75 1U/6.3V_4 T31 T1 VCCP_DMI R315 *0/short_6
DMI
VCC_GIO VCCA_DMI +1.05V

J31 T2 C273 1U/6.3V_4
+1.05V VCCRING_EAST VCCA_DMI
C3 T3 C272 1U/6.3V_4
+1.05V VCCRING_WEST VCCA_DMI
C253 1U/6.3V_4 B2
C254 1U/6.3V_4 VCCRING_WEST VCCP_VCCAPLL_DMI R313 *0_4
C2
VCCRING_WEST 0.104A RSVD
P2 +1.05V
+1.05V A21 AA1VCC1.8_DMIHMPLL R326 *0/short_4
+1.8V
VCC_LGI_VID VCCSFR_DMIHMPLL
D E2 C267 D
VCCP +1.05V
C256 C284 *1u/6.3V_4
*1u/6.3V_4 1u/6.3V_4
5 OF 6
Pineview-M 1.66G
PROJECT : ZE6
1B
Pineview Power
1 2 3 4 5 6 7 8
1
U21F PINEVIEW_M
07
A11 REV = 1.1 F24
VSS VSS
A16 F28
VSS VSS
A19 F4
VSS VSS
A29 G15
RSVD_NCTF VSS
A3 G17
RSVD_NCTF VSS
A30 G22
RSVD_NCTF VSS
A4 G27
RSVD_NCTF VSS
AA13 G31
VSS VSS
AA14 H11
VSS VSS
AA16 H15
VSS VSS
AA18 H2
VSS VSS
AA2 H21
VSS VSS
AA22 H25
VSS VSS
AA25 H8
VSS VSS
AA26 J11
VSS VSS
AA29 J13
VSS VSS
AA8 J15
VSS VSS
AB19 J4
VSS VSS
AB21 K11
VSS VSS
AB28 K13
VSS VSS
AB29 K19
VSS VSS
AB30 K26
VSS VSS
GND
AC10 K27
VSS VSS
AC11 K28
VSS VSS
AC19 K30
VSS VSS
AC2 K4
VSS VSS
AC21 K8
VSS VSS
AC28 L1
VSS VSS
AC30 L13
VSS VSS
AD26 L18
VSS VSS
AD5 L22
VSS VSS
AE1 L24
VSS VSS
AE11 L25
VSS VSS
AE13 L29
VSS VSS
AE15 M28
VSS VSS
AE17 M3
VSS VSS
AE22 N1
VSS VSS
AE31 N13
VSS VSS
AF11 N18
VSS VSS
AF17 N24
VSS VSS
AF21 N25
VSS VSS
AF24 N28
VSS VSS
AF28 N4
VSS VSS
AG10 N5
VSS VSS
AG3 N8
VSS VSS
AH18 P13
VSS VSS
AH23 P14
VSS VSS
AH28 P16
VSS VSS
AH4 P18
VSS VSS
AH6 P19
A VSS VSS A
AH8 P21
VSS VSS
AJ1 P3
RSVD_NCTF VSS
AJ16 P4
VSS VSS
AJ31 R25
VSS VSS
AK1 R7
RSVD_NCTF VSS
AK2 R8
RSVD_NCTF VSS
AK23 T11
VSS VSS
AK30 U22
RSVD_NCTF VSS
AK31 U23
RSVD_NCTF VSS
AL13 U24
VSS VSS
AL19 U27
VSS VSS
AL2 V14
RSVD_NCTF VSS
AL23 V16
VSS VSS
AL29 V18
RSVD_NCTF VSS
AL3 V28
RSVD_NCTF VSS
AL30 V29
RSVD_NCTF VSS
AL9 W13
VSS VSS
B13 W2
VSS VSS
B16 W23
VSS VSS
B19 W25
VSS VSS
B22 W26
VSS VSS
B30 W28
RSVD_NCTF VSS
B31 W30
RSVD_NCTF VSS
B5 W4
VSS VSS
B9 W5
VSS VSS
C1 W6
RSVD_NCTF VSS
C12 W7
VSS VSS
C21 Y28
VSS VSS
C22 Y3
VSS VSS
C25 Y4
VSS VSS
C31
RSVD_NCTF
D22
VSS
E1
RSVD_NCTF
E10
VSS
E19
VSS
E21
VSS
E25 T29
VSS VSS
E8
VSS
F17
VSS
F19
VSS 6 OF 6
Pineview-M 1.66G

PROJECT : ZE6
1B
Pineview GND
1
1
0110 : exchange USB port 1 and port 3

U20B TGP to fix charger port will auto wake up issue.
[4] DMI_RXN0 R23 H7 USBP0- [17]

DMI0RXN USBP0N
[4] DMI_RXP0 R24 H6 USBP0+ [17] SYSTEM (Right down)
C53 0.1U/10V_4 DMI_TXN0_C DMI0RXP USBP0P
[4] DMI_TXN0 P21 H3 USBP1- [17]
C46 0.1U/10V_4 DMI_TXP0_C DMI0TXN USBP1N
[4] DMI_TXP0 P20
DMI0TXP USBP1P
H2 USBP1+ [17] SYSTEM (Right up)
[4] DMI_RXN1 T21 J2 USBP2- [14]
DMI1RXN USBP2N
[4] DMI_RXP1 T20
DMI1RXP USBP2P
J3 USBP2+ [14] CCD
C65 0.1U/10V_4 DMI_TXN1_C T24 K6
DMI
[4] DMI_TXN1 DMI1TXN USBP3N USBP3- [17]
C59 0.1U/10V_4 DMI_TXP1_C T25 K5 SYSTEM (Left)
[4] DMI_TXP1 DMI1TXP USBP3P USBP3+ [17]
T19 K1 USBP4- [20]
DMI2RXN USBP4N
T18 K2 USBP4+ [20]
SIM
DMI2RXP USBP4P
U23 L2 USBP5- [20]
DMI2TXN USBP5N
U24 L3 USBP5+ [20] 3G
DMI2TXP USBP5P
V21 M6 USBP6- [15]
DMI3RXN USBP6N
V20
DMI3RXP USBP6P
M5 USBP6+ [15] BT
V24 N1 USBP7- [20]
DMI3TXN USBP7N
V23
DMI3TXP USBP7P
N2 USBP7+ [20] WLAN
USB
D4 USBOC#R_1 R303 *0/short_4 USBOC#R [17,22] USBOC#R_1 R305 8.2K_4
OC0# +3V_S5
[18] PE1RX- K21 C5 USBOC#L_1 R297 *0/short_4 USBOC#L [17,22]
PERN1 OC1# USBOC# USBOC#L_1 R298 8.2K_4
LAN [18] PE1RX+ K22
PERP1 OC2#
D3
C259 0.1U/10V_4 PCIE_TXN1_C J23 D2 USBOC#R_1
[18] PE1TX- PETN1 OC3#
C262 0.1U/10V_4 PCIE_TXP1_C J24 E5 USBOC# USBOC# R306 1K/F_4
[18] PE1TX+ PETP1 OC4#
[20] PE2RX- M18 E6 USBOC#
PERN2 OC5#/GPIO29 USBOC#
WLAN [20] PE2RX+ M19
PERP2 OC6#/GPIO30
C2
C263 0.1U/10V_4 PCIE_TXN2_C K24 C3 USBOC#
[20] PE2TX- PETN2 OC7#/GPIO31
C266 0.1U/10V_4 PCIE_TXP2_C K25
[20] PE2TX+ PETP2
[21] PE3RX- L23
PERN3
[21] PE3RX+ L24
C270 0.1U/10V_4 PCIE_TXN3_C PERP3
Card Reader [21] PE3TX- L22
PETN3 USBRBIAS
G2
PCI-E
A C268 0.1U/10V_4 PCIE_TXP3_C M21 G3 USBRBIAS R314 22.6/F_4 A
[21] PE3TX+ PETP3 USBRBIAS#
[20] PE4RX- P17
PERN4 placed within 500 mil of the chipset
[20] PE4RX+ P18
C271 PCIE_TXN4_C
*3G@0.1U/10V_4 PERP4
3G [20] PE4TX- N25
PETN4
C274 *3G@0.1U/10V_4
PCIE_TXP4_C N24
[20] PE4TX+ PETP4
F4 CLKUSB_48 CLKUSB_48 [2]
CLK48
R78 24.9/F_4 DMI_COMP H24

+1.5V DMI_ZCOMP
J22 CLKUSB_48
DMI_IRCOMP
[2] CLK_PCIE_ICH# W23

DMI_CLKN R309
[2] CLK_PCIE_ICH W24
DMI_CLKP
2
*10/F_4
Tiger Point
C258
*10P/50V_4

PROJECT : ZE6
1B
Tiger Point DMI/PCIE/USB
1
5 4 3 2 1
09
U20C TGP
D
R12 RSVD03 SATA0RXN AE6 SATA_RXN0 [19] D
AE20 RSVD04 SATA0RXP AD6 SATA_RXP0 [19]
AD17 RSVD05 SATA0TXN AC7 SATA_TXN0 [19] SATA HDD
AC15 RSVD06 SATA0TXP AD7 SATA_TXP0 [19]
AD18 RSVD07 SATA1RXN AE8
Y12 RSVD08 SATA1RXP AD8
AA10 AD9 <20090514(A1A)_Checklist Rev0.7>
RSVD09 SATA1TXN SERIRQ:8.2K pull-up
AA12 RSVD10 SATA1TXP AC9
Y10
A20GATE:10K pull-up +3V
SATA
RSVD11
AD15 RSVD12
W10 RSVD13
V12 SERIRQ R107 8.2K_4
RSVD14 GA20 R108 10K_4
AE21 RSVD15
AE18 KBRST# R338 10K/J_4
RSVD16 PCH_GPIO36 R339 *10K/J_4
AD19 RSVD17
U12 RSVD18
AD4 <Layout note>
SATA_CLKN CLK_PCIE_SATA# [2] Close to pin within 500mil
AC17 AC4 <Layout note>
RSVD19 SATA_CLKP CLK_PCIE_SATA [2] Close to pin within 200mil
C AB13 RSVD20
C
AC13 AD11 SATARBIAS# R335 24.9/F_4
RSVD21 SATARBIAS#
AB15 RSVD22 SATARBIAS AC11
Y14 AD25 SATALED#
RSVD23 SATALED# SATALED# [15]
AB16 R340 10K/J_4
RSVD24 +3V
AE24 RSVD25
AE23 RSVD26
+1.05V
AA14 U16 GA20 <Layout note>
RSVD27 A20GATE GA20 [22] Close to pin
V14 RSVD28 A20M# Y20 H_A20M# [4]
CPUSLP# Y21
Y18 R84
IGNNE# H_IGNNE# [4]
AD21 56/J_4
INIT3_3V# +1.05V <Layout note>
AD16 RSVD29 INIT# AC25 H_INIT# [4]
AB11 AB24 Close to pin within 1"
HOST
RSVD30 INTR H_INTR [4]

B
AB10 RSVD31 FERR# Y22 H_FERR# [4] B
PCH_GPIO36 AD23 T17
GPIO36 NMI H_NMI [4]
AC21 KBRST# KBRST# [22] R103
RCIN# 56/J_4
SERIRQ AA16 SERIRQ [22]
SMI# AA21 H_SMI# [4]
STPCLK# V18 H_STPCLK# [4]
THERMTRIP# AA20 PM_THRMTRIP# [4]
3
Tiger Point
NOTE
A 1. CPUSLP# is supported only on nettop platforms. A
PROJECT : ZE6
1B
Tiger Point Sata/Host
5 4 3 2 1
5 4 3 2 1
U20A TGP
A5 B22
PCI_INTA#
PCI_INTC#
RP4 1
3
2 8.2K_8P4R
4
+3V 10
PCI_DEVSEL# B15 PAR AD0 PCI_INTF#
DEVSEL# AD1 D18 5 6
[2] PCLK_ICH J12 C17 PCI_INTB# 7 8
T27 PCICLK AD2
A23 PCIRST# AD3 C18
PCI_IRDY# B7 B17 PCI_IRDY# RP3 1 2 8.2K_8P4R
IRDY# AD4 +3V
C22 C19 PCI_LOCK# 3 4
D
PCI_SERR# PME# AD5 PCI_PERR# D
B11 SERR# AD6 B18 5 6
PCI_STOP# F14 B19 PCI_TRDY# 7 8
PCI_LOCK# STOP# AD7
A8 PLOCK# AD8 D16
PCI_TRDY# A10 PCI D15 PCI_DEVSEL#RP5 1 2 8.2K_8P4R
TRDY# AD9 +3V
PCI_PERR# D10 A13 PCI_FRAME# 3 4
PCI_FRAME# A16 PERR# AD10 PCI_REQ1#
FRAME# AD11 E14 5 6
H14 PCI_REQ2# 7 8
<20090601(A1A)_Checklist Rev0.7> AD12
AD13 L14
Strap1#/strap2#: signals have weak J14
internal pull-ups T26 AD14 PCI_STOP# R272 8.2K/J_4
A18 GNT1# AD15 E10 +3V
T31 E16 C11 PCI_SERR# R283 8.2K/J_4
GNT2# AD16 EC_SCI# R54 10K_4
AD17 E12
PCI_REQ1# G16 B9
REQ1# AD18
PCI_REQ2# A20 REQ2# AD19 B13 PCI_INTD# 1RP1 2 8.2K_8P4R +3V
L12 PCI_INTH# 3 4
AD20 PCI_INTG#
AD21 B8 5 6
PCH_GPIO48 G14 A3 PCI_INTE# 7 8
PCH_GPIO17 GPIO48/ STRAP1# AD22
C A2 GPIO17/ STRAP2# AD23 B5 C
PCH_GPIO22 C15 A6
EC_SCI# GPIO22 AD24
[22] EC_SCI# C9 GPIO1 AD25 G12
AD26 H12
C8 PCH_GPIO22 8.2K_4 R284
AD27 +3V
AD28 D9
PCI_INTA# B2 C7
PCI_INTB# PIRQA# AD29
D7 PIRQB# AD30 C1
PCI_INTC# B3 B1
PCI_INTD# PIRQC# AD31 Description
H10 PIRQD# IRQ
PCI_INTE# E8
PCI_INTF# PIRQE#/GPIO2
D6 PIRQF#/GPIO3 PIRQA USB UHCI Controller #1, #4
PCI_INTG# H8 H16
PCI_INTH# PIRQG#/GPIO4 C/BE0# AC'97 Codec; option for SMBUS
F8 PIRQH#/GPIO5 C/BE1# M15 PIRQB
C/BE2# C13
T38 PCH_A16WP D11 L16 PIRQC USB UH Controller #3; SATA/IDE Native Mode
R271 10K/J_4 STRAP0# C/BE3#
+3V K9 RSVD01
R73 8.2K/J_4 M13 PIRQD USB UHCI Controller #2
B RSVD02 B
1
PIRQE Internal LAN; Option for SCI, TCO, HPET#0,1,2
Tiger Point
PIRQF Option for SCI, TCO, HPET#0,1,2
ICH Boot BIOS select
PIRQG Option for SCI, TCO, HPET#0,1,2
PCH_GPIO17 PCH_GPIO48
(INT PU) (INT PU) Boot BIOS Location PIRQH USB EHCI Controller; Option for SCI, TCO, HPET#0,1,2
0 1 SPI
1 0 PCI
1 1 LPC (Default) PCI_GNT#2 Internal PU
Should not be PD
*1K_4 R71 PCH_GPIO48 *1K_4 R72

+3V
*1K_4 R299 PCH_GPIO17 *1K_4 R300
A A
A16 SWAP Override strap Quanta Computer Inc.
PCH_A16WP Low = A16 swap override enabled
PROJECT : ZE6
(INT PU) Size Document Number Rev
High = Default 1B
TigerPoint PCI(3/6)
5 4 3 2 1
5 4 3 2 1
<20090515(A1A)_Checklist Rev0.7>
EMI BATLOW#:8.2K pull-up to V3ALWAYS

WAKE#:10K pull-up to VccSus3_3
11
14M_ICH U20D TGP SYS_RST#:10K pull-up to VccSus3_3
T18 AA5 T15 BM_BUSY# +3V_S5

LDRQ1#/GPIO23 BM_BUSY#/GPIO0
R327
[20,22] LPCAD0 V6 W16 PCH_GPIO6 T20
LAD0/FWH0 GPIO6
LPC
*33/J_4
[20,22] LPCAD1 AA6 W14 PCH_GPIO7 T19
PCLK_SMB R273 2.2K_4
LAD1/FWH1 GPIO7
[20,22] LPCAD2 Y5 K18 EC_SMI# EC_SMI# [22]
PDAT_SMB R288 2.2K_4
LAD2/FWH2 GPIO8
[20,22] LPCAD3 W8 LAD3/FWH3 GPIO9 H19 PCH_GPIO9 PCH_GPIO10 R277 8.2K_4
T17 Y8 LDRQ0# GPIO10 M17 PCH_GPIO10 PM_BATLOW# R282 8.2K_4
[20,22] LPCFRAME# Y4 A24 PCH_GPIO12 THERM_ALERT# R104 8.2K_4
LFRAME# GPIO12
C285 C23 PCH_GPIO13 DNBSWON# R276 *10K_4
ACZ_BITCLK_R GPIO13
D
*10P/50V_4
[16] ACZ_BITCLK_AUDIO
R321 33/J_4 P6 HDA_BIT_CLK GPIO14 P5 PCH_GPIO14 PCH_GPIO9 R275 8.2K_4
D
R316 33/J_4 ACZ_RST#_R U2 E24 PCH_GPIO15
AUDIO
[16] ACZ_RESET#_AUDIO HDA_RST# GPIO15
W2 AB20 EC_SMI# R286 10K_4
[16] ACZ_SDIN0 HDA_SDI0 DPRSLPVR PM_DPRSLPVR [4,26]
V2 Y16 SYS_RST# R274 10K_4
HDA_SDIN1 STP_PCI# PM_STPPCI# [2] SMBALERT#
P8 AB19 R285 10K_4
HDA_SDIN2 STP_CPU# PM_STPCPU# [2]
R324 33/J_4 ACZ_SDOUT_R AA1 R3 PCH_GPIO24 T44 SMB_LINK_ALERT# R278 10K_4
[16] ACZ_SDOUT_AUDIO HDA_SDOUT GPIO24
debug port for google require R323 33/J_4 ACZ_SYNC_R Y1 C24 DMI_AC_ENABLE 1C: Intel suggestion enable AC mode PCIE_WAKE# R296 10K_4
[16] ACZ_SYNC_AUDIO HDA_SYNC GPIO25
14M_ICH AA3 D19 PCH_GPIO26 SMLINK1 R304 10K_4
[2] 14M_ICH CLK14 GPIO26 T28
GPIO27 D20 PCH_GPIO27 SMLINK0 R308 10K_4
T32
U3 F22 PCH_GPIO28 PCH_GPIO15 R301 8.2K_4
EPROM
EE_CS GPIO28 T11
AE2 AC19 CLKRUN# CLKRUN# [22]
ICH_RI# R279 10K_4
EE_DIN CLKRUN#
T6 U14 PCH_GPIO33 PCH_GPIO12 R289 10K/J_4
EE_DOUT GPIO33 T16
<20090529(A1A)_Checklist Rev0.7> V3 AC1 MBID0 PCH_GPIO13 R287 10K/J_4
EE_SHCLK GPIO34
If integrated LAN is not used
GPIO38 AC23 MBID1 PCH_GPIO14 R317 10K/J_4
LAN_RST# tie it to GND. T4 LAN_CLK GPIO39 AC24 MBID2
P7
LANR_STSYNC +3V
B23 AB22 H_PWRGD [4]
C279 15P/50V_4 LAN_RST# CPUPWRGD/GPIO49
AA2
LAN
LAN_RXD0
AD1 AB17 THERM_ALERT# [4,22]
LAN_RXD1 THRM#
AC2 V16 VR_PWRGD_CK410 [2]
LAN_RXD2 VRMPWRGD
MISC
R320 W3 AC18 MCH_SYNC# MCH_SYNC# R337 1K/F_4
32.768KHz,+-20PPM LAN_TXD0 MCH_SYNC#
10M/J_4 T7 LAN_TXD1 PWRBTN# E21 DNBSWON# DNBSWON# [22,23] CLKRUN# R106 8.2K_4
Y3 U4 H23 ICH_RI# BM_BUSY# R333 8.2K_4
LAN_TXD2 RI#
G22 T42
1
RTC_X1 W4 SUS_STAT#/LPCPD#
D22 SUSCLK
RTC
RTCX1 SUSCLK SUSCLK [22]
C275 15P/50V_4 RTC_X2 V5 G18 SYS_RST#
RTCRST# RTCX2 SYS_RESET# VCCRTC
T5 RTCRST# PLTRSTB G23 PLT_RST# DMI_AC_ENABLE R290 1K_4
C25 PCIE_WAKE# PCIE_WAKE# [18,20]
SMBALERT# WAKE# SM_INTRUDER# R347 1M/F_6 TPT_PWROK R336 10K_4
E20 T8
PCLK_SMB SMBALERT#/GPIO11 INTRUDER#
[2,20] PCLK_SMB H18 U10 TPT_PWROK
SMBCLK PWROK
SMB
C PDAT_SMB E23 AC3 EC_RSMRST# EC_RSMRST# R334 10K_4 C
[2,20] PDAT_SMB SMBDATA RSMRST# EC_RSMRST# [22,23]
SMB_LINK_ALERT# H21 AD3 ICH_INTVRMEN
SMLINK0 SMLALERT# INTVRMEN R331 332K/F_4
F25 SMLINK0 SPKR J16 SB_BEEP [16]
SMLINK1 F24
SMLINK1
H20 SUSB# [22]
T43 SLP_S3#
R2 SPI_MISO SLP_S4# E25 SUSC# [22]
T46 T1 F21
SPI_MOSI SLP_S5# T12
SPI
T14 M8
SPI_CS#
T15 P9 B25 PM_BATLOW#
T45 SPI_CLK BATLOW#
R4 AB23 ICH_DPRSTP# [4,26]
SPI_ARB DPRSTP# +3V
DPSLP# AA18 H_DPSLP# [4]
F20
RSVD31
R329 R343 R342

Tiger Point
10K_4 *10K_4 *10K_4
MBID2
<20090721(B2A)> MBID1
Stuff U19 and C275 and un-stuff R205 for power sequence MBID0
Platform Reset TPT Power OK R328 R332 R330

*10K_4
*10K_4 10K_4
+3V
B
RTC(RTC) VCCRTC
+3V
C252 *0.1u/10V_4
C98 *0.1u/10V_4
B
U6
5
U17
5
D33 C293 2 *TC7SH08FU

[22,23] HWPG
+3VPCU PLT_RST# 2 *TC7SH08FU 4 TPT_PWROK
TPT_PWROK [23]
4 PLTRST# [4,18,20,21,22,23] [4,23,26] IMVP_PWRGD 1
CH500H-40 1u/10V_6 1
3
D32 R344 R307
3
VCCRTC_3 RTCRST#
100K_4
CH500H-40 20K/F_6 G1
1
C288
R135 0_4
1u/10V_6 R302 *0/short_4
R354 *SHORT_PAD
2
1K_4
[22,23] ECPWROK R110 *0_4
+5V_S5
20MIL 20MIL
VCCRTC_4 1 3 VCCRTC_1 R160 2K/F_4 VCCRTC_2 R165 2K/F_4
Q10 ACZ_SDOUT ACZ_SYNC INTVRMEN

MMBT3904 (INT PD) (INT PD) Description
2
R161 Enable internal VccSus1_5 VRM

1 (default)
68.1K/F_4
1
A 0 0 * 4 x 1s 0 Disable A
CN5 R162 1 0 Reserved

RTC SOCKET
150K/F_4
0 1 Reserved
2
1 1 1 x 4s(1 port/4 lanes)

PROJECT : ZE6
1.Level 1 Environment-related Substances Should NEVER be Used. 1A
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. TigerPoint GPIO
5 4 3 2 1
1
<Layout note>
Place 0402 caps close to ball 12
Place 0603/0805 caps close to ICH
D30 1 2 1SS355 +3V

VCC5_VCC5REF R270 100/F_4
+5V
C37 1u/10V_4
D31 1 2 1SS355
TGP +3V_S5
U20E RVCC5_VCC5REF_SUS R312 10/F_4
+5V_S5
C264 0.1u/10V_4
6mA VCC5REF
F12
VCC1.5_SATAPLL R109 *0/short_6

+1.5V
10mA F5 C83 0.1u/10V_4
VCC5REF_SUS
45mA Y6 C291 0.1U/10V_4 C97
VCCSATAPLL C290 0.01U/25V_4 4.7U/10V/8
6uA VCCRTC
AE3 VCCRTC
24mA Y25 VCC1.5_VCCDMIPLL L26 *0/short_6
VCCDMIPLL +1.5V
C281 0.01U/25V_4
10mA VCCUSBPLL
F6
C283
*4.7u/6.3V_6
14mA W18 VCCP_VCC1_05

V_CPU_IO
1.422A AA8 VCC1.5_VCC1.5 R341 *0/short_6

VCC1_5_1 +1.5V
M9 C66 0.1U/10V_4
VCC1_5_2 C67 0.1U/10V_4
M20
VCC1_5_3 C60 1U/6.3V_4
N22
VCC1_5_4 C89 1U/6.3V_4
C289 4.7U/10V/8
POWER
0.955A J10 VCCP_VCC1_05 R319 *0/short_6

VCC1_05_1 +1.05V
K17 C71 1U/6.3V_4
VCC1_05_2 C68 1U/6.3V_4
A P15 A
VCC1_05_3 C277 4.7U/10V/8
V10
VCC1_05_4
0.216A H25 VCC3_VCC3 R105 *0/short_6 +3V

VCC3_3_1 C90 1U/6.3V_4
AD13
VCC3_3_2 C48 1U/6.3V_4
F10
VCC3_3_3 C70 1U/6.3V_4
G10
VCC3_3_4 C73 0.1U/10V_4
R10
VCC3_3_5 C47 0.1U/10V_4
T9
VCC3_3_6
0.092A F18 RVCC3_VCCSUS3 R311 *0/short_6 +3V_S5

VCCSUS3_3_1 C261 1U/6.3V_4
N4
VCCSUS3_3_2 C51 1U/6.3V_4
K7
VCCSUS3_3_3 C260 0.1U/10V_4
F1
VCCSUS3_3_4
Tiger Point

PROJECT : ZE6
1.Level 1 Environment-related Substances Should NEVER be Used. 1B
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. TigerPoint Power
1
1
13
U1LB
U20F TGP
A1
VSS01
A25
VSS02
B6
VSS03
B10
VSS04
B16
VSS05
B20
VSS06
B24
VSS07
E18
VSS08
F16
VSS09
G4
VSS10
G8
VSS11
H1
VSS12
H4
VSS13
H5
VSS14
K4
VSS15
K8
VSS16
K11
VSS17
K19
VSS18
K20
VSS19
L4
VSS20
M7
VSS21
M11
VSS22
N3
VSS23
N12
VSS24
N13
VSS25
N14
VSS26
N23
VSS27
P11
VSS28
P13
VSS29
P19
VSS30
R14
VSS31
R22
VSS32
T2
VSS33
T22
VSS34
V1
VSS35
V7
VSS36
V8
VSS37
V19
VSS38
V22
VSS39
A V25 A
VSS40
W12
VSS41
W22
VSS42
Y2
VSS43
Y24
VSS44
AB4
VSS45
AB6
VSS46
AB7
VSS47
AB8
VSS48
AC8
VSS49
AD2
VSS50
AD10
VSS51
AD20
VSS52
AD24
VSS53
AE1
VSS54
AE10
VSS55
AE25
VSS56
G24
VSS57
AE13
VSS58
F2
VSS59
AE16
RSVD32
Tiger Point

PROJECT : ZE6
1.Level 1 Environment-related Substances Should NEVER be Used. 1B
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. TigerPoint GND
1
5 4 3 2 1
<20090724(B2A)>
Change R5 from CS41002JB20 to
CS44702JB15 (Follow vendor's R102
HALL SENSOR(HSR)
100K_4 LED Panel POWER SWITCH(LDS) CAMERA POWER(CCD)
+3VPCU +3V
suggestion and reduce power)
CCD_POWER 0.15A
Irush=1.5A
PT3661-BB: AL003661003 ; pull-up: 470K ohm D6 R260 *0/short_8 CCD_POWER
1 2 LID# 1 2
+3V C242 4.7U/10V/8
+
*VPORT_6
C95
D LCDVCC_1 LCDVCC D
C245 1000p/50V_4
3
0.1u/25V_6 MR1
R101 PT3661-BB R257 *0/short_8 C236 *0.1u/10V_4
10K_4
1
C230 C239 C233 C232
D5 BAS316
LID# [22]
*0.1u/10V_4 0.1u/10V_4 33p/50V_4 10u/10V_8
LED Panel(LDS)
2
VIN
+3V R269 *0/short_8 V_BLIGHT
DISPON C248 C247

4.7U/25V_8 0.1U/50V_6
3
R83 CN1
10K_4 +3V R385 0_8 1
+5V 1
2 2
2 BL# LCDVCC 3
Q5 <20090721(B2A)> reserve for IVO panel C325 C324 LCDVCC 3
LCDVCC 4
Change Q13,Q14 from BAM700200F6 to C235 U16 LCDVCC_1 *4.7U/25V_8 *0.1U/50V_6 4
+3V 5 5
3
2N7002K BAM70020002 (with ESD protection function) CCD_POWER 6

CCD_POWER 6
1u/10V_6 6 1 7
1
IN OUT 7
8 8
2 INT_LVDS_BLON [4] 4 IN GND 2 9 9
C
Q3 R48 *0/short_J_4 USBP2-_CCD 10
[4] INT_LVDS_PWM 10 C
3 5 USBP2+_CCD 11
[4] INT_LVDS_DIGON ON/OFF GND 11
2N7002K R82 R43 *0/J_4 12
[22] CONTRAST 12
DISPON 13
1
100K_4 R259 IC(5P) G5243AT11U C25 *3300P/50V_4 LCD_VADJ 13

14
14
3
15
INT_TXLOUTN2_L 15
16
100K_4 INT_TXLOUTP2_L 16
2 EC_FPBACK# [22] 17
17
18 18
Q4 INT_TXLOUTN1_L 19
DTC144EU INT_TXLOUTP1_L 19
20
1
20
21 21
R33 *0/short_4 INT_TXLOUTN0_L 22
INT_TXLOUTP0_L 22
23
23
24
INT_TXLOUTN0_L INT_TXLCLKN_L 24
[4] INT_TXLOUTN0 25 25
01/15 Modify [4] INT_TXLOUTP0 INT_TXLOUTP0_L INT_TXLCLKP_L 26
CRT(CRT) F1
C250 0.1u/10V_4
R35 *0/short_4
[4] LVDS_CLK
LVDS_CLK
LVDS_DATA
27
28
29
26
27
28
31
CRTVDD5 [4] LVDS_DATA 29 31
CN10 R384 *0_8
16
+5V 1 2 LCDVCC 30 30 32 32
SMD1206P110TFT R39 *0/short_4 LCD CONN

6
L14 PBY160808T-220Y-N CRT_R1 1 11 CRT_11 T7
[4] CRT_R INT_TXLOUTN1_L
7 [4] INT_TXLOUTN1
B L16 PBY160808T-220Y-N CRT_G1 2 12 DDCDAT_1 [4] INT_TXLOUTP1 INT_TXLOUTP1_L B
[4] CRT_G
8
L15 PBY160808T-220Y-N CRT_B1 3 13 CRTHSYNC
[4] CRT_B
9 R41 *0/short_4
4 14 CRTVSYNC
R85 R86 R87 C62 C63 C64 C56 C50 C55 10
5 15 DDCCLK_1 R34 *0/short_4
150/F_4 150/F_4 150/F_4 *10p/50V_4 *10p/50V_4 *10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
CRT CONN [4] INT_TXLOUTN2 INT_TXLOUTN2_L
17
[4] INT_TXLOUTP2 INT_TXLOUTP2_L
R37 *0/short_4
R38 *0/short_4
+3V
C38 U3
CRTVDD5 1 16 CRT_VSYNC1 R45 22_4 VSYNC_R L10 BLM18BA220SN1D_22_6 CRTVSYNC INT_TXLCLKN_L R31 *0/short_4
VCC_SYNC SYNC_OUT2 [4] INT_TXLCLKN
0.1u/10V_4 14 CRT_HSYNC1 R44 22_4 HSYNC_R L9 BLM18BA220SN1D_22_6 CRTHSYNC INT_TXLCLKP_L
SYNC_OUT1 [4] INT_TXLCLKP
7
C43 0.22u/25V_6 CRT_BYP VCC_DDC
8 BYP
15 CRTVDD5 C249 *10p/50V_4 CRTVDD5 R40 *0/short_4 USBP2+_CCD
SYNC_IN2 CRT_VSYNC [4] [8] USBP2+
2 13 USBP2-_CCD
+3V VCC_VIDEO SYNC_IN1 CRT_HSYNC [4] +3V [8] USBP2-
C20 2 1 *33p/50V_4 CRTVSYNC
A A
C49 CRT_R1 3 10 CRT_SCL CRT_SCL R53 2.2K_4 R46 R42 C21 2 1 *33p/50V_4 CRTHSYNC R32 *0/short_4
VIDEO_1 DDC_IN1 CRT_SCL [4]
0.1u/10V_4 CRT_G1 4 11 CRT_SDA CRT_SDA R58 2.2K_4 2.2K_4 2.2K_4
VIDEO_2 DDC_IN2 CRT_SDA [4]
CRT_B1 5 C31 *10p/50V_4 DDCCLK_1
VIDEO_3 DDCCLK_1
9
6
GND
DDC_OUT1
DDC_OUT2
12 DDCDAT_1 C27 *10p/50V_4 DDCDAT_1 Quanta Computer Inc.
IP4772_Rout=10ohm
PROJECT : ZE6
1B
CRT/LVDS
5 4 3 2 1
5 4 3 2 1
TOUCH PAD (TPD) +5V_TP

BLUETOOTH(BTM)
3mA
+5V
+5V_TP
4.7K/J_4 4.7K/J_4
<EMI>
CN3 R262 R261
L12 3A/120ohm_8
1 TP_R# CX121T30001:3A/120ohm_8
2 <EMI>
TP_L# BT@AO3413
3 TPDATA_CN L25 0.4A/120ohm_6
4 TPDATA [22]
TPCLK_CN L24 0.4A/120ohm_6 CN6
D 7 5 TPCLK [22] D
+5V_TP C30 +3V 1 3 BT_POWER
8 6 CX08T121000:0.4A/120ohm_6 5
CX121T04000:0.4A/120ohm_6 .1U/10V_4 Q14 4 6
TP_CONN [8] USBP6+ 3
C29 C28 + C160
[8] USBP6-
2
C159 T22 BT_LED 2 7
10P/50V_4 10P/50V_4 BT@0.22u/25V_6 1
BT@1000p/50V_4
R169 BT@CONN
[20,22] BT_POWERON#
BT@10K_4
C156
*BT@1000p/50V_4
SW2 SW3
3 1 TP_L# 3 1 TP_R#
4 2 4 2
1
1
5 5
6 TP switch D36 6 TP switch D35
*14V/38V/100P_4 *14V/38V/100P_4
2
2
C KEYBOARD (KBC) LED/SW (UIF) PWR Button C
SW1
3 2 NBSWON#
NBSWON# [22,23]
+3VPCU D15 1 2 *5.5V/25V/410P_4 4 1
<20100303(C3A)> 5
1
20110117 : add CP1~CP6 for EMI issue LED2 6
PWR LED 3 2 R222 200/J_4 PWRLED# [22]
power switch
D22
*5.5V/25V/410P_4
<EMI> 1 R223 470/J_4
SUS LED SUSLED# [22]
2
CN2
LED_AMBER/BLUE
1 MX7 MX7 7 8 D16 1 2 *5.5V/25V/410P_4
MX7 [22]
2 MX6 MX6 5 6 CP1
MX6 [22]
3 MX5 MX5 3 4 220P_8P4R side view
MX5 [22]
4 MY0 MY0 1 2
MY0 [22]
5 MY1 MY1 7 8
MY1 [22]
6 MY2 MY2 5 6 CP2
MY2 [22]
7 MX4 MX4 3 4 220P_8P4R D17 1 2 *5.5V/25V/410P_4 SW4
MX4 [22]
8 MY3 MY3 1 2 +3VPCU
MY3 [22]
9 MY4 MY4 7 8 LED3 3 2 NBSWON#
10
11
MY5
MY6
MY4 [22]
MY5 [22]
MY6 [22]
MY5
MY6
5
3
6
4
CP3
220P_8P4R
FULL LED 3 2 R224 200/J_4 BATLED0# [22] 4
5
1
12 MY7 MY7 1 2 1 R225 470/J_4 6

13
14
MY8
MX3
MY7 [22]
MY8 [22]
MX3 [22]
MY8
MX3
7
5
8
6 CP4
CHG LED LED_AMBER/BLUE
BATLED1# [22]
*DIP-TJG-533-S-V-T/R
15 MY9 MY9 3 4 220P_8P4R D18 1 2 *5.5V/25V/410P_4
MY9 [22]
16 MX2 MX2 1 2
MX2 [22]
17 MX1 MX1 7 8 side view
MX1 [22]
18 MY10 MY10 5 6 CP5
MY10 [22]
B 19 MY11 MY11 3 4 220P_8P4R B
MY11 [22]
20 MX0 MX0 1 2
MX0 [22]
21 MY12 MY12 7 8 D20 1 2 *3G@5.5V/25V/410P_4
MY12 [22]
22 MY13 MY13 5 6 CP6 +3V
MY13 [22]
23 MY14 MY14 3 4 220P_8P4R LED5
24 MY15
MY14 [22]
MY15 [22]
MY15 1 2 3G LED 3 2 R228 *3G@270/J_4
3G_MINI_LED# [20]
W/O 3G: use BE0R0083Z00
0402 size 1 R229 470/J_4 W 3G: use BEB00023ZA0
25 WLAN LED LED_AMBER/BLUE
WLAN_LED# [20]
26 D21 1 2 *5.5V/25V/410P_4
side view <20090609(A1A)_Checklist Rev1.0>

KB CONN SATALED# [9]
Need the buffer for LED driving
capability since the IOL is 6mA only.
*BSS84
2
+5V Q18
LED4
HDD LED 3 1 R226 *330/J_4 1 3
*LED_BULE
D19 1 2 *5.5V/25V/410P_4
side view
PWR: Blue Vf: 2.55~3.15V, If=20mA

SUS: Orange Vf=1.6~2.0V, If=20mA
A A
+3V
LED1
PWR indicator 2 1 R238 120/J_4
LED_BLUE
PROJECT : ZE6
1B
KB/BT/TP/LED/Power Connector
5 4 3 2 1
5 4 3 2 1
HPR
Codec(ADO) HEADPHONE
HPL
MIC1-VREFO-L Universal Jack

CN14
MIC1-VREFO-R COMBO MIC 3
6
HPL R361 47/F_4 HPL-1 L28 *0/short_6 HPL_SYS 1
ADOGND MIC2-VREFO
HPR R359 47/F_4 HPR-1 L27 *0/short_6 HPR_SYS 2
Place near codec 4
1
IN_MIC-VREFO C140 4.7U/6.3V_6 C151 place near to codec R358 R360 C299 C300 HP_JD# 5
ADOGND
D8 D9 UNIVERSAL JACK
C134 *1K/J_4 *1K/J_4 2200P/50V_4 2200P/50V_4 010030FR006G119ZR
1
Place next to pin 27 *14V/38V/100P_4 *14V/38V/100P_4
2
+
2.2u/6.3V_6 D7
*14V/38V/100P_4
D C135 C137 ADOGND ADOGND ADOGND D
2
C136 +
C133 ADOGND *10u/6.3V_6 0.1u/10V_4 +5VA
2.2U/6.3V_6
+5VA +
ADOGND
2.2u/6.3V_6 MIC2-VREFO
C141 C142 C139 R122

4.7U/6.3V_6 0.1u/10V_4 2.2K/J_4
36
35
34
33
32
31
30
29
28
27
26
25
U8 C138
0.1u/10V_4 C153 2.2U/6.3V_6 MIC2_R2
VREF
HP-OUT-L
MIC1-VREFO-L
AVSS1
AVDD1
MIC2-VREFO
CBN
HP-OUT-R
MIC1-VREFO-R
CBP
CPVEE
LDO-CAP
4.7U/6.3V_6
ADOGND ANALOG ADOGND
Place next to pin 38 COMBO MIC R123 1K/J_4 C155 2.2U/6.3V_6 MIC2_L2
Spilt by AGND 37 24 ADOGND
AVSS2 LINE1-R
Place next to pin 25
1
38 23 R118 <20100917> Add 22k PD by FAE
C3C AVDD2 LINE1-L D39 22K/F_4
R151 *0/short_6 +5VPVDD1 39 22 MIC1_R1 suggestion for discharing
+5V PVDD1 MIC1-R *14V/38V/100P_4
2
L_SPK+ 40 21 MIC1_L1
C148 C149 C147 C150 SPK-L+ MIC1-L MIC2-JD#
L_SPK- 41 20
Placement near Audio Codec ADOGND ADOGND
4.7U/6.3V_6 0.1u/10V_4 4.7U/6.3V_6 0.1u/10V_4 SPK-L- MONO-OUT
3
42 19 R152 20K/F_4 Q7
PVSS1(Vista Premium Version) JDREF ADOGND
2SK3018
43 18 SENSEB R155 20K/F_4 MIC2-JD#
PVSS2 Sense-B COMBO MIC R125 22K/F_4 2
Place next to pin 39 R_SPK- 44 17 MIC2_R2
SPK-R- MIC2-R
R_SPK+ 45 16 MIC2_L2
C3C SPK-R+ MIC2-L C120
Spilt by PGND
1
R174 +5VPVDD2
*0/short_6 46 15 LINE2_R2 4.7U/10V/8
+5V PVDD2 GPIO0/DMIC-DATA LINE2-R
GPIO1/DMIC-CLK
EAPD# 47 14 LINE2_L2
C165 C166 C167 C168 SPDIFO2/EAPD LINE2-L
Spilt by DGND
SENSEA R179 39.2K/F_4 HP_JD# ADOGND
SDATA-OUT
48 13
4.7U/6.3V_6 0.1u/10V_4 4.7U/6.3V_6 0.1u/10V_4 SPDIFO Sense A
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
49 R175 20K/F_4 MIC1_JD#
DVDD1
DVSS2
PGND
SYNC
ANALOG
PD#
C C
Place next to pin 46 ALC271X
1
10
11
12
PCBEEP dont coupling any signals if possible
DIGITAL 8/17 separate PCBEEP to Digital from Realtek suggestion System MIC MIC1-VREFO-R
C3C 1.6Vrms R199 47K/J_4 MIC1-VREFO-L
PCBEEP [22]
+3V R200 *0/short_6 +AZA_VDD
PCBEEP_1 C181 1u/10V_6 BEEP_1 R220 47K_4 SB_BEEP [11]
R356 R355
C193 R213 4.7K/F_4 4.7K/F_4
C170 C174 4.7K_4 If either HDA device io power use +1.5V,
0.1u/10V_4 4.7U/6.3V_6 100p/50V_4 all device IO power change to +1.5V
CN13
3
Place next to pin 1 6
R196 *0/short_6 MIC1_L1 C151 4.7u/6.3V_6 MIC1_L2 R113 1K/F_4 MIC1_L3 R346 *0/short_6 MIC1_L 1
+AZA_VDD
T49 DMIC_DAT_L
T50 DMIC_CLK_L C-test MIC1_R1 C144 4.7u/6.3V_6 MIC1_R2 R114 1K/F_4 MIC1_R3 R345 *0/short_6 MIC1_R 2
C173 C183 4
ACZ_RESET#_AUDIO MIC1_JD# 5
ACZ_RESET#_AUDIO [11]
PD# 0.1u/10V_4 4.7U/6.3V_6 UNIVERSAL JACK
0V : Power down Class D SPK amplifer ACZ_SYNC_AUDIO [11] C326 C105 010030FR006G119ZR
3.3V : Power up Class D SPK amplifer C286 C287 C298
ACZ_SDIN R185 33/J_4 *22P-50V_4 *22P-50V_4 Normal Open Jack
ACZ_SDIN0 [11]
Place next to pin 9 MIC1_JD# *470p/50V_4 *470p/50V_4 *0.1u/16V_6
ACZ_SDOUT_AUDIO [11]
1
D34
ACZ_BITCLK_AUDIO [11] ADOGND ADOGND
*VPORT_6 Near CN13
2
C175 *22p/50V_4 place near codec IC ADOGND
ADOGND
R363 *Short_4
R136 *0_6
R193 *0_6
R178 *0_6
B R144 *0_6 B
R97
R158
*0_6
*0_6
Internal Analog MIC
R127 *0_6
IN_MIC-VREFO
R357 *0_6
R132 *0_6
R325 *0_6
R168 *0_6 R131
R180 *0_6 10K_4 place near codec IC
C292 *1000p/50V_4
Power (ADO) C282 *1000p/50V_4 CN4
LINE2_R2
R539 1K/J_4 C158 1u/10V_6
1 C161 1u/10V_6 LINE2_L2
2
Demodulation Filter L17 Place close to Codec
1
ADOGND 6/15:C203,R210,R98 short for EMI request INT_MIC
D38 C104
C327 C328
*14V/38V/100P_4 *22P-50V_4
2
*22P-50V_4 *22P-50V_4
+5V DIGITAL ANALOG +5VA

ADOGND
ADOGND ADOGND
L17 0_8 Mute(ADO) ADOGND ADOGND
Internal Speaker
+5V
R184 40mil for each signal

*10K_4
CN7
R_SPK+ R210 *0/short_6 R_SPK+_1
A 4 A
PD# *BAS316 D13 ACZ_RESET#_AUDIO R_SPK- R198 *0/short_6 R_SPK-_1
L_SPK- R192 *0/short_6 L_SPK-_1 3 5
L_SPK+ R176 *0/short_6 L_SPK+_1 2 6
*BAS316 D14 EAPD# 1
SPEAKER-CON
C194 C186 C177 C169
*BAS316 D12 *68p/50V_6 *68p/50V_6 *68p/50V_6 *68p/50V_6
AMP_MUTE# [22]
R375 0_4

PROJECT : ZE6
1A
AUO/AMP
5 4 3 2 1
5 4 3 2 1
17
USB for iPod charge (USB)
+3VPCU
G547E1P81U: Enable: high active
Need infrom EC engineer modify
R369 +5VPCU
U22
*47K_4 C317 *0.1u/10V_4 G547E1P81U
2 8 5VUSB_1
IN1 OUT3
5
3 7
BC_CEN IN2 OUT2
2 6
USB_BC_EN OUT1
4 4
EN
[22] USB_CHARGE_ON 1 1
D GND D
5
C314 OC#
3
U23 1u/6.3V_4
*TC7SH08FU
USBOC#L [8,22]
R368 0/J_4
B-test:
have charge IC function: stuff U10,U23,R369,C179,R376,R377,R380,R381
no charge IC function : stuff R368,R378,R379,R382,R383
<Layout note>3528 type H=1.9mm <Layout note> 5VUSB_1
Close to CONN
2A
+5VPCU
C307
C179 *0.1u/10V_4 <Layout note> + C313
Co-lay .1U/10V_4 Left
100U/6.3V_3528
U10
*IC(8P)MAX14566AE R177 *0/short_4 CN19
USBP3- R380 *0/J_4 USBP3-_L1 1 5 USBP3-_L R376 *0/J_4 USBP3-_R
USBP3+ R381 *0/J_4 USBP3+_L1 CEN VCC USBP3+_L R377 *0/J_4 USBP3+_R 1 6
USBP3- USBP3-_L1 USBP3-_L USBP3-_R USBP3-_CN VDD GND6
[8] USBP3- 7 2 2 5
USBP3+ USBP3+_L1 TDM DM USBP3+_L USBP3+_R USBP3+_CN D- GND5
[8] USBP3+ 6 3 3
USBP3- R382 0/J_4 USBP3-_L2 TDP DP USBP3-_L2 R378 0/J_4 USBP3-_R D+
4 4 7
USBP3+ R383 0/J_4 USBP3+_L2 GND USBP3+_L2 R379 0/J_4 USBP3+_R GND1 GND7
8 9 8
CB EPAD GND8
1
R181 *0/short_4
D11 D10 USB_CONN
*5V/30V/0.2P_4 *5V/30V/0.2P_4
2
[22] CHARGE_IC_ON QCI P/N & Footprint
<20100128(B2A)>
Change CN14,16,17(USB CONN) from DFHS04FR201
to DFHS04FR362.
System Status: .
C C
> Lo: AM, autodetection charger identification active.
> HI: PM, pass-through mode active, DP/DM connected to TDP/TDM.
USB(USB)
+5VPCU
+3VPCU C276
4.7u/10V_6 U19 2A
R318 IC(8P)G547E2P81U
*10K_4 2 8 5VUSB_0
IN1 OUT3
3 7
IN2 OUT2 <Layout note>
OUT1
6 Right up
USB_EN# 4 Close to CONN C17
[22] USB_EN# EN# + C35
1
GND 0.1u/10V_4 CN9
9 5 USBOC#R [8,22]
GND-C OC# 220u/6.3V_7343
1 6
VDD GND6
2 5
R18 *0/short_4 D- GND5
3
D+
4 7
GND1 GND7
8
USBP1-_CN GND8
[8] USBP1-
USBP1+_CN USB_CONN
[8] USBP1+
R16 *0/short_4
1
D1 D2
*5V/30V/0.2p_4 *5V/30V/0.2p_4
2
B B
5VUSB_0
<Layout note>
Close to CONN C269
+ C16
0.1u/10V_4
*100u/6.3V_3528 Right down
R70 *0/short_4 CN12
1 6
USBP0-_CN VDD GND6
[8] USBP0- 2 5
USBP0+_CN D- GND5
[8] USBP0+ 3
D+
4 7
GND1 GND7
8
GND8
1
R68 *0/short_4
D3 D4 USB_CONN
*5V/30V/0.2p_4 *5V/30V/0.2p_4
2
A A

PROJECT : ZE6
1B
USB on Board/LED/SW/HOLE
5 4 3 2 1
5 4 3 2 1
LAN (LAN) 18
+3V_S5 +3V_LAN VDD10 R255 *0/short_6 EVDD10
1
R252 *0/short_6
Close To IC C237 C241 Close To IC Pin 13.
C228 C229 C246 1U/10V_4 0.1U/16V_4
2
1
C224 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4
C5 C243 C15
0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 *4.7U/10V/8
2
D D
R256 *0/short_6 CTRL12

Close to IC
C238
Close To IC Pin 31.
0.1U/16V_4
C10 33P/50V_4 25MCLKX1 25MCLKX1 LAN_ACTLED#

25MCLKX2
25MCLKX2 CTRL12 GPO R265 1K/J_4 +3V_LAN
R15 2.49K/F_4 RSET LAN_LINKLED# +3V_LAN
1
Y1
U2 CLKREQ_LAN#_L R251 *10K/J_4
32
31
30
29
28
27
26
25
25MHz-LAN
2
PCIE_WAKE# R28 *10K/J_4
RSET
LEDPIN/SPICSB
EESKPIN/LED1/TCLK/SPISCK
GPOUTPIN
CTRL12
CKXTAL2
CKXTAL1
VDD3
33
C8 33P/50V_4 GND EEDI/SDA R266 10K/J_4
34
GND
35 GND EECS/SCL R267 10K/J_4
+3V_LAN 1 24 EEDI/SDA
TX0P HV EEDIPIN/TDI/SPISI/SDA LED3/EEDO
2 23 T6
TX0N MDIP0 EEDOPIN/LED3/SPISO EECS/SCL
3 22
PU in CLK Gen. TX1P MDIN0 EECSPIN/TCS/SCL VDD10
4 21
TX1N MDIP1 VDD1 PCIE_WAKE# Int. PU in SB
5 20 PCIE_WAKE# [11,20]
C MDIN1 LANWAKEBPIN C
6 19 +3V_LAN
VDD10 NC VDD3 ISOLATE# R30 1K/J_4
7 18 +3V
R13 *0/short_4
CLKREQ_LAN#_L VDD1 ISOLATEBPIN R27 15K/J_4
[2] CLKREQ_LAN# 8 17
CLKREQBPIN PERSTBPIN
RTL8105TA-VC-CG
36 R268 *0/short_4
GND PLTRST# [4,11,20,21,22,23]
REFCLK_N
REFCLK_P
37
GND
38
GNDTX
VDDTX
GND
HSON
HSOP
39
HSIN
HSIP
GND
GND
GND
GND
1
C244
*4.7U/10V/8
40
41
42
9
10
11
12
13
14
15
16
2
[8] PE1TX+
[8] PE1TX-
[2] CLK_PCIE_LANP
[2] CLK_PCIE_LANN
EVDD10
C11 .1U/10V_4 PCIE_RXP0_LAN
[8] PE1RX+
C12 .1U/10V_4 PCIE_RXN0_LAN
[8] PE1RX-
For Rural
TRANSFORMER (LAN) RJ45 Connector (LAN)
B B
CN8
U13 U15 LAN_LINKLED# R254 *510/J_6 11
TX0P R9 0/J_4 TX0P_R X-TX1N Y-
1 8 1 8 +3V_LAN 12
TX0N R8 0/J_4 TX0N_R 1 8 X-TX1P 1 8 C240 Y+
2 7 2 7
TX1P R7 0/J_4 TX1P_R 2 7 X-TX0N 2 7
3 6 3 6
TX1N R6 0/J_4 TX1N_R 3 6 X-TX0P 3 6 *0.1U/50V_8 TERM9
4 5 4 5 8
4 5 4 5 NC4/3-
*UCLAMP2512T.TCT *UCLAMP2512T.TCT 7
NC/3+
X-TX1N 6 RX-/1-
TERM9 5
with ESD solution:R22,R13,R20,R26 need to use 1 ohm. NC2/2-
without ESD solution:R22,R13,R20,R26 need to use 0 ohm. U14 4
with ESD solution: stuff R35,U3,U8,D8 NC1/2+
without ESD solution: remove R35,U3,U8,D8 X-TX1P 3
TX1N_R X-TX1N RX+/1+
8 9
TX1P_R TD- TX- X-TX1P X-TX0N
7 10 2
TD+ TX+ TERM0 TX-/0-
6 CT CT 11
5 12 X-TX0P 1
NC NC TX+/0+
4 13 14
NC NC GND
3 CT CT 14 GND 13
TX0N_R 2 15 X-TX0N LAN_ACTLED# R239 *510/J_6 9
TX0P_R RD- RX- X-TX0P R242 *0/J_4 W-
1 16 +3V_LAN 10
RD+ RX+ C209 W+
2
C210 NS0014 LF_Bothhand R240 R243 *0.1U/50V_8 RJ45-CONN

C216 C215 C214 C213 D28
75/F_8 75/F_8 11/18 change connector pin define
*10p/50V_4 *10p/50V_4 *10p/50V_4 *10p/50V_4 0.01U/25V_4 Main:DFTJ12FR087
A *BS3500N-C A
White LED:pin9(-),pin10(+)
Amber LED:pin11(-),pin12(+)
1
The value should be

TERM9
0.01uF-0.4uF.
C223 Quanta Computer Inc.

1000P/3KV_1808
PROJECT : ZE6
1B
LAN RTL8105TA-VC-CG
5 4 3 2 1
5 4 3 2 1
D D
CN11
1
2 SATA_TXP0A C45 0.01u/16V_4 SATA_TXP0 SATA_TXP0 [9]
3 SATA_TXN0A C44 0.01u/16V_4 SATA_TXN0 SATA_TXN0 [9]
4
5 SATA_RXN0A C42 0.01u/16V_4 SATA_RXN0 U18
SATA_RXN0 [9]
6 SATA_RXP0A C41 0.01u/16V_4 SATA_RXP0 *CM1213-04SO
SATA_RXP0 [9]
7 SATA_RXP0A 1 6 SATA_RXN0A
CH1 CH4 +5V
8 2 5
VN VP
9
14 10 SATA_TXN0A 3 4 SATA_TXP0A C265
CH2 CH3
15 11 1A
C 16 12 5V_SATA R36 *0/short_8 +5V *0.1u/10V_4 C
17 13
+
C18 C19 C26 C22
MAIN_SATA .1U/10V_4 *0.1U/10V_4 4.7U/10V/8 *100U/6.3V_3528
C test: unstuff C22 for Cost down
B B
A A

PROJECT : ZE6
1B
SATA-HDD
5 4 3 2 1
5 4 3 2 1
Mini Card(MNC) +1.5V_Mini1_VDD +3V_Mini1_VDD 20

+3V_Mini1_VDD
+3V_Mini1_VDD 0.75A
CN20 R367 RF_LED_ON R159 *0/short_4 3G_MINI_LED# +3V +3V_Mini1_VDD
R372 *0/J_4 51 52 4.7K/F_4
[15,22] BT_POWERON# Reserved +3.3V
49 50 R170 *0/short_8
Reserved GND
2
PLTRST# R371 *0_4 47 48
R370 *0_4 Reserved +1.5V +3VSUS C322 C321 C308 C309 C312
[2] PCLK_DEBUG 45 46
Reserved LED_WPAN# WLAN_LED#_R
43 44 1 3 WLAN_LED# [15]
GND LED_WLAN# R366 *0/short_4 R171 *0_8 *10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 +3V_Mini1_VDD
41 42
+3.3Vaux LED_WWAN# Q12
39 40
+3.3Vaux GND *3G@2N7002K
37 38 USBP7+ [8]
D GND USB_D+ D
35 36 USBP7- [8]
GND USB_D-
4
2
33 34 R386 WLAN@0_4
[8] PE2TX+ PETp0 GND
31 32 WL_SMDATA RN1
[8] PE2TX- PETn0 SMB_DATA
29 30 WL_SMCLK
GND SMB_CLK *4.7K_4P2R
27 28
GND +1.5V Q19
[8] PE2RX+ 25 26
PERp0 GND
2
[8] PE2RX- 23 24 0.5A *2N7002E
3
1
PERn0 +3.3Vaux PLTRST#_2 R365 *0/short_4 PLTRST#
21 22 PLTRST# [4,11,18,21,22,23]
GND PERST# RF_EN +1.5V +1.5V_Mini1_VDD WL_SMDATA
19 20 RF_EN [22] [2,3] SMBDT1 3 1
UIM_C4 W_DISABLE#
17 18
UIM_C8 GND R172 *0_8
15 16 R237 *0/short_4
GND UIM_VPP LPCFRAME# [11,22]
13 14 C310 C311 C164
[2] PE2CLK+ REFCLK+ UIM_RESET LPCAD3 [11,22]
[2] PE2CLK- 11 12 LPCAD2 [11,22]
REFCLK- UIM_CLK *1000p/50V_4 *0.1u/10V_4 *10u/10V_8
9 10 LPCAD1 [11,22]
CLKREQ_WLAN# GND UIM_DATA +3V_Mini1_VDD
[2] CLKREQ_WLAN# 7 8 LPCAD0 [11,22]
CLKREQ# UIM_PWR
5 6
Reserved +1.5V Q17
3 4
GND
GND
Reserved GND
2
1 2 *2N7002E
WAKE# +3.3V
Q20 MINI-CARD1 3 1 WL_SMCLK
[2,3] SMBCK1
53
54
3 1 MINI1_WAKE#
[11,18] PCIE_WAKE#
+3V_Mini1_VDD *2N7002E R227 *0/short_4
3G sku: stuff R362, Q12, don't stuff R386
2
R373 *10K_4
W/O 3G sku: don't stuff R362,Q12, stuff R386
C C
Mini Card 2 / GPS(MNC) 1.1A

+3VSUS +3V_Mini2_VDD
+1.5V_Mini2_VDD R143 *3G@0_8
1
+3V_Mini2_VDD +3V_Mini2_VDD C143 C302 C303 C305 C319 C320 C301
+3V_Mini2_VDD
CN17 +3V *3G@4.7u/10V_8 *3G@0.1u/10V_4 *3G@0.1u/10V_4 *3G@0.1u/10V_4 *3G@0.1u/10V_4*3G@0.47u/6.3V_4 *3G@10p/50V_4
2
51 52
Reserved +3.3V R362 R173 *3G@0_8
49 50
Reserved GND
47 48
3G_WAKE_R Reserved +1.5V *3G@100K/F_4
T47 45 46
Reserved LED_WPAN# WLAN_LED#_R
43 44
GND LED_WLAN# 3G_MINI_LED#
41 42 3G_MINI_LED# [15] 0.5A
+3.3Vaux LED_WWAN# +1.5V
39 40
+3.3Vaux GND USBP5+_R +1.5V_Mini2_VDD +3V_Mini2_VDD
37 38
GND USB_D+ USBP5-_R
35 36
GND USB_D- R134 *3G@0_8
[8] PE4TX+ 33 34
PETp0 GND 3G_SMDATA
[8] PE4TX- 31 32
PETn0 SMB_DATA 3G_SMCLK C304 C318
29 30
GND SMB_CLK
27 28
GND +1.5V *3G@1000p/50V_4 *3G@0.1u/10V_4 +3V_Mini2_VDD
[8] PE4RX+ 25 26
PERp0 GND R154 R166
[8] PE4RX- 23 24
PERn0 +3.3Vaux PLTRST#_1 R364 *3G@0_4 PLTRST# Q11
21 22
GND PERST# *3G@10K_4 *3G@10K_4
19 20 3G_EN [22]
UIM_C4 W_DISABLE#
2
17 18 *3G@2N7002E
B UIM_C8 GND B
15 16 UIM_VPP PDAT_SMB 3 1 3G_SMDATA

GND UIM_VPP UIM_RST [2,11] PDAT_SMB
[2] PE4CLK+ 13 14
REFCLK+ UIM_RST UIM_CLK
[2] PE4CLK- 11 12
REFCLK- UIM_CLK UIM_DATA R145 *3G@0_4
9 10
CLKREQ_3G# GND UIM_DATA UIM_PWR R156 *3G@0_4
T48 7 8
CLKREQ# UIM_PWR
5 6
Reserved +1.5V USBP5+_R
3 4
GND
GND
Reserved GND USBP5+ [8]

T23 3G_WAKE_2_R 1 2 USBP5-_R USBP5- [8]
WAKE# +3.3V
*3G@MINI-CARD2 +3V_Mini2_VDD
53
54
R150 *3G@0_4
Q13
2
*3G@2N7002E
+3V
PCLK_SMB 3 1 3G_SMCLK
ESD1 [2,11] PCLK_SMB
SIM UIM_RST 1
2
CH1 CH4
6
5
UIM_VPP
R167 *3G@0_4
VN VP
Max: 7.5mA (Option) UIM_CLK 3 4 UIM_DATA
CH2 CH3
JSIM1 *3G@CM1293-04SO
UIM_CLK 6 1 UIM_PWR C227 *3G@27p/50V_4
USBP4-_R CLK(C3) GND(C5) UIM_PWR
7 2
R14 *3G@0_4 USBP4+_R D-(C8) VCC(C1) UIM_VPP
8 3
D+(C4) VPP(C6) UIM_RST UIM_DATA C221 *3G@10p/50V_4 <20090604(A1A)_Qualcomm design guide>
9 4
CT RST(C2) UIM_DATA Place 0.1uF near connector's VCC pin
A 10 5 A
USBP4+_R CD DATA(C7) UIM_PWR
GND
GND
GND
GND
[8] USBP4+
USBP4-_R UIM_CLK C231 *3G@10p/50V_4
[8] USBP4-
*3G@SIM-Conn
13
11
12
14
2
R11 *3G@0_4 UIM_RST C222 *3G@27p/50V_4 C225 C226
*3G@1u/10V_6
*3G@0.1u/10V_4 Quanta Computer Inc.
1
UIM_VPP C219 *3G@33p/50V_4
PROJECT : ZE6
1B
Mini-Card/WL/3G/SIM
5 4 3 2 1
5 4 3 2 1
for EMI issue: change R232,R233,R234,

RTS5209 +3V3_IN
R235,R236,R231,R211 to 33 ohm.
VCC_XD
CN18
R195 VCC_XD
*100K_4 13
SD_CD# SD-VCC
1 SD-CD-SW
SD_WP/XD_D7 2 45
[4,11,18,20,22,23] PLTRST# SD_D1 R232 33/J_4 SD_D1_R SD-WP-SW XD-VCC
3 SD-DAT1
SD_D0 R233 33/J_4 SD_D0_R 4
C184 SD_CLK R234 33/J_4 SD_CLK_R SD-DAT0 XD_CD#
10 SD-CLK XD-CD 28
*1U/6.3V_4X SD_CMD R235 33/J_4 SD_CMD_R 19 29 SD_D7/XD_RDY
SD_D3 R236 33/J_4 SD_D3_R SD-CMD XD-R/B SD_D6/XD_RE#
23 30
SD_D2 R231 33/J_4 SD_D2_R SD-DATA3 XD-RE SD_D5/XD_CE#
25 SD-DAT2 XD-CE 31
SD_D7/XD_RDY 5 32 MS_BS/XD_CLE
D
SD_D6/XD_RE# MMC-DATA7 XD-CLE MS_D5/XD_ALE D
8 33
SD_D5/XD_CE# MMC-DATA6 XD-ALE SD_D4/XD_WE#
17 34
SD_D4/XD_WE# MMC-DATA5 XD-WE MS_D1/XD_WP#
21 35
MMC-DATA4 XD-WP
[2] CLKREQ_CARD#
7
SD-GND1 MS_D4/XD_D0
15 37
+3V3_IN SD-GND2 XD-D0 MS_D0/XD_D1
26 SD-WP-GND XD-D1 38
TP5
TP6
TP7
27 39 MS_D2/XD_D2
C180 0.1U/10V_4X SD-CD-GND XD-D2 MS_D6/XD_D3
XD-D3 40
22 41 MS_D3/XD_D4
MS_BS/XD_CLE MS-VCC XD-D4 MS_D7/XD_D5
9 MS-BS XD-D5 42
CLKREQ_CARD#
R194 6.2K/F_4 MS_D1/XD_WP# 11 43 XD_D6
SD_WP/XD_D7
XD_D6 MS_D0/XD_D1 MS-DATA1 XD-D6 SD_WP/XD_D7
C196 12 44
MS_D2/XD_D2 MS-DATA0 XD-D7
14
CARDREF
MS-DATA2
PLTRST#
MS_INS#
R221 *0/short_4 MS_CLK MS_INS# 16
SD_CD#
MS-INS
XD_D6
MS_D3/XD_D4 18
EEDO
EECS
EESK
MS_CLK R211 33/J_4 MS_CLK_R MS-DATA3
10P/50V_4 20 MS-SCLK XD-GND1 36
46
XD-GND2
6 MS-GND1 XD-GND3 47
48
47
46
45
44
43
42
41
40
39
38
37
24 MS-GND2
U11 add C196 for EMI.
3V3_IN
GPIO/EEDI
EECS
EESK
RREF
CLK_REQ#
PERST#
EEDO
MS_INS#
SD_CD#
SP15
SP14
CM7R-052-H-D
12/06 change connector pin define and footprint

Main:DFHS44FR015
[8] PE3TX+ 1 36 MS_D7/XD_D5

HSIP SP13
Zdiff = 100 ohm [8] PE3TX- 2 35 MS_D3/XD_D4
HSIN SP12
[2] CLK_CARDREADER 3 34 MS_D6/XD_D3
REFCLKP SP11
Zdiff = 100 ohm [2] CLK_CARDREADER# 4 33 MS_D2/XD_D2
REFCLKN SP10
C C
C197 4.7U/6.3V_6X AV12 5 32 MS_D0/XD_D1
AV12 SP9
[8] PE3RX+ C198 0.1U/10V_4X PCIE_RXP2_R 6 31 MS_D4/XD_D0
HSOP SP8
Zdiff = 100 ohm
[8] PE3RX- C199 0.1U/10V_4X PCIE_RXN2_R 7
GND
HSON RTS5209-GR SP7
30 MS_D1/XD_WP#
MS_D5/XD_ALE VCC_XD
8 GND SP6 29
C203 4.7U/6.3V_6X
C200 0.1U/10V_4X DV12 9 28 MS_BS/XD_CLE
DV12 SP5 C315 C306 C208
VCC_XD 10 27 DV12_S C202 0.1U/10V_4X C316
Card1_3V3 DV12_S 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 4.7U/10V/8
+3V R230 *0/short_6 +3V3_IN 11 26 GND
3V3_IN GND
TP8 12 25 SD_D2
Card2_3V3 SD_D2
C204 C201
4.7U/10V/8 0.1U/10V_4X
DV33_18
SD_CMD
XD_CD#
SD_CLK
SD_D1
SD_D0
SD_D3
GND
SP1
SP2
SP3
SP4
13
14
15
SD_D7/XD_RDY 16
SD_D6/XD_RE# 17
SD_D5/XD_CE# 18
SD_D4/XD_WE# 19
20
21
22
23
24
AV12 L23 *PBY160808T-601Y-N_1A DV12
XD_CD#
DV33_18
GND
SD_CMD
SD_CLK
SD_D1
SD_D0
SD_D3
B B
add C206 for EMI and close to chip pin

C207 C205
*4.7U/6.3V_6X 0.1U/10V_4X
C206
SD_CLK_R
10P/50V_4
A A

PROJECT : ZE6
1A
RTS5138
5 4 3 2 1
5 4 3 2 1
I/O ADDRESS SETTING(KBC)

EC (KBC)
SHBM=0: Enable shared memory with host BIOS
L1 PBY160808T-250Y-N/3A/25ohm_6 30mil +A3VPCU
C7 C6 R250 *0/J_6
+3V SHBM 3G_EN R22 10K_4
.1U/10V_4 4.7U/6.3V_6 10mA D26
<Layout note> +3V_VDD_EC 1 2
+3VPCU E791AGND 1/13 Comfirm by vendor mail :
E791AGND Place every 0.1uF
R249 2.2/J_6 BAS316
1 2 +3VPCU_EC 0.03A (30mils) close to every C217 C218 <20090602(A1A)_Vendor suggest> Disabled ('1') if using FWH device on LPC.
Place 10nF-0.1uF capacitors for Enabled ('0') if using SPI flash for both system BIOS and EC firmware
C212 C3 C14 C13 C220 C1 power pin .1U/10V_4 4.7U/6.3V_6 every AD input. And close to the AD
115
102
D input. D
19
46
76
88
4
4.7U/6.3V_6 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 U1
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
+3VPCU
E791AGND C9 .01U/16V_4
3 97 BATLED0# R17 100K/J_4

[11,20] LPCFRAME# LFRAME GPIO90/AD0 TEMP_MBAT [24]
126 98 BATLED1# R29 100K/J_4
[11,20] LPCAD0 LAD0 GPIO91/AD1
[11,20] LPCAD1 127
LAD1 A/D GPIO92/AD2
99
128 100 ICMNT_EC R258 *0/short_4
[11,20] LPCAD2 LAD2 GPIO93/AD3 ICMNT [24]
[11,20] LPCAD3 1
LAD3
<20090831(A1A)_EC team suggest>
LCLK_EC 2 E791AGND C234 3300P/50V_4 1.change R7027/R7028 to 1M or 100K ohm
[2] LCLK_EC LCLK
101 2.change PWR/SUS LED's power from +3VPCU to +3V_S5 or +3VSUS
GPIO94/DA0
[11] CLKRUN# 8
GPIO11/CLKRUN D/A GPI95/DA1
105
can reduce pull-high resistor of SUSLED#/PWRLED#
106
GPI96/DA2
[9] GA20 121
GPIO85/GA20
[9] KBRST# 122

KBRST/GPIO86
64 ACIN [24]
GPIO01/TB2
29 LPC 79
[10] EC_SCI# ECSCI/GPIO54 GPIO02
GPIO03
95
R24 *0/J_4
NBSWON# [15,23] SM BUS PU(KBC) +3VPCU
[14] EC_FPBACK# 6 96 USBOC#R [8,17]
GPIO24/LDRQ GPIO04 R10 *0/J_4 MBCLK R20 4.7K/J_4
108 USBOC#L [8,17]
GPIO05 MBDATA R19 4.7K/J_4
[16] AMP_MUTE# 124 93 LID# [14]
GPIO10/LPCPD GPIO06/IOX_DOUT/RTS1
94
GPIO07
[4,11,18,20,21,23] PLTRST# 7 114 CHARGE_IC_ON [17]
LREST GPIO16 +3V
109
GPIO30
[20] RF_EN 123 15 T3
GPIO67/PWUREQ GPIO36/CTS1
80 VRON [23,26]
GPIO41 HWPG 2ND_MBCLK R264 10K_4
[9] SERIRQ 125 17
SERIRQ GPIO42/SCL3B/TCK THERM_ALERT#_1 R5 *0/J_4 2ND_MBDATA R263 10K_4
20 THERM_ALERT# [4,11]
GPIO43/SDA3B/TMS
[11] EC_SMI# 9 21 SUSB# [11]
GPIO65/SMI GPIO44/TDI
GPIO GPO47/SCL4
24 USB_CHARGE_ON [17]
25 D/C# [24]
MX0 GPIO50/PSCLK3/TDO S5_ON
[15] MX0 54 26 S5_ON [23,25,30]
MX1 KBSIN0 GPIO51 HDMI_IN
55 27
C
[15]
[15]
MX1
MX2
MX2
MX3
56
KBSIN1
KBSIN2
GPIO52/PSDAT3/RDY
GPIO53/SDA4
28
T1
SPI FLASH(KBC) C
[15] MX3 57 73 SUSC# [11]
MX4 KBSIN3 GPIO70 PWROK_EC_uR R25 *0/short_4
[15] MX4 58 74 ECPWROK [11,23]
MX5 KBSIN4 GPIO71 RSMRST#_uR R26 *0/short_4 +3VPCU
[15] MX5 59 75 EC_RSMRST# [11,23]
MX6 KBSIN5 GPIO72
[15] MX6 60 82 MAINON [23,27,28,29]
MX7 KBSIN6 GPIO75/SPI_SCK U12
[15] MX7 61 83 3G_EN [20]
KBSIN7 GPO76/SHBM SPI_SDI_uR R245 22_4 SPI_SDI_uR_R
<EMI> GPIO77
84 T25 2
SO VDD
8
MY0 53 91 D37 BAS316
[15] MY0 KBSOUT0/JENK GPIO81 DNBSWON# [11,23]
LCLK_EC MY1 52 110 SPI_SDO_uR_R 5 7 HOLD# R241
[15] MY1 KBSOUT1/TCK GPO82/IOX_LDSH/TEST SI HOLD
MY2 51 112 3.3K_4 C211
[15] MY2 KBSOUT2/TMS GPO84/IOX_SCLK/XORTR USB_EN# [17]
MY3 50 107 SPI_SCK_uR_R 6 3
[15] MY3 KBSOUT3/TDI GPIO97 SCK WP
MY4 49 KB .1u/10V_4
[15] MY4 KBSOUT4/JEN0
R4 MY5 48 +3VPCU R246 10K_4 SPI_CS0#_uR 1 4
[15] MY5 KBSOUT5/TDO CE VSS
MY6 47 31
[15] MY6 KBSOUT6/RDY GPIO56/TA1
*22/J_4 MY7 43 117 MX25L1606EM2I-12G
[15] MY7 KBSOUT7 GPIO20/TA2/IOX_DIN_DIO SUSON [5,23,27,29]
MY8 42 63
[15] MY8 KBSOUT8 GPIO14/TB1 FAN_SIG [4]
MY9 41
[15] MY9 KBSOUT9/SDP_VIS
MY10 40 TIMER 32 Winbond W25Q16CVSSIG AKE38ZP0N02
[15] MY10 KBSOUT10/P80_CLK GPIO15/A_PWM CONTRAST [14]
C2 MY11 39 118 EON EN25F40-100HIP AKE38ZA0Q00
[15] MY11 KBSOUT11/P80_DAT GPIO21/B_PWM PCBEEP [16]
*10P/50V_4 MY12 38 62 MXIC MX25L1606EM2I-12G AKE38FP0Z01
[15] MY12 KBSOUT12/GPIO64 GPIO13/C_PWM PWRLED# [15]
MY13 37 65
[15] MY13 KBSOUT13/GPIO63 GPIO32/D_PWM BATLED0# [15]
MY14 36 22
[15] MY14 KBSOUT14/GPIO62 GPIO45/E_PWM CPUFAN# [4]
MY15 35 16
[15] MY15 KBSOUT15/GPIO61/XOR_OUT GPIO40/F_PWM/RI1 SUSLED# [15]
34 81
GPIO60/KBSOUT16 GPIO66/G_PWM
33 66 BATLED1# [15]
GPIO57/KBSOUT17 GPIO33/H_PWM/SOUT1
1/13 Comfirm by vendor mail :
MBCLK 70
[24] MBCLK
MBDATA GPIO17/SCL1 If the Southbridge enables 'Long Wait Abort' by
[24] MBDATA 69
2ND_MBCLK GPIO22/SDA1 <20090721_FAE suggestion> default, the flash device should be 50MHz (or faster)
[4] 2ND_MBCLK 67
GPIO73/SCL2 SMB GPIO87/CIRRXM/SIN_CR
113
Stuff 100K and close to EC side
FOR CPU Thermal Sensor 2ND_MBDATA 68 14
[4] 2ND_MBDATA GPIO74/SDA2 GPIO34/SIN1/CIRRXL for improving power consumption
T4 119
GPIO23/SCL3 IR GPIO46/CIRRXM/TRST
23
FOR VGA T5 120
GPIO31/SDA3 GPO83/SOUT_CR/TRIST
111 T24
[15] TPCLK TPCLK 72 86 SPI_SDI_uR SPI_SDI_uR

TPDATA GPIO37/PSCLK1 F_SDI/F_SDIO1 SPI_SDO_uR R248 22/J_4 SPI_SDO_uR_R +3V
71 87
B [15] TPDATA
10
GPIO35/PSDAT1
GPIO26/PSCLK2 PS/2 FIU
F_SDO/F_SDIO0
F_CS0
90 SPI_CS0#_uR
SPI_SCK_uR R247 22/J_4 SPI_SCK_uR_R
HWPG B
[15,20] BT_POWERON# 11 92
GPIO27PSDAT2 F_SCK R244 R2
[11] SUSCLK R21 *0/short_4
E775_32KX1 77 30 ECDB_CLOCK T2
GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN_DIO 100K/J_4
85 VCC_POR# R23 47K/J_4 +3VPCU 10K_4
R3 *0/short_4 VCC_POR
12
VCORF
VTT
AGND
GND1
GND2
GND3
GND4
GND5
GND6
13 104 VREF_uR R12 *0/short_4 +A3VPCU D27 BAS316 R1

PECI VREF [23,29] HWPG_VCCGFX HWPG [11,23]
*0/short_4
If PECI 3.0 access functionality is not used, D29 *BAS316
[5,23,27] HWPG_1.5V
connect VTT pin to GND. NPCE791L
5
18
45
78
89
116
103
VCORF_uR 44
D23 *BAS316
[23,28,29] HWPG_1.05V
D24 *BAS316
[29] HWPG_1.8V
L3 D25 *BAS316
[25] SYS_HWPG
PBY160808T-250Y-N/3A/25ohm_6
C4
1U/6.3V_4
E791AGND E791AGND
INTERNAL KEYBOARD STRIP SET (KBC) INTERNAL KEYBOARD STRIP SET(KBC)

A 10/26 UnStuff +3VPCU A
SM BUS ARRANGEMENT TABLE
+3VPCU MY0 R253 *10K_4
RP2 10K/J_10P8R SM Bus 1 Battery
10 1 MX3
MX4 9 2 MX2
MX5 8 3 MX1 SM Bus 2 CPU thermal sensor
MX6 7 4 MX0
MX7 6 5
+3VPCU
PROJECT : ZE6
1A
WPCE781 & FLASH
5 4 3 2 1
5 4 3 2 1
EMI Hole Power Sequence Connector 30pin (CPU)
HOLE5 HOLE8 HOLE12 HOLE15 HOLE13

2 5 2 5 2 5 2 5 2 5
3 6 3 6 3 6 3 6 3 6
D 4 7 4 7 4 7 4 7 4 7 D
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
CN15
*HG-C276D98P2 *HG-C276D98P2 *HG-C276D98P2 *HG-C276D98P2 *HG-C276D98P2 NBSWON# 2 1

[15,22] NBSWON#
+3V_S5 +3V_S5 4 3 S5_ON
S5_ON [22,25,30]
EC_RSMRST# 6 5 +5V_S5 +5V_S5
[11,22] EC_RSMRST#
SUSON 8 7 DNBSWON#
[5,22,27,29] SUSON DNBSWON# [11,22]
HOLE9 HOLE14 HOLE16 HOLE4 HOLE10 +1.5VSUS +1.5VSUS 10 9 +3VSUS +3VSUS
2 5 2 5 2 5 2 5 2 5 MAINON 12 11 HWPG_1.5V
[22,27,28,29] MAINON HWPG_1.5V [5,22,27]
3 6 3 6 3 6 3 6 3 6 +5V +5V 14 13 +3V +3V
4 7 4 7 4 7 4 7 4 7 +1.5V +1.5V 16 15 +1.05V +1.05V
+1.8V +1.8V 18 17 HWPG_1.05V
HWPG_1.05V [22,28,29]
HWPG_VCCGFX 20 19 VCCGFX VCCGFX
[22,29] HWPG_VCCGFX
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
VRON 22 21 HWPG
[22,26] VRON HWPG [11,22]
VR_PWRGD_CK410# 24 23 VCORE VCORE
[2,26] VR_PWRGD_CK410#
[11,22] ECPWROK ECPWROK 26 25 IMVP_PWRGD
IMVP_PWRGD [4,11,26]
PLTRST# 28 27 TPT_PWROK
[4,11,18,20,21,22] PLTRST# TPT_PWROK [11]
*hg-tc276bc256d98p2 *HG-C276D98P2 *HG-C276D98P2 *HG-C276D98P2 *HG-TC276BC315D98P2 30 29 PLTRST#
PLTRST# [4,11,18,20,21,22]
*30pin POWER SEQ CONN

C HOLE7 HOLE2 HOLE3 C
2 5 2 5 2 5 HOLE19 HOLE20
3 6 3 6 3 6 h-c197d63p2 *3G@h-c197d63p2
4 7 4 7 4 7
8
1
9
8
1
9
8
1
9
1
*HG-TC276BC315D98P2 *HG-TC276BC315D98P2 *HG-TC276BC315D98P2
1 GND 11 HWPG_1.5V 21 HWPG
2 NBSWON# 12 MAINON 22 VRON
HOLE21 HOLE18 HOLE17 HOLE1 HOLE6
*3G@h-c197d63p2 h-tc177bc295d126p2 h-tc177bc295d126p2 *hg-c276do94x106p2 *O-ZE6-2 3 S5_ON 13 +3V 23 VCORE
2 5
3 6 4 +3V_S5 14 +5V 24 VR_PWRGD_CK410#
4 7
5 +5V_S5 15 +1.05V 25 IMVP_PWRGD
8
1
9
1
6 EC_RSMRST# 16 +1.5V 26 ECPWROK
7 DNBSWON# 17 HWPG_1.05V 27 TPT_PWROK
B 8 SUSON 18 +1.8V 28 H_PWRGD B
9 +3VSUS 19 VCCGFX 29 PLTRST#

HOLE11
*O-ZE6-3 PAD1 10 +1.5VSUS 20 HWPG_VCCGFX 30 RESERVE
1
A A

PROJECT : ZE6
1A
HDMI(1/2)
5 4 3 2 1
5 4 3 2 1
POWER_JACK
dcjk-2dc2003-000111-3p-v
VA1 PD9
PQ33
AO4427
PR116
0.01_0612
PQ35
AO4427
30
PJ1 PL3 SBR1045SP5-13 VIN
1 HI0805R800R-00/5A/80ohm_8 1 1 8 1 8
2 VA 3 VA2 2 7 1 2 2 7
2 3 6 3 6
3 5 5
PC64 PC63 PR102 CSIP_1 VIN_SRC PC80 PC79

7
6
5
4
4
0.1u/50V_6 0.1u/50V_6 220K/F_6 0.1u/50V_6 2200p/50V_4 PR6
PC66 33K_6
1
2200p/50V_6
D PD10 D
PC65 SMAJ20A
0.1u/50V_6 1 6 PR7
PD8 10K_6
2
SW1010CPT PR101 2 5 1 2 D/C# [22]
220K/F_6
3 4 PR103
3
*0/short_4
PQ34
IMD2AT108
VIN_SRC 2
PQ1
CSIP_1 DMN601K-7
1
VIN
PC71
1u/10V_4
PR106 PR108
10/F_6 10/F_6
PC6
PR4 2200p/50V_4
PC67 4.7_6 PC78
0.1u/25V_4 1u/10V_4
ISL88731_VDDP
CSIP CSIN PC7 PC76
0.1u/50V_6 4.7u/25V_8
33
32
31
30
28
27
26
21
C C
5
+3VPCU PD11
*RB500V-40
NC
GND
GND
GND
GND
CSSN
VCC
CSSP
VDDP
PC73 PC74
+3VPCU PR113
1u/10V_4 0.1u/50V_6 4
2.7_6
11 88731B_2
25 88731B_1
VDDSMB BOOT PQ2
AON7410 PR115
3
2
1
MBDATA 9 24 ISL88731_UGATE 0.01_0612
PR2 SDA UGATE PL6
100K/F_4 6.8uH_7X7X3
MBCLK 10 23 ISL88731_PHASE 1 2 BAT-V
SCL PHASE
5
13 20 ISL88731_LGATE PR3
[22] ACIN ACOK LGATE 2.2/F_4 PC11
0.01u/25V_4
PR5 PC75 PU7 19 4
49.9/F_4 0.1u/25V_4 ISL88731C PGND
DCIN 22 PQ43 PC10
DCIN PR121 AON7410 2200p/50V_4
3
2
1
PR105 10/F_6 PC5
82.5K/F_4 18 CSOP CSOP_1 2200p/50V_4 PC9
88731ACSET CSOP 10u/25V_1206
2
ACIN PC77 PC8
+3VPCU 0.1u/25V_4 10u/25V_1206
PR1 3
22K/F_4 VREF
B CSON 17 CSON BAT-V B
PR117
HI0805R800R-00/5A/80ohm_8 4 *0/short_4 PR120 CSOP_1
PR112 PL4 ICOMP 10/F_6
NC 16
100K_4
5 PR114
HI0805R800R-00/5A/80ohm_8 NC 100_4
PL5 15 BAT-V BAT-V
10 1 MBAT+ BAT-V VBF
6
2 PR107 100_4 VCOMP
29
3 TEMP_MBAT_C GND
GND
4 TEMP_MBAT [22]
ICM
NC
NC
5
6 PR104
7
14
12
7 2.21K/F_4
9 8 PC68 PC72
PJ2 0.1u/25V_4 100p/50V_4
bat-btj-08tc0b-8p-l-v PC69 PC70
Batt_Conn 47p/50V_4 PC1 PC4
*1u/10V_4 0.01u/25V_4
ISL88731 thermal pad
47p/50V_4 ICMNT
tie to Pin12
ICMNT [22]
PR111
*0/short_4
PR109 PR110 PC2 PC3

100_4 100_4 0.01u/25V_4 *0.01u/25V_4
PU6
*CM1293A-04SO
A MBDATA A
1 6
MBCLK [22] CH1 CH4
2 5 +3VPCU
VN VP
MBDATA [22] TEMP_MBAT 3 4 MBCLK
CH2 CH3
Add ESD diode base on EC FAE suggestion

PROJECT : ZE6
1A
CHARGER (ISL88731)
5 4 3 2 1
5 4 3 2 1
MAIND SYS_SHDN#
MAIND [27,29] SYS_SHDN# [4,26,30]
SUSD
SUSD [29]
Ven=7.23V
TP14 TP13 TP16 TP15
[22] SYS_HWPG VIN VIN VL 8223REF +3VPCU

+3VPCU
VIN VIN
D VIN D
PR165
4.7u/6.3V_6
4.7u/6.3V_6
PR164 10_8
665K/F_4 PC124
1
1u/6.3V_4
+ PR166
*0_4
8223_VIN
8223_EN
2 PC119 PC120 PC121 PC122 PC125 PC126
PC127
PC123
*100u/25V_6X5.8 4.7u/25V_8 2200p/50V_6 PR168 0.1u/25V_4 2200p/50V_6 4.7u/25V_8
*0/short_4
PR169 PR167
+5VPCU PR170 PR171 PR172 *0_4 *0/short_4
5
100K/F_4 330K/F_4 *0/short_4 +3VPCU
TP9 +3VPCU
16
17
TP10
3
PQ45
+5VPCU AON7410
3.3Volt +/- 5%
VREG3
VREG5
VIN
REF
5 Volt +/- 5% PQ44 4 SYS_SHDN# 13 14 +3V_SKIP
4 TDC : 3A
EN SKIPSEL
TDC : 4.7A AON7410
+3V_PG +3V_TON
PEAK : 4A
23 4
3
2
1
PGOOD TONSEL
TP11 PEAK : 6.2A OCP : 5A
1
2
3
+5V_DH 21 10 +3V_DH PC129
TP12
OCP : 7A UGATE1 UGATE2 0.1u/50V_6 Width : 120mil
PL10 PC128 PR173 +5V_B 22 9 +3V_B PR174 PL11
Width : 180mil 2.2uH_7X7X3 0.1u/50V_6 1/F_6 BOOT1 PU3 BOOT2 1/F_6 2.2uH_7X7X3
+5VPCU +5V_LX 20 RT8223M 11 +3V_LX +3VPCU
PHASE1 PHASE2
+5V_DL 19 12 +3V_DL
5
LGATE1 LGATE2
5
C PR175 +5VPCU 24 7 +3VPCU C
ENTRIP1
ENTRIP2
15.4K/F_4 VOUT1 OUT2 PR176 PR178
PQ46 +5V_FB 2 5 +3V_FB *4.7_6 6.81K/F_4
GND
GND
ENC
+ PR177 AON7702 FB1 FB2
4 +
*4.7_6 4
PC117 PC130 PC131
18
25
15
220u/6.3V_6X4.2 0.1u/50V_6 1 PR180 0.1u/50V_6
2
3
*Short_4 PQ47 PC132
3
2
1
8223_EN AON7702 *680p/50V_6
PR179 PC133
2
10K/F_4 *680p/50V_6
PR181 PC134
100K/F_4 0.1u/10V_4 PR184
10K/F_4
1
PR183
PR182 56.2K/F_4 PC118
80.6K/F_4 220u/6.3V_6X4.2
+5V_DL
OCP:5A
PC135 PR185 L(ripple current)
2 0.1u/50V_6 *0_6
OCP:7A PD12 +3V_DL PR186 =(9-3.3)*3.3/(2.2u*0.5M*9)
CHN217 3 *0/short_6
L(ripple current) PR187
~1.9A
=(9-5)*5/(2.2u*0.4M*9) 1 *0/short_6 PR188
PC137 *0/short_6
Iocp=5-(1.9/2)=4.05A
B =2.525A 0.1u/50V_6 Vth=4.05A*14mOhm=56.7mV B
2
Iocp=7-(2.525/2)=5.74A PD13
R(Ilim)=(56.7mV*10)/10uA
Vth=5.74A*14mOhm=80mV 3
CHN217 ~56.7K
PC136
R(Ilim)=(80mV*10)/10uA 1 0.1u/50V_6
~80.323K
+15V_ALWP
+15V
PR189
22_8
PC138
0.1u/50V_6
+3VPCU
VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU +3VPCU
+3VPCU
TDC : 1.32A
3
PR190 PR191 PR192 PR193 PR194
1M_6 22_8 22_8 1M_6 *1M_6 PEAK : 1.76A
3
3
SUSD 2 Width : 60mil
S5D 2 MAIND 2 MAIND 2 S5D 2
TDC : 0.148A
PEAK : 0.2A PQ24
3
A AO3404 A
1
2
PQ32
AO3404
PQ19
AO3404
PQ26
AO3404
PQ25
AO3404
Width : 10mil
2,23,30] S5_ON +3VSUS
1
1
2 2 2
+3V_S5
PR195 PQ49 PQ50
1
PQ48 1M_6 DMN601K-7 DMN601K-7

DTC144EU PQ51 PC139
+5V_S5 +5V +3V
1
DMN601K-7 1000p/50V_4
TDC : 0.008A TDC : 1.627A TDC : 1.496A PROJECT : ZE6
PEAK : 0.01A PEAK : 2.2A PEAK : 2A 1A
SYSTEM 5V/3V (RT8223M)
Width : 10mil Width : 70mil Width : 60mil Date: Friday, March 11, 2011 Sheet 25 of 35
5 4 3 2 1
5 4 3 2 1
12/10 : PR141 need to add after thermal final tune.
+1.05V PR8 *68/F_4

PR136 *0_8
PR9 *0_4 TP2 TP1 VID0
[4] H_PROCHOT# +5V
PR141 *0_4 PR25 *0_8
[4,25,30] SYS_SHDN#
VID1
PR118 PR12 PR139 *0_8

VIN
D 60.4K/F_4 10K/F_4 VID2 D
1
1
1 2 + PR135 *0_8
VID3
8796VCC PR123 PC82 PC14 PC90 +3VPCU
2
2.2_6 0.22u/25V_6 4.7u/25V_8 100u/25V_6X5.8 PR128 *0_8
PC81 VID4
12.7K/F_4
PR119
1u/10V_4
+5V PC13 PR127 *0_8
8796DH 2200p/50V_6 VID5
PR11 +3VPCU
PQ36 PR124 *0_8
AOL1448 VID6
5
10/F_6
PC85
VID 1.0V
23
31
30
29
28
27
24
26
25
1u/10V_4 4
TIME
LX
VDD
VCC
ILIM
VRHOT
PGDIN
BST
DH
1
2
3
[4] VID6 20
D6
19 TP3 TP4
[4] VID5 D5
18
[4] VID4 D4 DCR=3m
PL7
[4] VID3 17
D3 1uH
OCP:14A
C C
16 8796LX VCORE
[4] VID2 D2
15 22 8796DL PR18 PR17
[4] VID1 D1 DL 1.8K/F_4 *0/short_4
14 PC89 1000p/50V_4
[4] VID0 D0 PR122
5 PQ37 PR16 10K_6_NTC
PR22 *0/short_4 6 CSP AOL1718
[4,11] ICH_DPRSTP#
5
DPRSTP PC87 + +
PU8 0.22u/6.3V_4 PR24 2.74K/F_4
PR23 499/F_4 7 *4.7_6 PR15
[4,11] PM_DPRSLPVR
2
DPRSLPVR 10K/F_4 PC92 PC17
MAX8796GTJ+ 4 4
CSN
PC16
330u/2V_7343 330u/2V_7343
PC88 1000p/50V_4
1
2
3
PC84
2 1 PC15
2200p/50V_4
0.1u/50V_6 PR125 *680p/50V_6
PR126 2.7K/F_4
PWR 1
PWR
*2.7K/F_4 ESR=9m
PR20 8796CSP
8796VCC 8796THRM 8 3
THRM FB 8796CSN
13K/F_4 2
GNDS
PWRGD
PR140
CLKEN
PGND
AGND
SHDN
*100K/F_4_NTC PR19
V3P3
Load-line=-5.9mV/A
CCV
TON
B B
4.02K/F_4
for Pine Trial-M
9
10
11
12
13
32
21
33
PC12 1000p/50V_4
tSW = 16.3pF x (RTON + 6.5K ) PR130
200K/F_4 FB_SRC PR21 10/F_4
VCC_SENSE [6]
fsw=300KHz VIN
GNDS PR14 10/F_4
VSS_SENSE [6]
+3V PR137 1K/J_4 PC83
100p/50V_4 PC86 1000p/50V_4
PR131 *0/short_4
[4,11,23] IMVP_PWRGD
PR132 *0/short_4
[22,23] VRON
PR129 *0/short_8
PR138 10K/F_4 FB_SRC PR13 *10/F_4 VCORE
PR134
PR133 *0/short_4 *0/short_4 PR146 *0/short_8 GNDS PR10 *10/F_4
[2,23] VR_PWRGD_CK410#
C187
+3V Connect to output cap GND
*.1U/10V_4
PC91
A *470p/50V_4 A

PROJECT : ZE6
1A
VCore( IMAX8796GTJ+)
5 4 3 2 1
5 4 3 2 1
33
[PWM]
PC26
10u/6.3V_8
30mil
PR45 PC27
0.75A *0/short_6 0.1u/50V_6
8207A_VBST
+0.75V_DDR_VTT
D VIN D
8207A_DH
5
8207A_LX
8207A_DL PC93
PC23 PC22 4.7u/25V_8
10u/6.3V_8 10u/6.3V_8 4
PQ39
25
24
23
22
21
20
19
AON7410 PC96 PC94 PC28
3
2
1
0.1uF/50V_6 2200p/50V_6 4.7u/25V_8
LL
DRVL
GND
VTT
VLDOIN
VBST
DRVH
PL8 add for EMI
2.2uH
1 18 +1.5VSUS +1.5VSUS
VTTGND PGND
2
VTTSNS CS_GND
17
+1.5VSUS
5
3 16
1.5 Volt +/- 5%
GND CS
PU1
RT8207L PR36
PR48
2.2/F_4
TDC : 7A
15mil +1.5VSUS 4 15 13K/F_4 4 PEAK : 9A
MODE V5IN +5V_S5
+
0.375A PQ38 OCP : 10A
5 14 PR33 AON7702
+SMDDR_VREF
3
2
1
VTTREF
VDDQSNS
V5FILT 5.1/F_6 Width : 280mil
VDDQSET
+5V_S5 6 13 PC19 PC20 PC29
C
COMP PGOOD 1000p/50V_4 PC101 PC35 PC32 C
1u/10V_4 1u/10V_4
330u/2V_7343 10u/6.3V_8 1000pF/50V_4
NC
NC
S3
S5
PC21 PR29 +3V_S5
0.033u/50V_6 100K/F_4
7
10
11
12
HWPG_1.5V [5,22,23]
add for EMI add for EMI
PR30 (For RT8207A 400KHZ) close to PC2016

VIN
PR41 620K/F_4
*0/short_6
S5_1.8V 1 2 SUSON [5,22,23,29]
PR27 *0/short_4
PR40 S3_1.8V 1 2 MAINON [22,23,28,29]

*0/short_6 PR28 *0/short_4
PR34 +5V_S5
*0_4
PR32
Vout = (PR150/PR149) X 0.75 + 0.75
PC18 10K/F_4
*33p/50V_6
B
8207A_SET
L(ripple current) B
S5_1.8V S3_1.8V
=(19-1.5)*1.5/(2.2u*400k*9)
PR26 *0_4
+1.5VSUS
~1.57A
PR31
10K/F_4
Vtrip= (10-1.57/2)*14mohm=0.129V
RILIM=Vtrip/10uA~12.901Kohm
3
MAIND 2
[25,29] MAIND
PQ27 S3 S5 +1.5VSUS REF VTT

AO3404
1
S0 1 1 ON ON ON
+1.5V
S3 0 1 ON ON OFF
TDC : 2A S4/S5 0 0 OFF OFF OFF
PEAK : 2.7A
A Width : 80mil A

PROJECT : ZE6
1A
DDR 1.5V(TPS51116)
5 4 3 2 1
5 4 3 2 1
34
VIN
+5V_S5
D D
PC114 PC116
PR87 PD7 2.2n/50V_4 4.7u/25V_8
10_6 RB500V-40
5
PR94
1
PR90 2.2/F_6 +1.05V
1M/F_4 PC58
4.7u/10V_6
2
PU5 PR93 4
*0/short_6
PR92 G5602 PQ41
*0/short_4 PC62 AON7410
3
2
1
[22,23,27,29] MAINON 15 13 0.1u/50V_6
EN/DEM BOOT
+3V 16 12 UGATE-1.05V PL9
TON UGATE 2.2uH_7X7X3
1 11 PHASE-1.05V
VOUT PHASE
5
PR91 2 10 PR95
10K_4 VDD OC 5.62K/F_4
PC56 3 9 PC61
FB VDDP
1
C *0.1u/50V_6 1u/10V_4 PR163 + PC113 C
4 8 LGATE-1.05V 4 *4.7_6 0.1u/10V_4
[22,23,29] HWPG_1.05V PGOOD LGATE
2
6 7 PQ42
GND PGND AON7702
3
2
1
5 17 PC115
NC TPAD *680p/50V_6
14 NC PC111 PC112
PC57 330u/2.5V_6X4.2 *10u/6.3V_8
1u/10V_4
PC55
*1000p/50V_6
B B
PR89 PC54
VOUT=(1+R1/R2)*0.75 +1.05VSUS
4.02K/F_4 *33p/50V_6
R1 1.05 Volt +/- 5%
1.05V_FB
TDC : 5.5A
PEAK : 7.3A
PR88
10K/F_4
OCP : 9A
R2 Width : 220mil
PR86
*0/short_6
PR85
*0/short_6
TON=3.85p*RTON*Vout/(Vin-0.5) L(ripple current)

Frequency=Vout/(Vin*TON) =(19-1.05)*1.05/(2.2u*272k*19)
A
TON=3.85p*1M*1/(Vin-0.5) ~1.658A A
Rth=14m*(9-0.829)/20uA
Frequency=1/(0.0036767)=272K Quanta Computer Inc.
RILIM=5.719Kohm
PROJECT : ZE6
1A
+1.05V(G5602)
5 4 3 2 1
5 4 3 2 1
VIN +1.5VSUS +3VSUS +15V
PR49 PR64 PR56 PR59

1M_4 *22_8 22_8 1M_4
VCCGFX
0.89Volt +/- 5% +1.05V
D
SUS_ON_G SUSD
SUSD [25] TDC : 1.98A D
3
PEAK : 2.64A
1
PC105 +3V
PR58 Width : 80mil 0.1u/10V_4
2 PQ9 1M_4 2 2 2 PC106
2
[5,22,23,27] SUSON DTC144EU PC30 VCCGFX 10u/6.3V_8
PQ17 PQ11 PQ8 *2200p/50V_4 PQ40
*DMN601K-7 DMN601K-7 DMN601K-7 AO3402 PR145
1
100K_4
1
PU9
1 3
G9334
5 DRV PGD 4 HWPG_VCCGFX [22,23]
PR143
2
+
PC103 PC40 10K/F_4 HWPG_1.05V
1
EN
1
330u/2V_7343 10u/6.3V_8 3 PC95
FB +5V *0.1u/10V_4
GND
VIN +3V +5V +1.05V +1.5V +15V 6
2
PR147 VCC
PR142 Rg 47/F_4
1
102/F_4 PC100
PR67 PR53 PR52 PR50 PR51 PR60 0.1u/10V_4
1M_4 22_8 22_8 *22_8 22_8 1M_4
2
C C
PC102
MAINON_ON_G MAIND 33n/25V_4
MAIND [25,27]
3
3
PR144 Rh
3
127/F_4
PR68
2 PQ18 1M_4 2 2 2 2 2
[22,23,27,28] MAINON
DTC144EU PC33
PQ13 PQ12 PQ14 PQ15 PQ16 *2200p/50V_4
DMN601K-7 DMN601K-7 *DMN601K-7 DMN601K-7 DMN601K-7 Vout1 = (1+Rg/Rh)*0.5
1
1
PR196 100K_4
+5VPCU
+3V
PU4
B PC140 1u/16V_6 G9661 B
4 1 HWPG_1.8V [22]
VPP PGOOD
HWPG_1.05V 2 6 +1.8V
VIN VCCGFX PR197 *0/short_4 VEN VO
+3VSUS 3
VIN PR198
8 R1 +1.8V
ADJ
GND
9 5 43.2K/F_4
PR55 PR66 GND NC
1M_4 22_8 PR199 PC141
1.8Volt +/- 5%
7
100K_4 10u/6.3V_8 TDC : 0.5A
0.8V PR200
PEAK : 0.7A
Width : 20mil
3
PC142 PC143 PC144 34K/F_4

R2
3
10u/6.3V_8 0.1u/50V_6 *0.1u/50V_6

PR54
2 PQ7 1M_4 2
[22,23,28] HWPG_1.05V DTC144EU Vout =0.8(1+R1/R2)
PQ10 =1.8V
DMN601K-7
1
A A

PROJECT : ZE6
1A
Discharge/1.8V
5 4 3 2 1
1 2 3 4 5
36
Thermal Protection (DCD)
VIN
A PD2 A
SW1010CPT
PR47
1
1M/F_4
PQ3
AO3409
TSNS_ON 2
3
S5_ON 2
3
PQ6
1
DTC144EU
B
VL VL B
SYS_SHDN# [4,25,26]
PR42 PR35
1.3K/F_4 200K/F_4
PC24 PR44
0.1U/25V_4 200K/F_4
3
8
PR43
10K/J(NTC) _6 2.469V 3
+
1 2
2
- PQ4
3
PU2A DMN601K-7
4
AS393MTR-E1 PC25
1
0.1U/25V_4
[22,23,25] S5_ON 2
PR39
C PQ5 200K/F_4 C
DMN601K-7
1
PU2B
5
+
7
6
-
AS393MTR-E1
D D

PROJECT : ZE6
1A
Thermal protect
1 2 3 4 5
5 4 3 2 1
30
DDR3 SO-DIMM
DMI (100MHz)
Page 03
D CLOCK GEN CK505 LVDS CLK (Max. 200MHz) 11.6" LED Panel D
(SLG8SP513VTR Page 15
MEM (333MHz) SATA (100MHz)
,ICS9LPRS365BKLFT)
Tigerpoint
PCI (33MHz) BIT CLK (24MHz)
Audio ALC272
Page 26
REF (14.31818MHz)
CPU FSB (166MHz)
Intel@Pineview-M USB (48MHz)

MCH FSB (166MHz) SUSCLK (32KHz)
Page 9~14
MCH DMI (100MHz)
C LCD CLK (100MHz) C

Page 5~8
Y2(32.768K KHz)
DOT 96 (96MHz)
PCIE (100MHz)
LAN AR8131L
Y3(25 MHz)
Page 19
Page 2
PCIE (100MHz) WLAN(Mini Card 1)

Page 21
PCIE (100MHz) WLAN(Mini Card 2)

Page 21
B B
PCI CLK (33MHz) EC

(WPCE781L/FLASH) Y4(32.768 KHz)
Page 23
PCI CLK (33MHz) Debug Card

Page 21
48MHz Card Reader

RTS5138 Y5(12 MHz)
Page 22
A A
Y1(14.318 MHz) Quanta Computer Inc.

PROJECT : ZE6
1B
Clock Distribution Diagram
5 4 3 2 1
5 4 3 2 1
31
D ISL6261A VCC_CORE
D
PU3 <VRON>
+5VPCU
<AC/DC Insert>
AO3404 +5V_S5
+5VPCU
PQ0009 <S5D>
AO3404 +5V
VIN
POWER Distribution
PQ0010 <MAIND>
VIN LCD Backlight
+3VPCU
SYSTEM <AC/DC Insert> VCC_CORE CPU
5V/3V +5VPCU USB Connecter
(RT8206BGQW)
C
AO3404 +3V_S5 +5V_S5 RTC, TPT C
<S5D>
PQ0008
PU0001 +5V TPT , CRT , TouchPad , Codec , SATA , FAN , HDMI
+3VPCU RTC, Hall Sensor, Light Sensor, EC, BIOS
+3VPCU
ADAPTER AO3404 +3VSUS

CHARGER PQ0013 <SUSD> +3V_S5
VIN TPT , LAN , LAN EEPROM , RJ45 LED
(ISL88731)
3G
BATTERY PU2 AO3404 +3V +3VSUS
PQ0005 <MAIND>
+3V CLK_GEN, CPU, TPT , LCD , CCD, DMIC, BT, Codec, WLAN/Wimax, Card reader, EC, DDR, HDMI
RT9025-25PSP +2.5V DDR

+1.5VSUS
PU1 <MAINON>
CPU, HDMI
+1.8V
+1.5VSUS
+1.5V CPU, TPT
<SUSON>
+1.5VSUS
AO3404 +0.75V_DDR_VTT DDR

RT8207A +1.5V
PU2000 PQ2002 <MAINON> CPU, DDR
VIN
B B
+SMDDR_VREF
+1.05V CLK_GEN , CPU, TPT

+0.75V_DDR_VTT
<MAINON> VCCGFX CPU
+SMDDR_VREF +2.5V HDMI

<SUSON>
G9334ADJ
+1.05V
UP6111AQDD <MAINON + (RC)>
+1.05V
G9334ADJ
VCCGFX
PU9004 <HWPG_1.05V>
A G9334ADJ +1.8V
A
PU9003 <HWPG_1.05V>

PROJECT : ZE6
1B
Power Tree
5 4 3 2 1
5 4 3 2 1
ZGA Power On Sequence 32
From AC,BATT VIN

+5VPCU +3VPCU VCCRTC
D D
From PWM to EC HWPG_SYS(PCU)
>=18ms (VCCRTC to RTCRST#)(t200)
RTCRST#
From Button to EC NBSWON#
From EC to PWM S5_ON >=0ms (VCCRTC to S5 well)(t203)
+5V_S5 +5V_S5 power up before +3V_S5, or
after +3V_S5 within 0.7V (t201) +3V_S5 power down before +5V_S5,
+3V_S5 >=5ms (S5 well to EC_RSMRST#)(t205)
or after +5V_S5 within 0.7V
From EC to SB EC_RSMRST#
100ms (EC define)
From EC to SB DNBSWON#
1~2 RTCCLK (SUSC# to SUSB#)(t234)
From SB to EC SUSB#,SUSC#
From EC to PWM SUSON
+3VSUS +1.5VSUS +SMDDR_VREF
From PWM to EC HWPG_1.5V (SUS)
C C
From EC to PWM MAINON +5V power up before +3V, or

+3V power down before +5V,
after +3V within 0.7V (t209)
or after +5V within 0.7V
+5V +3V +1.5V +0.75V_DDR_VTT
+1.05V power down before +1.5V,
From PWM to EC,PWM MAINON + (RC)
or after +1.5V within 0.7V
+1.05V +1.5V power up before +1.05V, or
after +1.05V within 0.7V (t211)
>=0ms (+3.3V to +1.05V)(T1)
From PWM to EC,PWM HWPG_1.05V >=0ms (+1.8V to +1.05V)(T3)
+1.8V VCCGFX >=0ms (+1.05V to +1.8V)(T2)
From PWM to EC
HWPG_VCCGFX
From PWM to EC HWPG
From EC to PWM VRON 10~100us (VCC_CORE=1.2V)(Tc)
VCC_CORE 0~0.6ms (VCC_CORE@VID value)(Td)
From PWM to CLK,SB VR_PWRGD_CK410#
B B
BCLK
From CLK Gen
From PWM to EC,CPU IMVP_PWRGD

99ms (S0 well of TPT to TPT_PWROK)(t214)
To SB TPT_PWROK 0.05~200ms;Typ=20ms (VCC_CORE to H_PWRGD)(Te)
From SB to CPU H_PWRGD >=10BLK=60ns(BCLK stable to H_PWRGD)(Tf)
From SB PLTRST#
1~10ms (H_PWRGD to PLTRST#)(Th)
*Note: EC will sampling SUSB# & SUSC# every 5ms.

ICH SMBUS Table EC SMBUS Table
A
CLK GEN RAM Mini Card (WLAN) Mini Card (3G) Battery CPU thermal Sensor A
(SMB_DATA)/(SMB_CLK) (+3V_S5) V V V V EC781 SDA1 / SCL1 (+3VPCU) V

Power Plane +3V +3V +3V +3V_SUS
EC781 SDA2 / SCL2 (+3V) V
EC781 SDA3 / SCL3 (+3VPCU)
MOS CKT (Level shift) Stuff Stuff *Reserve Stuff Power Plane +3VPCU +3V
MOS CKT (Level shift) X X PROJECT : ZE6
*Reserve: There is not SMBUS function in AVL
1B
SYSTEM INFORMATION
5 4 3 2 1
5 4 3 2 1
33
SLP_S3#(SUSB#): NBSWON# 3
Control non-critical power plane when system into S3(Suspend to RAM)/S4(Suspend to Disk)/S5(Soft off). 5 +5V_S5 power up before +3V_S5
4
SLP_S4#(SUSC#): +3VPCU/+5VPCU +5V_S5
S5_ON
Control non-critical power plane when system into S4(Suspend to Disk)/S5(Soft off).Used to control DRAM power MOS
1b PQ0008/PQ0009 +3V_S5
6
AC Adapter 1 +3VPCU EC_RSMRST#
Always System power RSMRST#
BATT Charger VIN
D
PU9001 Regulator +5VPCU D
7
Battery PQ9007 DNBSWON#
PWRBTN#
9 2 8
SUSON SUSC#
SLP_S4#
12 SUSB#
SLP_S3#
MAINON
EC TigerPoint
ECPWROK
Pineview
19
VRON U8002
24
H_PWRGD
PWROK CPUPWRGD CPUPWRGOOD
TPT_PWROK
C C
23 RSTIN# PWROK
25
U23 PLTRST# PLTRST#
20
VIN
Regulator VCC_CORE
PU3 U8003 VRMPWRGD
IMVP_PWRGD 22
VR_PWRGD_CK410#
16
+1.8VSUS
MOS +1.8V 1.05V power up before 1.8V
PQ9021 SYS_HWPG 21
VR_PWRGD_CK410
16 HWPG_1.8V
+1.05V VCCGFX(0.89V)
LDO 17 HWPG_VCCGFX 18
PU9004 HWPG
B B
15 HWPG_1.05V
VIN 14 HWPG_2.5V
MAINON +(RC) CKPWRGD
Regulator +1.05V 1.5V power up before 1.05V
PU6000 HWPG_1.5V
CK505
+3VPCU
LDO +2.5V U9
PU1
+1.5VSUS
LDO +1.5V 13
PQ2002
+3VPCU/+5VPCU +5V +5V power up before +3V

MOS +3V
PQ0005/PQ0010
11
+0.75V_DDR_VTT 13
A A
VIN
Regulator +1.5VSUS
PU2000 +SMDDR_VREF
10
+3VPCU
+3VPCU SUSD +3VSUS
MOS Quanta Computer Inc.
MOS PQ0013 PROJECT : ZE6
1B
power sequence block diagram
5 4 3 2 1
5 4 3 2 1
MODEL
ZE6
Model REV CHANGE LIST FROM To
FIRST RELEASED: (PCB:A) X 1A
A1
Page 2 : add R374 for CLK GEN change version
ZE6 MB Page 11 : change RTC connector type from SMT to holder.
Page 15 : modify TP connector pin define
Page 16 : modify audio and mic connector pin define.
Page 17 : modify USB charger IC circuit to support or not support charger function.
D D
Page 29 : modify 1.8V IC enable signal to HWPG_1.05V
B
20110117 Page 15 : add CP1~CP6 for EMI issue
20110117 Page 15 : for EMI issue: change R232,R233,R234,R235,R236,R231,R211 to bead CX5BB121001
20110118 Page 27 : for EMI issue: add PC96 ,PC32 and stuff PR48, PC29
20110118 Page 30 : Thermal temperature setting at 75C, change PR42 from 1.54K/F to 1.3K/F
20110131 Page 14 : add 5V into LCD connector for IVO panel to use.
C C
B B
1D
A A

DOC NO. PROJECT MODEL : 11.6 APPROVED BY: DATE: 2009/12/05 PROJECT : ZE6
1B
PART NUMBER: DRAWING BY: REVISON: 1B Change list
5 4 3 2 1

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ZE6 Block Diagram

DDR SYSTEM MEMORY

Audio Codec Realtek ALC271X EC NPCE791L

Quanta Computer Inc.

Date: Friday, March 11, 2011 Sheet 1 of 35

CLK GEN (CLK) 02

CLKREQ_MNC#_R R202 10K/J_4

Y2 SMBCK1 8 34 FSB C189 *10P/50V_4

33P/50V_4 CG_XOUT USB48_1/FSB SRC_5

VSS_SRC CLKREQ_B# CLKREQ_WLAN# [20]

R206 *10K/J_4 0 0 133MHz VR PWRGD

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

Place these Caps near So-Dimm0. 1K/F_4

+SMDDR_VREF R140 *0_6 +SMDDR_VREF_DQ0

C115 + C108 C110 C107 C132 C131

C116 C125 C113 C111 C128 2.2u/6.3V_6

C118 C117 C122 C119

DMI_RXN_0 DMI_TXN_0 DMI_RXN0 [8] RSVD_TP

XDP_BPM#5 : Length<200mil R55 C36 R281 C251 C257

CPU FAN CTRL(THM) CPU Thermal monitor(THM) +3V

125 Degree Protection(CPU)

FAN_ON# R124 10K_4 FAN_PWM_B 2 Q6

CPUFAN# Size Document Number Rev

[22,23,27,29] SUSON 1 AG13 AG21 M_A_DQS#4

TC7SH08FU R121 DDR_A_DQ_32 M_A_DQ33

R353 C296 AA24 M_A_DQ56

VCCGFX U21E VCORE

VCC_GIO VCCA_DMI +1.05V

Quanta Computer Inc.

0110 : exchange USB port 1 and port 3

[4] DMI_RXN0 R23 H7 USBP0- [17]

R78 24.9/F_4 DMI_COMP H24

[2] CLK_PCIE_ICH# W23

Quanta Computer Inc.

RSVD30 INTR H_INTR [4]

*1K_4 R71 PCH_GPIO48 *1K_4 R72

EMI BATLOW#:8.2K pull-up to V3ALWAYS

T18 AA5 T15 BM_BUSY# +3V_S5

R329 R343 R342

Platform Reset TPT Power OK R328 R332 R330

D33 C293 2 *TC7SH08FU

Q10 ACZ_SDOUT ACZ_SYNC INTVRMEN

R161 Enable internal VccSus1_5 VRM

CN5 R162 1 0 Reserved

1 1 1 x 4s(1 port/4 lanes)

D30 1 2 1SS355 +3V

VCC1.5_SATAPLL R109 *0/short_6

14mA W18 VCCP_VCC1_05

1.422A AA8 VCC1.5_VCC1.5 R341 *0/short_6

0.955A J10 VCCP_VCC1_05 R319 *0/short_6

0.216A H25 VCC3_VCC3 R105 *0/short_6 +3V

0.092A F18 RVCC3_VCCSUS3 R311 *0/short_6 +3V_S5

Quanta Computer Inc.

Quanta Computer Inc.

+3V C242 4.7U/10V/8

DISPON C248 C247

2N7002K BAM70020002 (with ESD protection function) CCD_POWER 6

100K_4 R259 IC(5P) G5243AT11U C25 *3300P/50V_4 LCD_VADJ 13

SMD1206P110TFT R39 *0/short_4 LCD CONN

CRT CONN [4] INT_TXLOUTN2 INT_TXLOUTN2_L

TOUCH PAD (TPD) +5V_TP

1K_4 R71 PCH_GPIO48 1K_4 R72

MAIN_SATA .1U/10V_4 0.1U/10V_4 4.7U/10V/8 100U/6.3V_3528

HG-C276D98P2 HG-C276D98P2 HG-C276D98P2 HG-C276D98P2 *HG-C276D98P2 NBSWON# 2 1

TON=3.85pRTONVout/(Vin-0.5) L(ripple current)