ARM7 THUMB FAMILY

w w w . a r m . c o m

ARM7TDMI , ARM7TDMI-S ,
ARM7EJ-S and ARM720T

The ARM7 family of processors is a range of low-power, 32-bit RISC cores

optimized for cost and power-sensitive applications. All the cores in the

family feature the 16-bit Thumb instruction set, enabling high code density to

be achieved with 32-bit performance levels.

The ARM7 family comprises:

ARM7TDMI: An integer core with three-stage pipeline delivering high

performance together with very low power consumption on a small die size.

This outstanding combination makes the ARM7TDMI processor the most

widely shipped 32-bit embedded RISC processor in the world

ARM7TDMI-S: A synthesizable version of the ARM7TDMI core, ideal for

modern design flows where portability and flexibility are key

ARM7EJ-S: An enhanced, synthesizable core with architecture and

instruction set extensions to support DSP operations and accelerated

execution of Java applications using ARM Jazelle technology

ARM720T: An integer core with memory management unit and 8KB unified

cache for open platform applications such as Windows CE, Linux, Palm OS

and Symbian OS.

Key Features Key Benefits

All ARM7 family processors share a range of All ARM7 family processors offer significant
common features: benefits to developers and integrators:

High performance: up to 120 MIPS on Established, high-volume 32-bit RISC

0.13m (Dhrystone2.1) architecture
Low power consumption Fast time-to-market
Small die size Wide choice of development tools
High code density Code-compatible upward migration path to
ARM9 and ARM10 families allowing re-use
Real-time debug facilities of application code
Coprocessor interface Migration and support across new process
technologies

T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D
 Industry Acceptance The ARM7 Thumb Family ARM720T
More than 40 companies currently offer ASICs, Open platform processor core

ASSPs and system-on-chip solutions using ARM7 MMU

ARM7EJ
family cores. This global acceptance enables a Jazelle-enabled core 8K Cache
ARM7TDMI ARM7TDMI-S
wide range of design and system support, from Synthesizable integer core
Integer core EmbeddedICE-RT EmbeddedICE-RT
ARM and its Partners, to meet the growing need
EmbeddedICE-RT EmbeddedICE-RT ETM9 Interface ETM7 Interface
for reduced design cycles and faster time-to-
ETM7 Interface ETM7 Interface DSP Extensions ARM v4T
market.
ARM v4T ARM v4T Jazelle Extensions ARM7 Core
While widely accepted, the ARM7 cores, together
ARM7 Core ARM7 Core ARM v5TEJ Thumb Extensions
with IP and development tools from ARM and third-
Thumb Extensions Thumb Extensions Thumb Extensions AHB Interface
party companies, enable our Partners to develop
highly differentiated solutions matched closely to
specific market requirements.
The ARM7TDMI Core The ARM720T Macrocell
Applications The ARM7TDMI core is the industrys most The ARM720T hard macrocell is a high-
Basic wireless handset widely used 32-bit embedded RISC performance processor for systems requiring full
Pager microprocessor. Optimized for cost and power- virtual memory management and protected

Ink-jet/bubble-jet printer sensitive applications, the ARM7TDMI solution execution spaces. It is compatible with leading
provides the low power consumption, small size operating systems such as Linux, Palm OS,
Digital still camera
and high performance needed in portable, Symbian OS and Windows CE.
PDA
embedded applications. Key features are:
It combines the ARM7TDMI core with:
Java-Enabled Hard macrocell
Applications 8K unified cache
Portable down to 0.13m
Memory Management Unit (MMU)
Entry-level Java wireless handset Performance up to 120 MIPS (Dhrystone 2.1)
Write buffer
Home automation Thumb and ARM instruction sets
AMBA AHB bus interface
Entertainment systems Three-stage pipeline
The ARM720T core retains the coprocessor and
Gaming Unified bus architecture
ETM interfaces for system expansion and real-
Information delivery Low power, fully static design
time debug capabilities.
Small die size
Coprocessor interface AR720T System Benefit
EmbeddedICE-RT debug logic The on-chip cache and write buffer substantially
ETM Interface EmbeddedICE-RT logic Embedded Trace Macrocell (ETM) interface raise the average execution speed and reduce the
average amount of system bus bandwidth
The ARM7TDMI-S Core required by the processor. There are multiple
ARM7TDMI

The ARM7TDMI-S core is the synthesizable benefits to system design:

version of the ARM7TDMI core with identical
The system bus and external memory can be run
ARM7TDMI performance levels and feature set.
core at lower speed than the processor, reducing
power consumption
Optimized for flexibility, the ARM7TDMI-S core
cuts time-to-market by reducing development External memory can support additional
processors or Direct Memory Access (DMA)
Coprocessor
Interface
Bus Interface Unit time while allowing for increased design channels with minimal performance loss.
flexibility.
Low-cost commodity RAM can be used.

www.arm.com
Flyer 2pp | ARM DOI 0107-1/10.01
info@arm.com
 ETM Interface

Coprocessor
ARM v5TEJ Interface
CPU core Jazelle Technology Thumb Instruction
Set
ARMs Jazelle technology provides hardware
ARM7EJ-S acceleration to deliver up to 8 times higher Java The Thumb instruction set is an extension

performance compared to a software-only Java of the 32-bit ARM architecture.

Control Logic and Bus Interface Unit Virtual Machine (JVM). Thumb instructions are a subset of the
most commonly used 32-bit ARM
Jazelle technology-enabled ARM cores also use over
instructions that have been compressed
80% less energy per CaffeineMark than an equivalent
into 16-bit opcodes. On execution, these
non-accelerated ARM core.
16-bit instructions are decompressed to
The ARM7EJ-S Enhanced Because Jazelle extends the ARM7 core 32-bit ARM instructions in real time
Core functionality, developers have the freedom to run without performance loss.

The ARM7EJ-S core provides all the benefits of the
ARM7TDMI core low power consumption, small
size and the Thumb instruction set while also
incorporating ARMs Jazelle technology and DSP
extensions, offering up to 120 MIPS on a typical
Java code alongside existing operating systems and Designers can use both 16-bit Thumb and
applications offering a fast upgrade path for designs 32-bit ARM instruction sets at a sub-
using the ARM7TDMI core. routine level and therefore have complete
flexibility to compile for maximum
DSP Instructions performance or minimum code size as

0.13m process (Dhrystone2.1). required by the application software.

The ARM7EJ-S processor incorporates the ARM DSP

The DSP instruction extensions allow systems that extensions that offer enhanced 16-bit and 32-bit The use of Thumb code provides typical
arithmetic capabilities within the functionality of a memory savings of up to 30%.
may conventionally have been designed using a
microcontroller and DSP to be implemented in a single CPU, for improved performance and flexibility. Key

core solution, removing multi-core complexity. features are: AMBA

16-bit data operations The AMBA interconnect is an open
The Jazelle extensions enable hardware acceleration
standard, on-chip bus specification that
in the execution of Java applications while retaining Saturating, signed arithmetic on both 16-bit and
32-bit data details a strategy for the interconnection
compatibility with existing ARM and Thumb code.
Enhanced MAC operations. and management of functional blocks
that makes up a system-on-chip (SoC).
Coprocessor Support Advanced High-performance Bus
All members of the ARM7 family have a coprocessor the AHB is a high-bandwidth bus for
interface to allow easy connection of up to 16 connecting fast blocks such as
memory
coprocessors.
Advanced Peripheral Bus the APB
The ARM720T processor has a built-in coprocessor is a simpler bus for connecting
general-purpose peripherals
(CP15) which is used for internal control of cache and
MMU.
ETM Interface

PERFORMANCE CHARACTERISTICS
Processor Generic Performance Power Consumption Area Frequency
Cache Foundry Process MIPS/MHz mW/MHz mm2 MHz
(Dhrystone 2.1) (Typical1) (Worst case2)
MMU ARM7TDMI ARM7TDMI 0.18m 0.9 0.25 0.53 90
core
ARM7TDMI-S 0.18m 0.9 0.39 0.62 80-110
ARM7EJ-S 0.18m 1.0 0.45 0.95 80-110
Write buffer
ARM720T 0.18m 0.9 0.65 3.00 75
ARM720T

Control Logic and Bus Interface Unit

ARM7TDMI 0.13m 0.9 0.06 0.26 133
ARM7TDMI-S 0.13m 0.9 0.10 0.32 100-133
Coprocessor ARM7EJ-S 0.13m 1.0 0.18 0.42 100-133
Interface AMBA AHB bus
ARM720T 0.13m 0.9 0.20 2.40 100
1
Typical figures on nominal silicon at 25 C 2
Worst case figures on slow silicon at 125 C
Average port & synthesis & cell library Average best port & synthesis & cell library
0.18 m at 1.8V, 0.13 m at 1.2V 0.18 m at 1.62V, 0.13 m at 1.08V
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Real-Time Debug and Development Support

Integrator
The Integrator development boards enable SoC
designers to integrate hardware and software
platforms easily and seamlessly with ARM core-
based microprocessors.

The Integrator family provides a modularized set of

boards that offers ARM test silicon, a development
environment with memory, peripherals, PCI bus
connectors, the AMBA bus and the ability to
incorporate custom logic into FPGAs.

EmbeddedICE-RT MultiTrace
The ARM Developer Suite
The integral EmbeddedICE-RT logic enables the core The MultiTrace trace port analyzer unit passively The ARM Developer Suite (ADS) provides a
to be halted on breakpoints and watchpoints and collects information from SoCs where an ARM7 complete software development environment,
allows registers and memory to be examined and core-has been connected to an ETM7 logic unit. The including compiler,
modified. The logic is configured and accessed ETM monitors the ARM instruction and data buses assembler, debugger,
through a TAP controller and JTAG port. For real- at full core speeds, using the MultiTrace analyzer to linker and instruction
time systems, where physical components must buffer the collected information before transmission set simulator for
remain under control, interrupts can be re-enabled to the Trace Debug Tools running on the rapidly and cost-
to allow service routines to continue to execute development workstation. effectively creating
whilst the foreground task is debugged.
applications to run on
Multi-ICE
the ARM architecture.
Embedded Trace Macrocell The Multi-ICE unit is a powerful JTAG-based In-
The optional Embedded Trace Macrocell (ETM) Circuit Emulator (ICE) that enables the non-intrusive Trace Debug Tools (TDT)
interfaces directly to any of the ARM7 family cores debug of the ARM7 family cores at full speed. The Trace Debug Tools are an extension to the ARM
to monitor the internal buses and enable non-
The Multi-ICE unit interfaces between a Developer Suite (ADS) which decompresses the
intrusive tracing of instruction execution and data
development workstation and the JTAG port of a stored information retrieved from the MultiTrace unit
accesses at core speeds.
SoC. Software running on the workstation is used to and interleaves assembler code, symbolic
The trace information is compressed, buffered and control the EmbeddedICE-RT and ETM logic to information and data accesses.
passed off-chip through a dedicated, configurable support a full
AMBA Design Kit (ADK)
Trace Port. range of in-circuit
The ADK solution is a versatile toolkit aimed at
debug and trace
Embedded Trace Buffer enabling the successful creation of AMBA bus-
facilities.
In SoC designs where a Trace Port cannot be based components and SoC designs. It contains the
implemented due to pin constraints, the optional Example AMBA System Design (EASY), ASB and
Embedded Trace Buffer (ETB) can store trace APB Module testbenches, CPU AHB wrappers,
information in an on-chip circular buffer. The stored testbenches, synthesis scripts, example software,
data be read externally through the JTAG port or production test vectors, module testbenches and
internally through an AHB slave device. documentation.

ARM, ARM Powered, StrongARM, Thumb, Multi-ICE, Integrator, PrimeCell and ARM7TDMI are registered trademarks of ARM Limited. ARM7TDMI-S, ARM7EJ, ARM720T, ARM740T, ARM9TDMI, ARM920T, ARM922T, ARM940T, ARM9E, ARM926EJ-S, ARM946E-S, ARM966E-S, ARM1020E,
ARM1022E, EmbeddedICE, EmbeddedICE-RT, AMBA, MultiTrace, ModelGen, ARM Developer Suite, RealView, ETM, ETM7, ETM9, ETM10, Embedded Trace Macrocell, Jazelle, PrimeXsys, MOVE and JTEK are trademarks of ARM Limited. CodeWarrior is a registered trademark of Metrowerks
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ARM7 Thumb Family | ARM DOI 0035-3/02.02(7)