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Microprocessor CBCS IV sem

8086 Microprocessor

The 8086 microprocessor was developed by Intel in 1978. It was the first 16-bit microprocessor. The
word length of the 8086 microprocessor is 16 bits. The memory address ( width of Address Bus) of 8086 is 20
bits and hence can access a memory space of 1 MB.

Architecture of 8086

Architecture of 8086 is divided into two main blocks namely BIU and EU.

Execution Unit (EU): It executes all the logical and arithmetic instructions. It comprises of general purpose
registers like:

1) AX - It is called as the Accumulator and is 16-bit in length. It can also be accessed as two half registers
as AH and AL respectively.

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2) BX - It is called as the Base Register. It is also of 16 bits and can be split as BH and BL into two 8 bit
registers. It is used to store base address for arrays.
3) CX - It is a 16 bit register and is known as the Counter Register. It can also be split into CH and CL,
two 8-bit registers.
4) DX - It is used for MUL and DIV instructions. It is also used for reading and writing into I/O ports. It
is also 16 bits in length and can be split as DH and DL.
5) SI - This is the Source Index register and is 16 bits in length. It points to source string.
6) DI - This is the Destination Index register and is also 16 bits wide. This pointer points to destination
string.
7) SP This is the Stack Pointer and points to the top of the stack. It is 16 bits in length.
8) BP This is known as the Base Pointer. This also points to the top of the stack and is 16 bits long.
Execution Unit has a 16 bit ALU to perform 8 or 16 bit arithmetic and logical operations. The
result is recorded in an internal register before it is written to another register or any other memory
location. This also affects flags.

FLAG REGISTER:

1) OF (Overflow Flag):
Used for signed arithmetic
It is 1 when arithmetic operation has resulted in an overflow condition
It is 0 when no overflow has not been produced.
For 8 bit arithmetic it is given by OF = (C6 XOR C7) and for 16 bit arithmetic it will be given
by OF = (C14 XOR C15).
For subtraction operation of 8 bit arithmetic it is given by OF = (B6 XOR B7) and for 16 bit
arithmetic it will be given by OF = (B14 XOR B15) where B is borrow flag.
2) DF (Directional Flag):
This is a programmable flag and is used in string operations.
When the string is to be scanned from first character to the last (STD), it is set to 1.
When the string is to be scanned form the end of the string (CLD), it is set to 0.
3) IF (Interrupt flag):
It is a programmable flag. It is used to control the maskable interrupts in 8086.
If the interrupts on INTR is desired, then it must be set to 1.
If the interrupts on INTR is not desired it must be set to 0.
4) TF (Trap Flag):
It is another programmable flag.
It must be programmed to 1 if single step execution is needed. Else, it must be programmed to
0 to disable single step execution.
5) SF (Sign Flag):
This is a status flag in 8086.

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It is set to 1 if previous arithmetic operation has produced a negative result i.e. MSB = 1.
If the result is positive or the MSB = 0, this flag is set to 0.
6) ZF (Zero Flag):
This is also a status flag.
It is set to 1 if the previous arithmetic operation has produced zero result.
It is set to 0 if the previous arithmetic result has produced a non-zero result.
7) AF (Auxiliary Flag):
It is the auxiliary carry flag and is a status flag.
It is set to 1 if there is a carry or borrow from B 3 to B4.
It is set to 0 if there is no carry or borrow from B 3 to B4.
8) PF (Parity Flag):
This is also a status flag and is an even parity flag.
It becomes 1 if there is an even number of 1s in the lower byte of the result after an arithmetic
operation.
It becomes 0 if there is an odd number of 1s in the lower byte of the result after an arithmetic
operation.
NOTE: For both 16 - bit and 8 - bit operation, parity is applicable to only the lower 8 bits of the
result.
9) CF (Carry Flag):
This is a status flag. It also acts as the borrow flag during subtraction operations.
It is set to 1 if a carry/borrow is generated during an arithmetic operation. It is the B7 for 8 bit
operation and B15 for 16 bit operation.
Bus Interface Unit (BIU):
This connects the execution unit of 8086 to the rest of the world. It majorly has segment registers, instruction
queue and control unit.
Segment and Segment registers:
Memory of 8086 is divided into segments. We can have 4 segments namely:
1) Code segment: It is used to store the program or code or instruction.
2) Data segment: It is used to store the data related to the segments.
3) Stack segment: It is used to store the stack.
4) Extra segment: It is used to store data. It is mainly used for strings.
The starting address of each of the registers is in a register called segment register as,
Segment Reg. name Length of Reg Size of segment

Code segment CS 16-bit 64 KB


Data segment DS 16-bit 64 KB
Stack segment SS 16-bit 64 KB
Extra segment ES 16-bit 64 KB

6 byte instruction queue:

On the 8086 chip there is a 6 byte instruction queue to prefetch the instruction from memory. This improves the
processing speed. Depending on the length of the instruction, we can prefetch 1 to 6 instructions in the queue
and the queue follows FIFO (First In First Out) so that the order of the execution does not change.

Control Unit:
This generates all the control signals required for the program execution. E.g. RD, WR etc.

Instruction pointer:
This is a 16 bit register. It points to the next instruction to be executed.

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PROGRAMMING MODEL OF 8086

For 8086 to the Pentium 4, this model holds good. E indicates extended registers. In 8086, 8088 and 80286, 16
bit registers are present and 8 bit registers like AH, AL etc. are present. CS, DS, ES and SS is also present.
From 80386 onwards, 32-bit registers like EAX, EBX etc are there. And for 64bit processors the
register will be RAX, RBX etc. 80386 onwards also have FS and GS registers which define two more segments
which are used to store the data. The size of segments is always 64KB.

There are two modes of operation namely Real mode and Protected mode.

1) REAL MODE: In this, processor can address only upto 1 MB (first Mega Byte) is called as Real
memory or conventional memory or DOS memory system. All registers are 16-bit. DOS OS needs real
memory only.

2) PROTECTED MODE: In this memory is more than 1 MB and can go upto 4GB. Windows OS will be
used. All registers will be 32-bit.

SEGMENTATION

In 8086, all registers, pointers, segment registers are all 16 bit wide whereas the PA (Physical Address bus
width) is 20 - bit and can hence address 1 MB memory.

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This 1 MB of memory in 8086 in divided into segments of size 64 KB (2 16 bytes). Basically there are 4
segments in 8086. Their names and uses are given below:

NAME USE

Code segment Used to store program


Data segment Used to store data
Stack segment Used to store stack
Extra segment Used to store data

Each of these segments starting address (MS 4 hex digits) is stored in CS, DS, SS and ES segment registers
respectively. For one program, a user may require 1 CS, 1 DS, 1 SS and 1 ES or just a single CS.

The memory address of 8086 is defined at 2 levels which are:

1) EFFECTIVE ADDRESS (EA):

This is 16 bits in length.


This is not the complete address of the memory location.
EA is provided by the addressing mode used for the operand. Examples of this are:

Direct AM By variable name


Register Direct AM Contents of BX,SI or DI
Register relative BX, SI, DI or BP with 8 or 16 bit offset
Base indexed (BX or BP)+(SI or DI)+ (8 or 16 bit offset)

2) PHYSICAL ADDRESS (PA):


This is 20 bits in length.
This is the true address of the memory location.
This is computed using segment register. The pointers with the allowable respective registers are given
below:
POINTERS REGISTER NOTATION USE

DS BX, SI, DI PA=DS:BX Data storage


PA=DS:SI
PA=DS:DI
SS SP, BP SS:SP Stack handling
SS:BP
ES DI ES:DI String operations
CS IP CS:IP Instruction handling

Segmentation allows multiple users to share the same memory. 1 CS, 1DS, 1 ES and 1 SS takes 256KB of
memory. Hence, 4 users can share the same memory.
Segments can be overlapped if they do not need complete 64KB. By overlapping them, we can have more
segments in the same 1MB memory and more users can work on the same memory.
Another advantage of segmentation is the relocation of code. If the code segment is starting at 1000h first
time and the second time, it is moved to 2000h then the code need not change because EA is still the same
and only the PA changes.
NOTE: Segments in the real and protected i.e. 8086 to Pentium pro are 64KB in size. In protected, we have
2 more segments FS and GS to store the data.

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SEGMENT OVERRIDE:

BP by default points to Stack Segment but if we want BP to point to and access data from Data
segment then we need to override the segment. Segment override prefix is used to change the segment register
from default to a new segment to calculate PA. Hence, the instruction translates as,

MODE REG R/M


MODE
In this, considering MODE=001 and R/M=100, for different values of REG, the value translates to the following
values with the Segments as,

REG Segment Value of code

00 ES 24h
01 CS 2Ch
10 SS 34h
11 DS 3Eh

8086 ADDRESSING MODES

The various addressing modes of 8086 are as follows:


1. Immediate addressing mode
2. Register addressing mode
3. Direct addressing mode
4. Register indirect addressing mode
5. Register relative addressing mode
6. Based-indexed addressing mode
7. Based-indexed with displacement addressing mode
8. Fixed port addressing mode
9. Variable Port addressing mode

1) IMMEDIATE ADDRESSING MODE:


Here, data is a part of the instruction.

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It can be 8-bit or 16-bit but can be used only as a source operand.


The data can be given in different bases i.e. h for hexadecimal, d for decimal, o for octal and b for
binary.
If immediate data begins with alphanumeric character, then prefix of 0 is needed.
Eg: MOV AX,1234h
MOV [SI],34h

2) REGISTER ADDRESSING MODE:


In this, data will be in CPU register.
WORD registers are AX, BX, CX, DX, SI DI, BP and SP.
BYTE registers are AL, BL, CL, DL, AH, BH, CH and DH.
It can be both source and destination.
Data transfer has to happen between register of same capacity (byte to byte or word to word).
e.g.: 1) MOV BX,SI 2) MOV AL,DH

3) DIRECT ADDRESSING MODE:


Address of the instruction operand is specified in instruction.
Variables can be declared in data segment using :
db: define byte
dw: define word
dd: define double word (32-bit)
dq: define quad word (64-bit)
dt: define tera word (10-byte)
It can be either source or destination operand.
EA= provided in the instruction
PA= (segment register 1610) + EA
For BX, SI, DI use DS for PA calculation.
For BP use SS for PA calculation.
E.g.:
1. MOV AX,LOC
2. MOV BL,N1
3. MOV SI,DS:2000h
Assume LOC=10h, N1=1000h and DS=1000h.
a. EA of LOC=10h.
PA= (1000h 1610) + 10h = 10010h
b. EA of N1=100h.
PA= (1000h 1610) + 100h = 10100h
c. EA of DS:2000h = 2000h
PA= (1000h 1610) + 2000h = 12000h

4) REGISTER INDIRECT ADDRESSING MODE:


The EA of the operand is given by a pointer register (BX, SI and DI)
It can be either only source or only destination.
E.g.: MOV AH,[SI] move a byte from EA in SI to AH. If SI=2000h then EA=2000h and if DS=3000h,
PA=32000h.
Similarly, MOV [BX],DX copies the content of DX to word location pointed by BX.

5) REGISTER RELATIVE ADDRESSING MODE:


EA is given by a pointer register (BX, SI, DI or BP) with a signed 8 or 16-bit offset.
It can be only source or only destination.

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E.g.: MOV CX,23h[DI] copies a 16-bit data from word location given by (23h+DI) to CX. Assuming
DI=212h, EA=212h+23h=245h, DS=1000h we get PA=10245h.
E.g.: MOV 1000h[BP],SI moves a 16-bit data present in SI to the EA derived by (1000h+BP). PA is
calculated by using SS as segment register.
E.g.: MOV DS:[BP]23h,SI here PA is calculated from DS.

6) BASED INDEXED ADDRESSING MODE:


EA of the operand is given by a base register and indexed register as (BX or BP) + (SI or DI).
It can only be source or destination.
E.g.: MOV [BX+DI],23h copies 23h to the EA got from [BX+DI].

7) BASED INDEXED WITH DISPLACEMENT ADDRESSING MODE:


EA is derived from the base register, indexed register and 8 or 16-bit signed offset.
It can be only source or only destination.
EA = (BX or BP) + (SI or DI) + 8 or 16-bit offset
E.g.: MOV 23h[BP+SI],AL copies one byte of data from AL to EA obtained by [BP+SI+23h]. PA =
DS:EA.
NOTE: If BP is used then SS will be default segment register for PA calculation.

I/O PORT ADDRESSING:

1) Fixed port addressing:


The address of the port is provided in the instruction.
For byte transfer AL is the default register. For word operations AX will be default operations and data
will be read from two consecutive locations.
E.g.: IN AL,82h reads an 8-bit data from port address 82h.
E.g.: IN AX,82h reads 2 byes from 82h and 83h in AL and AH.
Similarly OUT 82h,AL and OUT 82h,AX is used to write data to the port.

2) Variable port addressing:


Address of the port is specified in DX register.
For byte transfer use AL and for word transfer use AX register.
E.g.: IN MOV AL,DX. In this, EA = DX one byte is read from the address into AL.
E.g.: IN AX,DX reads one word from address in DX into AX.
OUT DX,AL or OUT DX,AX is similarly, used to write to output port.

Machine language Instruction fomat

The instruction format of 8086 has one or more number of fields associated with it.

The first filled is called operation code field or opcode field, which indicates the type of operation. The
instruction format also contains other fields known as operand fields.There are six general formats of
instructions in 8086 instruction set. The length of an instruction may vary from one byte to six bytes.

a) One byte Instruction : This format is only one byte long and may have the implied data or register operands.
The least significant 3 bits of the opcode are used for specifying the register operand, if any. Otherwise, all the
eight bits form an opcode and the operands are implied.

For example:

11111000 F 8H CLC : clear carry

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This is an operation without any operand, which clear the carry flag bit.

10010 reg
Exchange register with accumulator

Depending on the register (reg = RRR), the contents of the specified register will be exchanged with the
accumulator. This operation is having one operand which is specified in a register.

ASCII Adjust for addition AAA 00110111 37 H

Here the operand to this instruction is implicit and it take the contents of register AL.

b) Register to Register : This format is 2 bytes long. The first byte of the code specifies the operation code and
the width of the operand specifies by w bit. The second byte of the opcode shows the register operands and RIM
field.

D7 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

OP CODE D w 11 REG R/M


WWWWW

The register represented by the REG field is one of the operands. The RIM field specifies another register or
memory location, ie., the other operand. The register specified by REG is a source operand if D 0 , else it is a
destination operand.

For example:

MOV : data transfer operation from Register to Register.

Op-code is

100010dw 1 1 R E G R/M
10001000 11 000 001 88H C1H

REG = 0 0 0 indicates Register AL

REG = 0 0 1 indicates Register CL

w0 indicates it is a byte operation (8 bit)

d 0 indicates AL is a source register.

This instruction indicates MOV CL, AL, i.e CL AL

C) Register to/from memory with no displacement : This format is also 2 bytes long and similar to the register to
register format except for the MOD field.

D7 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

OP CODE d w MOD REG R/M


WWWWW
The MOD field shows the MOD of addressing. In case of no displacement. MOD = 00

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For example :

MOV : Data transfer Register/memory to/from register.

100010dw mod reg rim

This format is similar to register to register transfer. The difference is in mood field.

For register to register, mod = 11

For register to/from memory with no displacement, mod = 00.

When mod = 0 0, the r/m fields indicates the address to memory location.

As for example r/m = 1 1 1 indicates (Bx)

The instruction

1 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 indicates the instruction MOV AX, [BX]

In hexadecimal, the instruction is 8 AH O7 H

Here the data is present in a memory location in DS whose offset address is in BX. The effective address of the
data is given as 10H DS BX

There d 1 indicates AX is a destination register so it moves the data from memory to register.
d) Register to/from Memory with Displacement :

This type of instruction format contains one or two additional bytes for displacement along with 2-byte the
format of the register to/from memory without displacement.

D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0

opcode MOD REG R/M Low byte of


displacement

D7 D0
High byte of
displacement
MOD = 0 1 indicates displacement of 8 bytes (instruction is of size 3 bytes)

MOD = 1 0 indicates displacement of 16 bytes. (instruction is of size 4 bytes)

Already we have seen the other two options of MOD

MOD = 1 1 indicates register to register transfer

MOD = 0 0 indicates memory without displacement

In this case, R/M fields indicates a memory when MOD is not 1 1

R/M = 1 1 1 indicates (BX)

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When MOD = 0 1, the offset address is BX D8


When MOD = 1 0, the offset address is BX D16
e) Immediate operand to register

In this format, the first byte as well as the 3 bites from the second byte which are used for REG field in case of
register to register format are used for opcode. It also contains one or two bytes of immediate data.

D7 D0 D7 D6 D5 D4 D3 D2 D1 D0

Op code w 11 op code R/M

D7 D0 D7 D0
Lower byte Higher byte DATA
DATA

When w 0 , the size of immediate data is 8 bits and the size of instruction is 3 bytes.

When w 1 , the size of immediate data is 16 bits and the size of instruction is 4 bytes.

f) Immediate operand to memory with 16-bit displacement : This type of instruction format requires 5 to 6 bytes
for coding. The first two bytes contain the information regarding OPCODE, MOD and R/M fields. The
remaining 4 bytes contain 2 bytes of displacement and 2 bytes of data.

D7 D0 D7 D6 D5 D4 D3 D2 D1 D0

Op code w MOD op code R/M

D7 D0 D7 D0 D7 D0
Lower byte of Higher byte of Lower byte of Higher byte of
displacement displacement Immediate data Immediate data

DATA

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The REG code of the different registers (either a source or destination operands) in the opcode byte are assigned
with binary code.

operands Memory operands Register operands

No Displacement Displacement
Displacement
8 bits 16 bits

MOD 00 01 10 11

RIM w0 w 1

000 BX SI BX SI D8 BX SI D16 AL AX

001 BX DI BX DI D8 BX DI D16 CL CX

010 BP SI BP SI D8 BP SI D16 DL DX

011 BP DI BP DI D8 BP DI D16 BL BX

100 SI SI D8 SI D16 AH SP

101 DI DI D8 DI D16 CH BP

110 D16 BP D8 BP D16 DH SS

111 BX BX D8 BX D16 BH DI

Data Transfer Instructions

Note : Data transfer instructions do not affect any flags


Data Transfer Between CPU and the Memory

Memory Write:

Byte Transfer: move BYTEPTR ds : [SI], 37H

Word Transfer: move WORDPTR ds : [SI], 1237H

Memory Read:

Byte Transfer: move al, BYTEPTR ds : [SI]

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Transfers data from the physical memory address calculated using ds and [SI] to register

AL ( Lower byte of AX Register)

Word Transfer: move ax, WORDPTR ds : [SI]

Transfers data from the physical memory address calculated using ds and [SI] to register

AL ( Lower byte of AX Register) and the next byte from the next memory location

calculated as ds:[SI +1] is transferred to AH ( Higher byte of AX Register)

Memory operation through ax Register

Write:

MOV AX , 1234H

MOV WORD PTR DS: [SI], ax

DS: 0000H

SI: 0500H

Physical Address: 00000+0500= 00500 H

The instruction transfers

34 00500H

12 00501H

Read:

MOV ax, WORD PTR ds: [SI]

DS: 0000H

SI: 0500H

Physical Address: 00000+0500= 00500 H

The instruction transfers

AL (00500)

AH (00501)

Data Transfer Between CPU and the Port

Port addresses in 8086 are assigned either 8bit port address or 16 bit address

For a Port with 8bit port address:


Read Operation:

IN Instruction - This IN instruction will copy data from a port to the AL or AX register.

For the Fixed port IN instruction type the 8 bit port address of a port is specified directly in the instruction.

Example:

IN AL,0C8H ;Input a byte from port 0C8H to AL

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IN AX, 34H ;Input a word from port 34H AND 35H to AL and AH resp.

For a variable port IN instruction, the port address is loaded in DX register before IN instruction. DX is 16 bit.

Port address range from 0000H FFFFH.

Example:

MOV DX, 0FF78H ;Initialize DX point to port

IN AL, DX ;Input a byte from a 8 bit port 0FF78H to AL

IN AX, DX ;Input a word from 16 bit port to 0FF78H to AX.

Write Operation:

OUT Instruction - The OUT instruction copies a byte from AL or a word from AX or a double from the
accumulator to I/O port specified by op. Two forms of OUT instruction are available : (1) Port number is
specified by an immediate byte constant, ( 0 - 255 ).It is also called as fixed port form. (2) Port number is
provided in the DX register ( 0 65535 )

Example:

(1)OUT 3BH, AL ;Copy the contents of the AL to port 3Bh

OUT 2CH,AX ;Copy the contents of the AX to port 2Ch

(2) MOV DX, 0FFF8H ;Load desired port address in DX

OUT DX, AL ; Copy the contents of AL to FFF8h

OUT DX, AX ;Copy content of AX to port FFF8H

LAHF Instruction - Copy low byte of flag register to AH

LAHF instruction copies the value of SF, ZF, AF, PF, CF, into bits of 7, 6, 4, 2, 0 respectively of AH register.

LDS Instruction - Load register and DS with words from memory

LDS register, memory address of first word

This instruction loads a far pointer from the memory address specified by op2 into the DS segment register and
the op1 to the register.

LDS op1, op2

LDS BX, [4326] ; copy the contents of the memory at displacement 4326H in DS to BL, contents of

the 4327H to BH. Copy contents of 4328H and 4329H in DS to DS register.

LES Instruction - Load register and ES with words from memory LES register, memory address of

first word.

LDS Instruction - This instruction loads a far pointer from the memory address specified by op2 into the DS

segment register and the op1 to the register. LDS op1, op2

Example:

LDS BX, [4326] ; copy the contents of the memory at displacement 4326H in DS to BL, contents of

the 4327H to BH. Copy contents of 4328H and 4329H in DS to DS register.

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LEA Instruction - This instruction indicates the offset of the variable or memory location named as the source
and put this offset in the indicated 16 bit register.

Example:

LEA BX, PRICE ;Load BX with offset of PRICE in DS

LEA BP, SS:STAK;Load BP with offset of STACK in SS

LEA CX, [BX][DI] ;Load CX with EA=BX + DI

SAHF Instruction Copy AH register to low byte of flag register

SAHF copies the value of bits 7, 6, 4, 2, 0 of the AH register into the SF, ZF, AF, PF, and CF respectively.

Can be used to clear lower byte of flag register.

XCHG Instruction - The Exchange instruction exchanges the contents of the register with the contents of

another register (or) the contents of the register with the contents of the memory location. Direct memory to
memory exchange are not supported. It can exchange two bytes or two words.

XCHG op1, op2

The both operands must be the same size and one of the operand must always be a register .

Example:

XCHG AX, DX ;Exchange word in AX with word in DX

XCHG BL, CH ;Exchange byte in BL with byte in CH

XCHG AL, M [BX] ;Exchange byte in AL with byte in memory at EA.

POP Instruction - POP instruction copies the word at the current top of the stack to the operand specified by op
then increments the stack pointer to point to the next stack element.

Example:

POP DX ;Copy a word from top of the stack to DX and increments SP by 2.

POP DS ; Copy a word from top of the stack to DS and increments SP by 2.

POP TABLE [BX] ;Copy a word from top of stack to memory in DS with EA = TABLE + [BX].

POPF Instruction - Pop word from top of stack to flag -register.

This instruction copies a word from the two memory location at the top of the stack to flag register

and increments the stack pointer by 2.

POP AX :If AX=1234h

Before execution

45
67
ab SP =
cd 200h

After execution AX= 6745h and SP incremented twice. SP= 202h

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45
67
ab SP =
cd 202h

PUSH Instruction - PUSH instruction decrements the stack pointer by 2 and copies a word from a specified
source to the location in the stack segment where the stack pointer pointes.

Example:

PUSH BX ; Decrement SP by 2 and copy BX to stack

PUSH DS ; Decrement SP by 2 and copy DS to stack

PUSH TABLE[BX] ;Decrement SP by 2 and copy word ;from memory in DS at EA = TABLE + [BX] to

;stack .

PUSHF Instruction - This instruction decrements the SP by 2 and copies the word in flag register to the memory

location pointed to by SP.

Push AX :If AX=1234h

Before execution AX= 1234h is placed on stack (little Endian) and SP decremented twice. SP= 0feh

SP
After execution
100h

34 SP =
12 0feh

ARITHMETIC INSTRUCTIONS

1) ADD
1. Add the contents of two registers or register and memory location or immediate data to reg/memloc

OP-CODE D W

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The notations and the respective combinations are as follows:-


BIT(S) VALUE MEANING

D 1 REG field has destination register

0 REG field has source register

W 1 Word operation

0 Byte operation

MOD 11 Both CPU registers

00 One register and the other is memory location

01 One is register and other is memory location with 8 bit signed


offset
10 One is register and other is memory location with 16 bit
signed offset

E.g.: ADD AX,BX


This instruction is a 2 byte instruction. This adds the contents of BX register with that of AX and stores
the result in AX. This affects all flags.
Instruction is:

OP-CODE D W MOD REG R/M

0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1

Hence the code word for the above case becomes 03C3h. This can also be written considering the source in
REG field ,

OP-CODE D W MOD REG R/M

0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 0

This gives the word as 0108h.


Note Assembler generates on of the code randomly.

ADD AX,BX
AX=2ABCh and BX=1FFFh. Upon addition we get 4ABBh as the result.
Before execution After execution
AX 2ABCh 4ABBh
BX 1FFFh 1FFFh

The various flag status are Z=0, S=0, C=0, AC=1, P=1 and OV=0.

ADD [SI],BL

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This adds an 8 bit number in BL with memory location pointed by SI. The result is stored back in
memory.

2. Adding immediate data to a register or a memory location:

OP-CODE S W MOD OP-CODE R/M

0 0 0

Here, the S bit is present. This is known as the sign extension bit. It is 0 for byte operation. When this is 1
and the W bit is also 1, if immediate data is <= 7Fh, assembler generates only one byte for immediate, but
during execution it is converted into word by sign extension.
If S=0 and W=1 then, if immediate data > 7Fh, the assembler generates 2 byte code for the immediate data.
E.g.: ADD DX , 92h ; This adds 92h to the contents of DX register

OP-CODE S W
MOD OP-CODE R/M
1 0 0 0 0 0 0 1
1 1 0 0 0 0 1 0

This code will be followed by the actual immediate data that is being used and hence the total code will be
81C20092h.
E.g.: ADD DX,67h
OP-CODE S W MOD OP-CODE R/M

1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0

Hence, the total code will be 10000011 11000010 with the number to be added i.e. 67h.
Hence, code = 80C023h.

3. Adding immediate data to the accumulator

0 0 0 0 0 1 0 W

Here, when W=1 it implies AX and when W=0, it implies AL.


E.g.: ADD AX,1234h
ADD AL, 12h

2) ADC
This stands for add with carry. This is used for multi byte or multi word addition.
E.g.: ADC 23h[DI],DX
This adds the contents of [23h+DI] along with the carry to DX. The result is stored back in the memory
location. All flags are affected.
Considering that [DI+23h] has the data 5000h and DX has 6000h,
Before execution After execution
DX 6000h 6000h
DS:23h[DI] 5000h B000h

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Microprocessor CBCS IV sem

NOTE: Both ADD and ADC consider only carry for unsigned operation and both sign and overflow flags
for unsigned addition.]
OV=1 can occur when we add 2 numbers of same sign
For 8 bit addition, OV = C6 XOR C7.
For 16 bit addition, OV = C14 XOR C15.
E.g.: ADC CL, DL ; This adds DL content to CL content with carry.
ADC AX, 67h
ADC [DI+BX], 0ABCDh

3) INC

Adds one to the destination operand.


Destination can be CPU register or memory location of byte or word capacity.
Affects all flags except carry.
E.g.: INC SI
This adds 1 to SI content. If SI=2000h before execution, then after execution it will have become
2001h.
E.g.: INC word ptr DS:[BP+100h]
This adds one to the word data pointed by BP+100h in data segment.
E.g.: INC byte ptr [DI]
This adds 1 to the byte data pointed by DI.
If content of the register or memory location is FFh or FFFFh then after INC instruction and they are
changed to 00h and 0000h respectively and the C = 0 (does not change).

4) DAA

This stands for Decimal Adjust after Addition.


This is used for BCD arithmetic.
This works only on AL.
After addition if lower nibble of AL is invalid BCD or if AC=1, then it adds 6 to lower nibble.
After addition if upper nibble of AL is invalid BCD or if C=1, then it adds 6 to upper nibble.
If both the above conditions are true, then it adds 66h else there will be no change.

E.g.:
MOV AL, 67h
MOV BL, 78h
ADD AL,BL ; 67h + 68h = DFh
DAA ; add 66h to AL

After this, we get the value as 1 45. In this, 1 will be stored as Carry and 45 will be stored in AL.

5) AAA

This stands for ASCII Adjust after Addition.


Numbers keyed in from standard input (keyboard) are in ASCII form i.e. 0 to 9 is got as 30 to 39h.
When we add 2 ASCII numbers, to get the result back in ASCII format, AAA is used.
Consider AL=38h and BL=36h. When added using the statement ADD AL, BL the value of AL becomes
6Eh. On executing AAA, following steps are done,

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a) If lower nibble of AL is invalid BCD or AC=1, adds 06 to AL.


b) Upper nibble of AL is cleared.
c) AH is incremented by 1 if carry is produced.
d) Sets AC and C flags.
The execution steps are:
38h+36h gives 6E. 6Eh gets added with 06h to give 0102h. In this, AH gets 01h and AL gets 02h. Now
AX=0102h. Adding 3030h to AX, we get 3132h representing the needed answer in ASCII format.
Both DAA and AAA work on only bytes and the answer must be in AL.

SUBTRACT GROUP OF INSTRUCTIONS

The various instructions are SUB, DAS, AAS and DEC.

1) SUB
Subtracts the contents of source from the destination.
It can operate on 8 bit and 16 bit data.
Operands can be both CPU registers, CPU register and memory location or register or memory location
with immediate data.
Flags affected are Z, P, C,S, AC, for unsigned arithmetic. For signed arithmetic, OV and S are to be
considered.
OV=1 can occur when two numbers of opposite sign are subtracted.
For 8 bit subtraction, OV = B6 XOR B7.
For 16 bit subtraction, OV = B14 XOR B15.
E.g.: SUB AX, 67h (unsigned)
AX=ABh and 67h is subtracted from this.
Before execution After execution
AX ABh 44h

The various flag status are C=0, A=0, P=1 and Z=0.
E.g.: SUB AX, 67h (signed)
AX=ABh and 67h is subtracted from this.
Before execution After execution
AX ABh = (-55h) 44h

The various flag status are C=0, A=0, P=0, Z=0, OV=0.
E.g.: SUB word ptr [DI], 1234h
Before execution After execution
[DI] 6789hh 5555h

The various flag status are C=0, A=0, P=1, Z=0, OV=0.
2) SBB
This stands for Subtract with Borrow.
E.g.:SBB CX, DX
Considering that CX has 1234h and DX has 5678h,
Before execution After execution
CX 1234h BBBCh
DX 5678h 5678h
Flag affected are S=1, OV=0, P=0, C=1, A=1, Z=0.

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E.g.:SBB CX, DX
Considering that CX has 5678h and DX has 1234h,
Before execution After execution
CX 5678h 4443h
DX 1234h 1234h

3) DAS
This stands for Decimal Adjust after Subtraction.
It is used for BCD subtraction.
Works on AL and 8 bit data.
After subtraction if lower nibble of AL is invalid BCD or if AC=1, then it subtracts 6 to lower nibble.
After subtraction if upper nibble of AL is invalid BCD or if C=1, then it subtracts 6 to upper nibble.
If both the above conditions are true, then it subtracts 66h else there will be no change.
It sets carry flag and the result is in 10s complement form.
E.g. code 1:
MOV AL, 76H
MOV BL, 48H
SUB AL, BL; AL = 76H 48H = 2EH
DAS; 2E 06H = 28H in AL
E.g. code 2:
MOV AL, 48H
MOV BL, 76H
SUB AL, BL; AL = 48h-76h = D2h
DAS; AL = D2h 60h= 72h which is 10s complement of 28h

4) AAS
When 2 ASCII numbers are to be subtracted and the result should be in ASCII format AAS is used.
It is used after subtraction and works only on 8 bit data.
It does following steps:
a) If lower nibble of AL is invalid BCD or AC=1, subtracts 06 to AL.
b) Upper nibble of AL is cleared.
c) AH is decremented by 1 if carry is produced.
d) Result is in 10s complement form.
E.g.: Al=34h, BL = 37h
SUB AL, BL; AL= 64h 37h = FDh
AAS; AL=0Dh 06h = 07h
; AH=FFh in 10s complement form AL = -3h.
E.g.: Al=39h, BL = 33h
SUB AL, BL; AL= 39h 33h = 06h
AAS; AL=06h as all are valid

5) DEC

This is the mnemonic for decrement instruction.


This subtracts one from the destination i.e. destination = destination 1.
Data can be in CPU registers or in memory location.
It affects all flags except carry.

E.g.: DEC DX
Before execution After execution
DX FFFFh FFFEh

Flags status are Z=0, P=0, S=0, OV=0, AC=0.

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E.g.: DEC byte ptr DS:[BP+2]


Before execution After execution
DS:[BP+2] 00h FFh

6) CMP (compare)

Compare two 8-bit/16-bit number. It can compare data between two regs, reg and mem location or immediate
data with mem location content. I works like SUB instruction all flags are affected but the result is not recorded.

E.g.: CMP AX, 67h (unsigned)


AX=ABh and 67h is subtracted from this.
Before execution After execution
AX ABh ABh

The various flag status are C=0, A=0, P=1 and Z=0.
E.g.: SUB AX, 67h (signed)
AX=ABh and 67h is subtracted from this.
Before execution After execution
AX ABh = (-55h) ABh = (-55h)

The various flag status are C=0, A=0, P=0, Z=0, OV=0.
E.g.: SUB word ptr [DI], 1234h
Before execution After execution
[DI] 6789hh 6789h

The various flag status are C=0, A=0, P=1, Z=0, OV=0.

MULTIPLY INSTRUCTIONS:
This is of two types, signed and unsigned. Signed multiplication is done using IMUL instruction and
unsigned is done using MUL.
This can multiply 2 bytes or 2 words.
For byte operation one operand must be AL and the second can be in any byte memory location or byte
register. The 16 bit product will be in AX.
For word operation, one operand must be in AX register. The other can be in any word register or word
addressable memory location. The result will be in DX AX pair with higher word in DX and lower in AX.
For unsigned multiplication, C=OV=1 if AH <> 00h for byte operation and DX <> 0000h for word
operation.
E.g.: MUL CX
Before execution After execution
AX 1234h 5328h
CX 0672h 0672h
DX FFFFh 0075h
Multiplies AX data with CX data and result is 32 bit.
This is done as (AX * CX) and the result is stored in (DX AX).
E.g.: MUL byte ptr [SI]
Before execution After execution
[SI] 72h 72h
AL ABh 26h
AH 00h 4Ch
This is done as (AL * [SI]) and result is stored in AX.

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Microprocessor CBCS IV sem

For signed multiplication, C=OV=1 if AH <> 00h or FFh for byte operation and DX <> 0000h or FFFFH
for word operation.

E.g.: IMUL word ptr 22h[DI]


Before execution After execution
22h[DI] ABCDh = (-5433h) ABCDh
AX 7256h 00DEh
DX 0000h DA65h

2)AAM

This is the mnemonic for ASCII Adjust after Multiplication.


It is used for multiplication of 2 ASCII numbers.
It works only on AL.
Converts an 8 bit hex number in AL to unpacked BCD in AX.
E.g. code:
MOV AL, 05h
MOV BL, 06h
MUL BL; AL = 05h*06h=2Eh
AAM; AX = 0300h
If we add 3030h to AX, we get 3330h which is the ASCII value of 30h.

DIVIDE INSTRUCTIONS

1) Unsigned division (DIV):


It divides a 16 bit number (stored in AX) by a 8 bit number (which is either in memory location or
register).8 bit quotient will be in AL and the 8 bit remainder will be in AH.OV=1 if quotient is greater
than FFh (overflow error).
It can also divide a 32 bit number (in DX AX pair) by a 16 bit number (present in a word register or
memory location). The 16 bit quotient is placed inn AX and the 16 bit remainder in DX register. OV=1
if quotient is greater than 0FFFFh.

E.g.: DIV CL
Before execution After execution
AX 8000h AH = 84h
CL A4h AL = C7h

E.g.: DIV word ptr [SI]


Before execution After execution
[SI] 7FABh 7FABh
AX 2000h Quotient (1E14h)
DX 0F00h remainder

2) Signed division (IDIV):


This does signed division between the numbers specified. The instruction has a mnemonic
IDIV.
It divides a 16 bit signed number (stored in AX) by a 8 bit signed number (which is either in
memory location or register).8 bit quotient will be in AL and the 8 bit remainder will be in
AH.OV=1 if quotient is more positive than 7Fh or more negative than 80h (overflow error).
It can also divide a 32 bit signed number (in DX AX pair) by a 16 bit signed number
(present in a word register or memory location). The 16 bit quotient is placed inn AX and the

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Microprocessor CBCS IV sem

16 bit remainder in DX register. OV=1 if quotient is positive than 7FFFh or more negative
than 8000h (overflow error).

DIVIDEND DIVISOR QUOTIENT REMAINDER

+ve +ve +ve +ve


+ve -ve -ve +ve
-ve +ve -ve -ve
-ve -ve +ve -ve

E.g.: IDIV CX
Before execution After execution
CX ABF0h FFB0h
AX 0FE0h 0300h
DX FFFFh FFE0h

3) AAD (ASCII ADJUST BEFORE DIVISION):


If we want to divide 62h by 8h, 62 h in ASCII is 3632h and this is stored in AX. This is first subtracted
by 3030h. Hence, the value becomes 3632h 3030h = 0602h. Upon usage of AAD instruction, this
converts the unpacked BCD into equivalent hex value of 8 bit in AL.
AX=0602h becomes 3Eh (hex equivalent) in AL. Now, the division by 8h can be done.
(AX/BL)=(003Eh/8h) gives AL (quotient) = 07h and the remainder as 06h in AL.

4) NEGATE (NEG):
It obtains 2s complement of a given number.
It can work on 8 bit or 16 bit data in register or memory location.
E.g.: NEG DX
Before execution After execution
DX 5050h AFB0h

This affects overflow flag. OV=1 if 80h and 8000h

Historical Background

The mechanical age:

In 500BC Babylonians invented ABACUS- first mechanical calculator. 1642- Mathematician Blaise Pascal
invented a calculator constructed of gears and wheels. Then it was program calculator in 1937. Analytric engine
is a mechanical computer that stored 1000, 20 digit decimal numbers.

The Electrical age:

1800- Electrical motor by Micheal faraday.


1889- Herman Hollerith developed the punched cards for storing data
1896- Hollerith formed a company called the tabulating machine company
1941-23 calculating computer developed bya German inventor, used in World War II.i
1946- General purpose programmable electronic computer called ENIAC (Electronics Numerical Integrator and
Calculator). Which was programmed by rewiring its circuits and another problem is life of vacuum tubes,
required frequent maintenance.
Programming Advancements:

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Microprocessor CBCS IV sem

Languages to control computers- the first machine language, which was constructed of ones and zeros. In
1950s Assembly language was used. Then its FORTRAN (Formula Transistor), which allowed formulas to
solve mathematically. The additional languages are BASIC, C/C++, PASCAL, ADA.

The microprocessor age:

Intel 4004 was the first 4-bit microprocessor. It had 4096, 4-bit wide memory instructions. In 1971 Intel
introduced 8008 extended 8 bit version of 4004. In 1977, Intel introduced 8085, an 8-bit microprocessor. In
1978, Intel released a 16-bit microprocessor, which executed instructions as little as 400ms and 1MB memory.

80286- microprocessor with 16mb memory,


80386- 4GB memory and 32-bit processor.
80486- 33 bit processor with 4GB with 8K cache.
Pentium- 64-bit microprocessor
Microprocessor based personal computer system

Memory Microprocessor I/O system


System

Dynamic RAM (DRAM) 8086 Printer


Static RAM (SRAM) 8088 serial communication
Cache 80286 Floppy disk drive
Read only (ROM) 80386 Hard disk drive
Flash 80486 Mouse
EEPROM Pentium CD-ROM
SDRAM Pentium-II Keyboard
RAMBVS Pentium-III Monitor
Pentium-IV DVD

Fig 1: Block diagram of microprocessor based personal computer system

The block diagram is composed of three blocks that are interconnected by buses. The memory structures of all
Intel 80x86 Pentium 4 personal computer systems are similar. The memory system is divided into 3 main
parte: TPA (transient program area), System area and XMS (extended memory) .

TPA 640Kbytes
System area- 384Kbytes
XMS- 15Mbytes

Branch Instructions

8086 branch instructions can be classified into 3 categories namely:

Unconditional (equivalent to goto of C)

Conditional branch (depending on flags)

Iterative ( for implementation of loops.

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Microprocessor CBCS IV sem

Unconditional Jump Instruction

The execution of the instruction always results in branching. It can be within the same segment then
it is called NEAR jump or an INTRASEGMENT jump. There are three types of near jumps

a. NEAR jump with 1 byte signed displacement( or short jump)

b. NEAR jump with 2 byte signed displacement

c. NEAR jump of Indirect type (destination address in a register or a memory location)

Branching to a different code segment is called FAR jump or an INTERSEGMENT jump.

a. FAR Direct jump

b. FAR INDIRECT jump

JMP Intrasegment Relative Short Jump

It is 2 Byte instruction , first byte is opcode and second provides the displacement (+/-
127B)

back: sub ax,bx

jmp Back

next : mov ax,cx

As it is backward jump assembler calculates the displacement, if displacement is <=128


bytes the instruction is coded as EBh with one byte displacement, if displacement is
>128 bytes then it is coded as E9h with two byte displacement.

Jmp next

next: sub ax, bx

For a forward branch the exact displacement will not be known during the first pass of the
assembler. Assembler codes it as EBh and reserves two bytes (worst case displacement of 2
bytes). Later (during second pass) when the actual displacement is calculated if the
displacement is <127 then the displacement is stored in one byte and the other byte filled
with NOP. But if the actual displacement is >127 bytes then the assembly code is E9h
followed by 2 byte displacement.

Conditional Branch Instructions

Conditional branch instructions in 8086 are based on single flag , two or three flags. The table
summarises all conditional bramch instructions.

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SL.NO INSTRUCTION FLAG SCOPE EXAMPLE


SUB AX,BX
JZ nxt
INC CH; z =0

Nxt: INC CL ; z =1
JZ/JE
1. Z-flag =1 -127 B to
Jump on Zero/ Jump if equal
-128B CMP AX,BX
JE nxt ; AX!=BX

Nxt: ;AX==BX

JNZ / JNE SUB AX,BX


2. Z=0 -127 B to
Jump if not zero/ JNZ last
-128B
Jump if not equal CMP DX,SI
JNE last
SUB AX,BX
JS S=1 -127 B to JS Last ; S=0 , result
3.
Jump if Sign flag = 1 (-ve result) -128B +ve
Last: ; S=1
SUB AX,BX
JNS end1 ; S=1
JNS S=0 -127 B to
4.
Jump if no sign flag (+ve result) -128B
end1: ; S=0
SUB AX,BX
JO O=1 -127 B to JO last ; O=0
5.
Jump on over flow -128B
Last: ;O=1
SUB AX,BX
JNO O=0 -127 B to JNO last ; O=1
6.
Jump if no overflow -128B
Last: ; O=0
SUB AX,BX
JC last

JC Jump if Carry is set -127 B to Last: ;c=1


7. JB- Jump if Below C=1 -128B
JNAE - Jump if above or equal CMP AX,BX
JB endl

endl: ;ax<bx
JNC - Jump if no carry -127 B to SUB AX,BX
8. C=0
JAE/JNB - Jump if no above or -128B JNC last
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Microprocessor CBCS IV sem

equal/Jump if not equal


Last: ;c=0 AX>BX

CMP AX,BX
JAE endl

Endl: ;ax>=bx C=0


ADD ax,bx
-127 B to JP last ; P=0
9. JP Jump on parity P=1(even)
-128B
Last: ;P=1 (even parity)
ADD ax,bx
-127 B to JNP last ; P=1
10. JNP Jump on no parity P=0(odd)
-128B
Last: ;P=0
SUB ax,bx
JBE last
Nxt instruction ;C=0,Z=0
JBE - Jump if below or equal -127 B to (ax>bx)
11. C=1 or Z=1
JNA- Jump if not above -128B

Last: ; C=1 or Z=1


(ax<=bx)
SUB ax,bx;
JNBE Jump if not above or JA last
12. -127 B to
equal C=0 or Z=0
-128B
JA - Jump if above Last: ;C=0 & Z=0
(ax>bx)
SUB al,bl al=33h, bl=43h
S<>0 or Z=1 JLE last
JLE - Jump if less than or equal -127 B to
13. S not equal to Last: ; S=1 O=0
JNG - Jump if not greater -128B
OF (ax<bx)
(al=43h bl=43h Z=1 control
goes to target)
JNLE Jump if not less than or
SUB ax,bx ; ax=43h, ax=33h
equal S==0 -127 B to
JG last
JG Jump if greater than & Z=0 -128B
Last: ;S=0 ,Z=0 ,O=0
SUB al,bl ; al=34h,bl=43h
JL Jump if less
-127 B to JL Last
15. JNGE Jump if not greater than S<>0
-128B
or equal
Last: ; S=1,O=0,al<bl
SUB al,bl ;al=34h, bl=17h
JNL Jump if not less -127 B to JGE Last
16. S==0
JGE - Jump if greater or equal -128B
Last: ; S=1,O=0,al>bl

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Microprocessor CBCS IV sem

LOOP Instruction (LOOP, LOOPE, LOOPZ, LOOPNE, LOOPNZ):

The LOOP instruction is a combination of a decrement of CX and a conditional jump. In the


8086, LOOP decrements CX and if CX is not equal to zero, it jumps to the address indicated
by the label. If CX becomes a 0, the next sequential instruction executes.

Conditional LOOPS: The LOOP instruction also has conditional LOOPE and LOOPNE. The
LOOPE (loop while equal) instruction jumps if CX is not equal to zero, while an equal
condition exists. It will exit the loop if the condition is not equal or if the CX register
decrements to 0. The LOOPNE (loop while not equal) instruction jumps if CX is not equal to
zero, while a not equal condition exists. It will exit the loop if the condition is equal or if the
CX register decrements to 0. As with the conditional repeat instructions, alternates exist for
LOOPE and LOOPNE.

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