Handout: # 03
- To write this matrix in a systematic way, an arbitrary orientation is specified for each
loop using an ordered list of its branches and nodes.
- The total number of loops are determined using an exhaustive search.
The elements of the complete loop/circuit matrix have the following values:
1, if the branch j is in the loop i and their orientations coincide,
bij = 1, if the branch j is in the loop i and their orientations are opposite,
0, if the branch j is not in the loop i.
IL L
a
R1 R2
I1 2 I2 b 2 c
1 3 1 3
Is I3
IC
Vs + C R3 d e f
4 4
(a) (b)
2060720-02#20160829LJS 1/5
L. Joyprakash Singh, PhD EE - 304 ENT August 29, 2019
Let us try to find out the possible loops/circuits in the given graph: Thus, all possible
a a a a
2 b 2 c 2 c 2
1 c 3 1 3 1 3 1 c 3
b b b
L2 L3 L4
d e f d e f d e f d e f
4 4 4 4
(a) Loop 1: L1 {a,c,b} (b) Loop 2: L2 {b,e,d} (c) Loop 3: L3 {c,f,e} (d) Loop 4: L4 {a,f,d}
a a a
b 2 c 2 2 c
1 3 1 c 3 1 3
b b
L6 L7
d e L5 f d e f d e f
4 4 4
Fig. 1.2: (a)-(g) are all possible loops/circuits of the graph of Fig. 1.1(b).
loops are:
Loop 1: L1 {a,c,b} Circuit 1: L1 {a,c,b}
Loop 2: L2 {b,e,d} Circuit 2: L2 {b,e,d}
Loop 3: L3 {c,f,e} Circuit 3: L3 {c,f,e}
Loop 4: L4 {a,f,d} or Circuit 4: L4 {a,f,d}
Loop 5: L5 {b,c,f,d} Circuit 5: L5 {b,c,f,d}
Loop 6: L6 {a,c,e,d} Circuit 6: L6 {a,c,e,d}
Loop 7: L7 {a,f,e,b} Circuit 7: L7 {a,f,e,b}
Taking the clock-wise orientation, the complete loop matrix, BC , of the above graph
may be written as
Branches
a b c d e f
Circuits
L1 b11 b12 b13 b14 b15 b16
L2
b21 b22 b23 b24 b25 b26
L3
b31 b32 b33 b34 b35 b36
BC = L4
b41 b42 b43 b44 b45 b46
L5
b51 b52 b53 b54 b55 b56
L6 b61 b62 b63 b64 b65 b66
L7 b71 b72 b73 b74 b75 b76
Branches
Loops a b c d e f
1 1
L1 1 0 0 0
L2
0 1 0 1 1 0
L3
1 1 0 0 1 1
BC = L4
1 0 1 1 1 0
L5
0 0 1 0 1 1
L6 1 0 0 1 0 1
L7 0 1 1 1 0 1
f -circuits : L1 {a,b,c}
4 : L2 {b,d,e}
: L3 {a,b,e,f}
Fig. 1.3: A tree with twigs{a,b,e}.
Note: Every link defines a fundamental loop of the graph.
b 2 c b IL1 2 b 2 b 2
1 3 1 c 3 1 3 1 3
IL3
L2
d e f e d e e f
4 4 4 4
Branches
f -Loops a b c d e f
L1 1 1 1 0 0 0
B= L2 0 1 0 1 1 0
L3 1 1 0 0 1 1
Example - 3: Obtain a tie-set from the following graph of Fig. 1.4(a) in which twigs
are specified by solid lines while links dashed lines:
a a
I
b 2 c b 2 L1 b 2 c b 2 c
1 3 1 c 3 1 3 1 3
L2 IL3
d e f e d e e f
4 4 4 4
Fig. 1.4
f circuit : L1 {a, c, b}
f circuit : L2 {d, b, e}
f circuit : L3 {f, e, c}
Links T wigs
branches
a d f b c e
f circuits
1 1 0 0 1 1 0
B= 2 0 1 0 1 0 1
3 0 0 1 0 1 1
B = [Bl Bt ] = [U, Bt ]
where Bl is a square matrix for links having order (n 1) (n 1) and is the identity
matrix. And Bt is a matrix of order (n 1) (b n + 1) which corresponds to the
twigs. Hence, B is a non-singular matrix. Therefore, the rank of B is (b n + 1), the
number of links.
(c) Tie-Set Matrix, B, and KVL
Kirchhoffs voltage law (KVL) of a graph can be applied to the f -loops to obtain a
set of linearly independent equations. For the tree with twigs {b,c,e}, there are three
fundamental loops, L1 , L2 and L3 with loop currents I1 , I2 and I3 respectively.
If Va , Vb , Vc , Vd , Ve and Vf are the branch voltages, then the KVL equations for the three
f -loops can be obtain from B V = 0.
For example: Considering the last tree with twigs{b,c,e}, we have
Va
Vb 0
1 1 1 0 0 0
Vc 0
0 1 0 1 1 0 Vd = 0
0 0 1 0 1 1
Ve
0
Vf
b 2 c 2 b 2 c 2 c
1 3 1 c 3 1 3 1 3
IL1
L2 IL3
d e f d e d e d e f
4 4 4 4
ia 1 0 0
ib 0 1 0
I L
ic
= 1 0 1 1
IL
2
id 1 1 0
IL3
ie 1 1 1
if 0 0 1
1 0 1 1 1 0
Where B = 0 1 0 1 1 0
0 0 1 0 1 1
Branch current equations in terms of loop currents from the above equation is
given by
ia = IL1 id = IL1 + IL2
ib = IL2 ie = IL1 + IL2 IL3
ic = IL1 + IL3 if = IL3
Q. Obtain reduced incidence matrices and at least two tie-set matrices by selecting
appropriate trees from each of the following graphs.
1 a 2
1
b g
c
4 3
5 i h
2 b c 5 d
a d
6 e f
3 4
References
[1] M. E. Van Valkenburg, Network Analysis, 3/e, PHI, 2005.
[2] W. H. Hayt, J. E. Kemmerly, S. M. Durbin, Engineering Circuit Analysis, 8/e, MH, 2012.
[3] M. Nahvi, J. A. Edminister, Schuams Outline Electric Circuits, 4/e, TMH, SIE, 2007.
[4] D. Roy Choudhury, Networks and Systems, New Age Publishers, 1998.
[5] A. Sudhakar, S. S. Palli, Circuits and Networks: Analysis and Synthesis, 2/e, TMH, 2002.