Department of Computer Science and Engineering

Course Name : DIGITAL LOGIC DESIGN FOR COMPUTERS

Course Number :

Course Designation: Core

Prerequisites :

II B Tech I Semester
(2015-2016)

P.ANJAIAH
Associate Professor
 SYLLABUS

Number Systems: Binary, Octal, Hex Decimal, and Conversions, range; Binary additions
and subtractions (using 1c, and 2c), concept of overflow; representations of negative
numbers using 1s and 2s complement and range; BCD numbers: Representation of
Unit I
8421, 2421, Ex-3, Gray and self complementary codes; additions and subtractions on 8421
codes; Error detecting codes: even, odd parity, hamming codes; Error correcting
codes: hamming codes, block parity codes; Floating point representation.

Boolean Algebra and Digital Logic GATES, Basic Boolean LAWs and properties;
Boolean functions; canonical and standard forms (SOP, POS); Gate minimization using
Unit II
three and four variable K-Maps with and without dont cares. Encoders, Decoders,
Multiplexers, D-Multiplexers;

Definition of combinational circuits, design procedure for half, full, decimal (8421) adders
Unit III and subtractions; Combinational Circuit Design for BCD code converters;

Sequential circuits, latches, Flip Flops; Analysis of clocked sequential circuits, State
Unit IV Reduction and Assignment, Register, Ripple Counters, Synchronous Counters, Other
Counters.

Types of Memory Main memory random access memory, ROM, Types of ROM;
Decoder and RAM interface: Address lines, data lines, chip select signal; Design of large
Unit V memories using small memories, using decoders; problems in memory design; Cache
Memory- design issues, hit and miss ratio related problems; Associative and Auxiliary
memory;
TEXT BOOKS & OTHER REFERENCES

Text Books
Digital Design Third Edition, M. Morris Mano, Pearson Education/PHI.
1.
Fundamentals of Logic Design, Roth, Fifth Edition, Thomson.
2.

Suggested / Reference Books

3. Switching and Logic Design C.V.S. Rao, Pearson education
4. Switching and Finite Automata Theory by Zvi. Kohavi, Tata McGraw Hill.
5.

Websites References
http://computerju.com/Materials/DSD/Digital-Design-4th-ed-M-Morris-
1.
Mano
2. http://www.prenhall.com/mano

3. http://www.writphotec.com/mano4

4. http://www.abandah.com/gheith

5. http://www-inst.eecs.berkeley.edu/~cs152/index.html

6.
 Time Table
Room No: W.E.F: 15/07/15
Class 1 2 3 4 5 6 7
Hour
9:00 - 09.50 10:40 11:30 1:10 2:00 2:50
Time 09:50 10:40 11:30 12: 20 2:00 2:50 3:40

MON

TUE

LUNCH BREAK
12:20 1:10
WED

THU

FRI

SAT
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

PEO1 The Graduates are employable as software professionals in reputed industries.

PEO2 The Graduates analyze problems by applying the principles of computer science,
mathematics and scientific investigation to design and implement industry
accepted solutions using latest technologies.

PEO3 The Graduates work productively in supportive and leadership roles on

multidisciplinary teams with effective communication and team work skills with
high regard to legal and ethical responsibilities.

PEO4 The Graduates embrace lifelong learning to meet ever changing developments in
computer science and Engineering.

PROGRAM OUTCOMES (POs)

PO1 An ability to communicate effectively and work on multidisciplinary teams

PO2 An ability to identify, formulate and solve computer system problems with
professional and ethical responsibility.

PO3 A recognition of the need for, and an ability to engage in life-long learning
to use the latest techniques, skills and modern engineering tools

PO4 The broad education necessary to understand the impact of engineering

solutions in a global, economic, environmental and social context

PO5 An ability to apply knowledge of mathematics, science, and computing to

analyze, design and implement solutions to the realistic problems.

PO6 An ability to apply suitable process with the understanding of software

development practice.
Course Outcomes:

A student who successfully fulfills the course requirements will

have demonstrated an ability to:

CO1. Design combinational and sequential circuits using Boolean

algebra.

CO2. Design combinational and sequential circuits using

Karnaugh Maps.

C03. Work with the various Complement Arithmetic Systems

used for hardware arithmetic.

CO4.Understand elementary Boolean codes.& Work with the

commonly encountered hardware library modules

CO5. Design with Complex Programmable Logic, ROM, RAM,

And Field-Programmable Gate Arrays.

MAPPING OF COURSE OUT COMES WITH POs & PEOs

Course Outcomes POs PEOs

CO1 PO5 PEO2
CO2 PO5 PEO2
CO3 PO2 PEO4
CO4 PO2 PEO3
CO5 PO6 PEO2
 COURSE SCHEDULE

Distribution of Hours Unit Wise

Chapters
Total No.
Unit Topic
of Hours
Book1 Book2

I Ch1 Ch1 12

II Ch2,3 Ch9 10

III Ch4,5 Ch8 8

IV Ch6 Ch11 10

V Ch7 Ch9 10

Contact classes for Syllabus coverage 50

Tutorial Classes : 05 ; Online Quiz : 1

Case studies-2 (Before Mid Examinations)
Revision classes :1 per unit

Number of Hours / lectures available in this Semester / Year 55

Lecture Plan

Units Topic Hours Date of Completion

Number Systems: Binary, Octal, Hex Decimal

2
Conversions,
1
Binary additions and subtractions (using 1c, and 2c),
Unit-1 1
concept of overflow
representations of negative numbers using 1s and 2s 1
complement and range;
2
Representation of 8421, 2421, Ex-3,
 1
Gray and self complementary codes
1
additions and subtractions on 8421 codes
Error detecting codes: even, odd parity, hamming 1
codes;
hamming codes, block parity codes; Floating point 1
representation.

1
revision
12
Total
1
Boolean Algebra and Digital Logic GATES
1
Basic Boolean LAWs and properties
1
Boolean functions
2
canonical and standard forms (SOP, POS);
Unit-2
Gate minimization using three and four variable K- 2
Maps with and without dont cares
1
Encoders, Decoders
1
Multiplexers, D-Multiplexers;
1
revision
10
Total
1
Definition of combinational circuits
2
design procedure for half, full adders
2
decimal (8421) adders and sub tractors;
Combinational Circuit Design for BCD code 2
Unit-3 converters;

1
revision
8
Total
1
Unit-4 Sequential circuits
 2
latches, Flip Flops
2
Analysis of clocked sequential circuits
1
State Reduction and Assignment
2
Register, Ripple Counters,
1
Synchronous Counters
1
revision
10
Total
1
Types of Memory Main memory
1
random access memory, ROM, Types of ROM
1
Unit-5 Decoder and RAM interface
1
Address lines, data lines, chip select signal
1
Design of large memories using small memories,
1
using decoders; problems in memory design
1
Cache Memory- design issues,
1
hit and miss ratio related problems
Associative and Auxiliary memory; 1

1
revision
10
Total
50
Total No of hours
Date of Unit Completion & Remarks

Unit 1

Date : __ / __ / __

Remarks:
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Unit 2

Date : __ / __ / __

Remarks:

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Unit 3

Date : __ / __ / __

Remarks:

________________________________________________________________________

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Unit 4

Date : __ / __ / __

Remarks:

________________________________________________________________________

________________________________________________________________________
Unit 5

Date : __ / __ / __

Remarks:

________________________________________________________________________

________________________________________________________________________
Unit Wise Assignments (With different Levels of thinking (Blooms Taxonomy))
Note: For every question please mention the level of Blooms taxonomy

Unit 1
Convert the following numbers
a) (1432)8 to base 10
b) 10101100111.0101 to base 10
c) 11010011001.1010 to base 8 and base 4
1. d) (2002)10 to base 8
e) (2002)10 to base 6
f) (75.125)10 to base 2
g) (3.375)10 to base 8 and base 2
h) (ABCD)16 to base 10

Perform the subtraction with the following unsigned binary numbers by taking
the 2s complement of the subtrahend. [52]
i. 11010 - 10110
2. ii. 11011 1001
iii. 100 - 110100
iv. 1010101 - 1010101
v. 11 - 1101.

Unit 2

i. Find the complement of the Boolean function (BC+AD) (AB+CD)

1.
and reduce it to a minimum number of literals
(ii) Convert the function f (x, y, z) = (0, 3, 6, 7) to the other canonical form.

Simplify the Boolean function F in sum of products using the dont care
2. conditions d: (Karnaugh map method) F = y+xz
d = yz+xy
Draw the AND-OR gate implementation of the following function after
simplifying of the following function
3. after simplifying it in.
i) SOP and posii) Forms
F(A,B,C,D) = (0,2,5,6,7,8,10)
Simplify the following expression and implement them with two level NAND
gate circuits.
4. i) AB ABD AB D A C D A B C
ii) BD BC D A BC D .

Unit 3
A combinational circuit has 4 inputs(A,B,C,D) and three outputs(X,Y,Z)XYZ
1. represents a binary number whose value equals the number of 1's at the input:
 Implement Half adder using 4 NAND gates
(b) Implement full subtract or using NAND gates only.
2.

. (a) Design a BCD to Excess-3 code converter using minimum number of

3. NAND gates
(b) Design a BCD to Gray code converter using 8:1 multiplexers.
4.

Unit 4

Give the implementation of a 4-bit ripple-carry adder using half- adder(s) /

1.
full-adder(s).

Give the transition table for RS flip flop.

2.
Convert JK flip flop into T and D flip flops.

Draw and explain with the help of truth table the logic diagram of a master slave
D flip-flop using NAND
3.
gates. With active low preset and clear and with negative edge triggered clock.

Draw the schematic circuit of T-Flip-op. Give its truth table. Justify the entries
4.
in the truth table?

Unit 5
What are the main differences between RAM and ROM? Design a circuit using
1. ROM which will perform the squaring operation for the given 3 bit binary
number.
(a) Explain the block diagram of a memory unit. Explain the read and write
operation a RAM can perform.
(b) i. How many 32K * 8 RAM chips are needed to provide a memory capacity
of
2. 256K bytes?
ii. How many lines of the address must be used to access 256K bytes? How
many of these lines are connected to the address inputs of all chips?
iii. How many lines must be decoded for the chip select inputs? Specify the size
of the decoder.
Case Studies (With Higher Levels of thinking (Blooms Taxonomy))
Note: For every Case Study please mention the level of Blooms taxonomy

1(Covering Syllabus Up to Mid-1)

Design A Case Study On Combinational circuit by Using Various Gates And Circuits

2(Covering Entire Syllabus)

Design A Case Study On Sequential Circuits Using Registers And Counters

Unit Wise Multiple Choice Questions

Number Systems And Codes

Unit-1

1. The number of digits in octal systems are

(a) 8 (c) 8 or 7
(b) 7 (d) 10
Ans. (a)

2. The digit F in hexadecimal system has equivalence in digital system to

(a) 16 (c) 17
(b) 15 (d) 18
Ans. (b)
 3. The number FF in hexadecimal system has equivalence in decimal system to
(a) 256 (c) 240
(b) 255 (d) 239
Ans. (b)

4. Two voltages are 0V and -5V. In positive logic

(a) 0V is 1 and -5V is 0
(b) -5V is 1 and 0V is 0
(c) 0V is 1 in some circuit and 0 in others
(d) -5V is 1 in some circuit and 0 in others

Ans. (a)

In positive logic, higher voltage is represented as logic 1 and lower as logic 0

5. In the decimal number 27, the digit 2 represents

(a) 2 (c) 0.2
(b) 20 (d) 200
Ans. (b)
6. Hexadecimal number F is equal to octal number
(a) 15 (c) 17
(b) 16 (d) 18
Ans. (c)

8. -8 is equal to signed binary number (8 bit)

(a) 10001000 (c) 1000000
(b) 00001000 (d) 11000000
Ans. (a)

For signed binary number MSB is 1 for negative number.

9. 1 s complement of 11100110 is
 (a) 00011001 (c) 00011010
(b) 10000001 (d) 00000000
Ans. (a)

10. 2s complement of binary number 0101 is

(a) 1011 (c) 1101
(b) 1111 (d) 1110
Ans. (a)

Just complement the bits and add 1

11.-24 is 2s complement form is

(a) 11101000 (c) 01111111
(b) 01001000 (d) 00111111
Ans. (a)

(+24)10 = (00011000)2 2s complement is 1110100 = (-24)10

Alternative and simple method to find 2s complement.

Write the ( ) ( )
MSB LSB

00011000

Stating from LSB copy all digits till first 1, then complement the further bits
(-24)10 = 11101000 in 2s complement form

12.7BF16 = (----)2
(a) 0111 1011 1110 (c) 0111 1011 0111
(b) 0111 1011 1111 (d) 0111 1011 0011
Ans. (b)

Convert each hexadecimal digit to binary

13.(E7F6)16 = (-----)10
(a) (600000)10 (c) (9382)10
 (b) (59382)10 (d) (382)10
Ans. (b)

14. 26810 = (----)16

(a) 10 A16 (c) 10 C16
(b) 10 B16 (d) 10 D16
Ans. (c)
By observation one could see that

Alternative method:

Convert decimal to Hex

Division Remainder

16)268 -

16)16 12C LSD

16)1 0

16)0 1 MSD

Remainder
Read the remainders from bottom to top (10C) 16

15. Convert (47)16 = ( )8

The hexadecimal number can be converted to decimal and decimal to octal, but the
best way is

Convert the number to its binary equivalent

Form group of 3 bits starting from LSB

Write the equivalent octal number
(47)16 = (0100 0111)

Here each hex digit is written in a group of 4 binary bits

16.The number of bits in ASCII is

(a) 12 (c) 9
(b) 10 (d) 7
Ans. (d)
 17.The number of bits in EBCDIC is
(a) 12 (c) 8
(b) 10 (d) 6
Ans. (C)

18.FF16 when converted to 8421 BCD is

(a) 0000 0101 0101 (c) 1111 0101 0101
(b) 0010 0101 0101 (d) 1000 0101 0101
Ans. (b)
( )

Now represent each digit in BCD

19.Decimal number 9 in Gray code is

(a) 1100 (c) 110
(b) 1101 (d) 1111
Ans. (b)
(9)10 = (1001)2

20.11011 in gray code equal to binary

(a) (10010)2 (c) (11100)2
(b) (11111)2 (d) (10001)2
Ans. (a)
 Unit II

1) Boolean algebra is also called

A. switching algebra
B. arithmetic algebra
C. linear algebra
D. algebra

2) To perform product of maxterms Boolean function must be brought into

A. and terms
B. or terms
C. not terms
D. nand terms

Answer B

4). Boolean algebra theorem 6b gives x(x+y) equal to

A. x'
B. 1
C. x
D. 0

5). A Boolean function may be transformed into

A. logical diagram
B. logical graph
C. map
D. matrix

6.) e*x=x*e=x is the

A. commutative property
B. inverse property
C. associative property
D. identity element
 7).Minterms are also called

A. standard sum
B. standard product
C. standard division
D. standard subtraction

8). Maxterms are also called

A. standard sum
B. standard product
C. standard division
D. standard subtraction

9). x+xy=x is known as

A. inverse law
B. commutative law
C. distributive law
D. absorption law

10). A two valued Boolean algebra is defined as a set of

A. three values
B. two values
C. four values
D. five value

11). Most preceded operator is

A. parenthesis
B. AND
C. OR D. NOT

12). (a+b+c)'=

A. a'b'c'
B. a'+b'+c'
C. abc
D. a+b+c

Answer A
 13). x+x'y=

A. x
B. y
C. x-y
D. x+y

14). Another way of expressing Boolean algebra is

A. graphical form
B. plot form
C. non standard form
D. standard form

15). The primed or unprimed variable is

A. map
B. logic gates
C. literal
D. graph

16). A binary variable can take the values

A. 0 only
B. 0 and -1
C. 0 and 1
D. 1 and 2

Answer C

16.1). According to the Boolean algebra theorems x.x is equal to

A. x
B. 1
C. 0
D. x'

17). One that is not the postulate of Boolean algebra

A. commutative
B. duality
C. associative
D. identity element
 18). Symbol representing AND operation

A. (+)
B. (.)
C. (-)
D. (/)

19). Boolean algebra is an algebraic structure with two arithmetic operations

A. addition and subtraction

B. subtraction and multiplication
C. addition and multiplication
D. addition and division

20). 2^3 would have

A. three values
B. four values
C. six values
D. eight values

Answer D

21). Is it possible to find two algebric expressions that specify the same function

A. no
B. yes
C. maybe
D. never

22). Postulate 2 of Boolean algebra defines

A. x+0=x
B. x+0=1
C. x+0=0
D. x+1=0

23). x+xy=

A. y
B. 1
C. 0 D. x
 24). x+y=y+x is the

A. commutative property
B. inverse property
C. associative property
D. identity element

25). Boolean algebra is the collection of objects having

A. positive properties
B. negative properties
C. common properties
D. different properties

25.a).An identity element w.r.t addition

A. x-1
B. x+1
C. x-0
D. x+0

Answer D

25.b). A simple method of deriving the complement is two to take dual and

A. divide
B. subtract
C. add
D. complement

Answer D

26). The complement of a function expressed as

A. sum of minterms
B. product of minterms
C. sum of maxterms
D. product of maxterms

27). (x*y)*z=x*(y*z) is the

A. commutative property
B. inverse property
C. identity element. D. associative propertyAnswer D
 28). Huntington postulates does not includes

A. inverse law
B. commutative law
C. associative law
D. distributive law

28.a). An identity element w.r.t addition

A. x-1
B. x+1
C. x-0
D. x+0

29). A simple method of deriving the complement is two to take dual and

A. divide
B. subtract
C. add
D. complementAnswer D

30). The complement of a function expressed as

A. sum of minterms
B. product of minterms
C. sum of maxterms
D. product of maxterms

31). (x*y)*z=x*(y*z) is the

A. commutative property
B. inverse property
C. identity element
D. associative property

32). Huntington postulates does not includes

A. inverse law
B. commutative law
C. associative law
D. distributive law

Answer C
 32.a).the exclusive-OR is an

A. prime function
B. undefined function
C. even function
D. odd function

33).Truth table is the way of expressing

A. Boolean function
B. Boolean operators
C. Boolean addition
D. Boolean subtraction

34). NAND is a complement of

A. AND
B. OR
C. NOT
D. XOR

35). Boolean algebra theorem 4 gives (x')' is equal to

A. x'
B. x
C. 1
D. 0

36). Any Boolean function can be represented in a

A. plane
B. graph
C. flow chart
D. truth table

Commutative property w.r.t addition is

A. x+y=y+x
B. x-y=y-x
C. x*y=y*x
D. (x+y)z=(z+y)x

37). NOR is a complement of

A. AND
B. OR
C. NOT
D. XOR

38). The inverter circuit inverts the logic sense of

A. division
B. addition
C. Boolean variable
D. Subtraction

39). x+x' is equal to

A. 1
B. 0
C. x
D. x'

40). One that shows distributive law of addition over multiplication

A. x+(y.z)=(x.y)+(x.z)
B. x+(y.z)=(x+y).(x+z)
C. x+(y.z)=(x.y).(x+z)
D. x.(y+z)=(x+y).(x+z)

41). In the equation a*b=c, * is the

A. binary operator
B. logical operator
C. geometric operators
D. linear operators

42). The complement of the function F is

A. 1
B. F'
C. F
D. 0

43). Binary operator + defines

A. multiplication
B. division
C. addition
D. subtraction
 44). Demorgan law over addition is

A. (x.y)'=x'y'
B. (x+y)'=x+'y'
C. (x+y)'=x'y'
D. (x+y)'=x'

45). (x')' is

A. complement
B. dual complement
C. duality
D. reflection

wer
Key point

The first two problems at S. Nos. 1 and 2 are on the Number of Boolean expressions
for a given number of variables.

The number of Boolean expressions for n variables is

Note that for n variable Boolean function one can have 2n Boolean inputs.

46. The number of Boolean function that can be generated by n variables is equal to:
(a) (c)
(d)
(b)
[GATE 1990 : 1 Mark]
Ans. (b)

The number of district Boolean expressions for n variables is

Where, n is the number of variables.

47. The number of distinct Boolean expressions of 4 variables is

(a) 16 (c) 1024
(b) 256 (d) 65536
[GATE 2003 : 1 Mark]
Ans. (d)

Two 2s complement number having sign bits x and y are added and the
sign bit of the result is z. Then, the occurrence of overflow is indicated
by the Boolean function.
 Ans. (c)

This problem is based on 2s complement addition/subtraction (covered

in number systems). Here we have to write the Boolean expression for
the case where overflow occurs.

In the 2s complement arithmetic we had seen that if MSB (Sign bit) of

operands (Minuend & Subtrahend) is same, and the MSB of the result is
different or vice versa an overflow occurs.
i.e.
or, if
Overflow occurs
So, we can write
is the Boolean function for the overflow to occur.
Key points:

The problems in Q Nos. 3, 4, 5, 6, 7 and 8 are on the simplification of Boolean

expressions based on algebraic methods like using laws and theorems of Boolean
algebra. But this method becomes complex with increase in number of variables
and number of terms.

49. The logical

is equivalent to
expression
(a) (c)
(b) (d)
[GATE 1999 : 1
Mark]

Ans. (d)
Key Points:

Prime implicants :A product term in SOP which cannot be further simplified

by combination with other terms.

SOP (Sum of product) and POS (producer Sum) expressions.

K-Map has 2k cells where k is no. of variables.

Dont care combinations: Represented asd. ds can be combined with 1s to
simplify, where needed.

54).The K-map for a Boolean function is shown in figure. The number of essential prime
implicants for this function is
AB
CD 00 01 11 10
00 1 1 0 1

01 0 0 0 1

11 1 0 0 0

10 1 0 0 1

(a) 4 (c) 6
(b) 5 (d) 8
[GATE 1998 : 1 Mark]
Ans. (a)

AB
CD 00 01 11 10
00 1 1 1

01 1

11 1

10 1 1

On the K-Map retaining only minimum terms (corresponding to 1)

 The number of prime implacants are

Four prime implicants
55). The number of products terms in the minimized sum-of-product expression obtained
through the following K-map is (where, d denotes dont care states)
1 0 0 1

0 d 0 0

0 0 d 1

1 0 0 1

(a) 2 (c) 4
(b) 3 (d) 5
[GATE 2006 : 2 Marks]

Ans. (a)

A
B
CD 00 01 11 10
00 1 0 0 1

01 0 d 0 0

11 0 0 d 1

10 1 0 0 1

To write the minimized expression (d terms do not simplify the expression)

So there are only two product terms

can be minimized to
56. The Boolean expression
(a) (c)
(b) (d)
[GATE 2007 : 2 Marks]
 Unit-3

1.Which of the circuits in figure (a to d) is the sum-of-products implementation

of figure (e)?

2.

A. a

C. c

3.For the device shown here, let all D inputs be LOW, both S inputs be HIGH,
and the input be LOW. What is the status of the Y output?
 A. LOW

B. HIGH

C. Don't Care

D. Cannot be determined

4.For the device shown here, let all D inputs be LOW, both S inputs be HIGH,
and the input be HIGH. What is the status of the Y output?

A. LOW

B. HIGH

C. Don't Care

D. Cannot be determined

5.Convert BCD 0001 0010 0110 to binary.

A. 1111110

C. 1111000

9.A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW

outputs. What would be the state of the four outputs if inputs 4 and 5
are LOW and all other inputs are HIGH?

A.

B.

C.

D.
6.Convert BCD 0001 0111 to binary.

A. 10101

C. 10001

7.Which of the figures in figure (a to d) is equivalent to figure (e)?

A. a

C. C
8.How many data select lines are required for selecting eight inputs?

A. 1

C. 3

9. The simplest equation which implements the K-map shown below is:

A.

B.

C.

D.

10.How many 1-of-16 decoders are required for decoding a 7-bit binary number?

A. 5

C. 7

11. Which of the following logic expressions represents the logic diagram shown?

A.

B.

C.
 D.

12.The implementation of simplified sum-of-products expressions may be

easily implemented into actual logic circuits using all universal ________ gates
with little or no increase in circuit complexity. (Select the response for the blank
space that will BEST make the statement true.)

A. AND/OR

C. NOR

13.Which of the following statements accurately represents the two

BEST methods of logic circuit simplification?

A. Boolean algebra and Karnaugh mapping

B. Karnaugh mapping and circuit waveform analysis

C. Actual circuit trial and error evaluation and waveform analysis

D. Boolean algebra and actual c

14.For the device shown here, assume the D input is LOW, both S inputs are
HIGH, and the input is HIGH. What is the status of the outputs?

A. All are HIGH.

B. All are LOW.

C. All but are LOW.

D. All but are HIGH.

15.Which of the following combinations cannot be combined into K-map groups?

A. Corners in the same row

B. Corners in the same column

 C. Diagonal corners

D. Overlapping combinations

16.As a technician you are confronted with a TTL circuit board containing
dozens of IC chips. You have taken several readings at numerous IC chips,
but the readings are inconclusive because of their erratic nature.
Of the possible faults listed, select the one that most probably is causing the problem.

A. A defective IC chip that is drawing excessive current from the power supply

B. A solar bridge between the inputs on the first IC chip on the board

C. An open input on the first IC chip on the board

D. A defective output IC chip that has an internal open to Vcc

17.Which gate is best used as a basic comparator?

A. NOR

C. Exclusive-OR

18.The device shown here is most likely a ________.

A. comparator

B. multiplexer

C. demultiplexer

D. parity generator

19. In VHDL, macrofunctions is/are:

A. digital circuits.
 B. analog circuits.

C. a set of bit vectors.

D. preprogrammed TTL devices.

20. Which of the following expressions is in the product-of-sums form?

A. (A + B)(C + D)

B. (AB)(CD)

C. AB(CD)

D. AB + CD

21. Which of the following is an important feature of the sum-of-products

form of expressions?

All logic circuits are reduced to nothing more than simple

A.
AND and OR operations.

B. The delay times are greatly reduced over other forms.

No signal must pass through more than two gates, not

C.
including inverters.

The maximum number of gates that any signal must pass

D.
through is reduced by a factor of two.

22. For the device shown here, assume the D input is LOW, both S inputs

are LOW, and the input is LOW. What is the status of the outputs?
 A. All are HIGH.

B. All are LOW.

C. All but are LOW.

D. All but are HIGH.

23. An output gate is connected to four input gates; the circuit does not function.

Preliminary tests with the DMM indicate that the power is applied;

scope tests show that the primary input gate has a pulsing signal,

while the interconnecting node has no signal. The four load gates

are all on different ICs. Which instrument will best help isolate the problem?

A. Current tracer

B. Logic probe

C. Oscilloscope

D. Logic analyzer

24.The binary numbers A = 1100 and B = 1001 are applied to the inputs

of a comparator. What are the output levels?

A. A > B = 1, A < B = 0, A < B = 1

B. A > B = 0, A < B = 1, A = B = 0

C. A > B = 1, A < B = 0, A = B = 0
 D. A > B = 0, A < B = 1, A = B = 1

25. A logic probe is placed on the output of a gate and the display indicator is dim.
A pulser is used on each of the input terminals, but the output indication
does not change. What is wrong?

A. The output of the gate appears to be open.

B. The dim indication on the logic probe indicates that the supply
voltage is probably low.

C. The dim indication is a result of a bad ground connection on the logic probe.

D. The gate may be a tristate device.

26.Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder.

The carry input is 1. What are the values for the sum and carry output?

A. 4 3 2 1 = 0111, Cout = 0

B. 4 3 2 1 = 1111, Cout = 1

C. 4 3 2 1 = 1011, Cout = 1

D. 4 3 2 1 = 1100, Cout = 1

27. Each "1" entry in a K-map square represents:

A. a HIGH for each input truth table condition that produces a HIGH output.

B. a HIGH output on the truth table for all LOW input combinations.

C. a LOW output for all possible HIGH input conditions.

D. a DON'T CARE condition for all possible input truth table combinations.

Looping on a K-map always results in the elimination of:

28. Based on the indications of probe A in the figure given below, what is wrong,

if anything, with the circuit?

 31.The logic probe is unable to determine the state of the circuit at
A.
that point and is blinking to alert the technician to the problem.

The output appears to be shorted to Vcc, but is being pulsed by the

B.
pulser.

C. The output appears to be LOW, but is being pulsed by the pulser.

D. Nothing appears to be wrong at that point.

29. In HDL, LITERALS is/are:

A. digital systems.

B. scalars.

C. binary coded decimals.

D. a numbering system.

30. Which of the following expressions is in the sum-of-products form?

A. (A + B)(C + D)

B. (AB)(CD)

C. AB(CD)
 D. AB + CD

31.The carry propagation can be expressed as ________.

A. Cp = AB

B. Cp = A + B

C.

D.

32.Which of the K-maps given below represents the expression X = AC + BC + B?

A. a

C. c

33.A decoder can be used as a demultiplexer by ________.

A. tying all enable pins LOW

B. tying all data-select lines LOW

C. tying all data-select lines HIGH

D. using the input lines for data selection and an enable line for data input
 34.How many 4-bit parallel adders would be required to add two binary
numbers each representing decimal numbers up through 30010?

A. 1

C. 3

35.Which statement below best describes a Karnaugh map?

A. A Karnaugh map can be used to replace Boolean rules.

B. The Karnaugh map eliminates the need for using NAND and NOR gates.

C. Variable complements can be eliminated by using Karnaugh maps.

D. Karnaugh maps provide a visual approach to simplifying Boolean expressions.

36.For a two-input XNOR gate, with the input waveforms as shown below,
which output waveform is correct?

A. a

C. c

37. Solve the network in the figure given below for X.

A. A + BC + D

B. ((A + B)C) + D
 C. D(A + B + C)

D. (AC + BC)D

38. A full-adder has a Cin = 0. What are the sum ( ) and the carry (Cout) when A = 1 and B = 1?

A. = 0, Cout = 0

B. = 0, Cout = 1

C. = 1, Cout = 0

D. = 1, Cout = 1

39. What type of logic circuit is represented by the figure shown below?

A. XOR B. XNOR

C. XAND D. XNAND

40. The device shown here is most likely a ________.

A. comparator

B. multiplexer
 C. demultiplexer

D. parity generator

41. The design concept of using building blocks of circuits in a PLD program is called a(n):

A. hierarchical design.

B. architectural design.

C. digital design.

D. verilog.

42. When adding an even parity bit to the code 110010, the result is ________.

A. 1110010 B. 1111001

C. 110010 D. 001101

43. Which of the following combinations of logic gates can decode binary 1101?

A. One 4-input AND gate

B. One 4-input AND gate, one OR gate

C. One 4-input NAND gate, one inverter

D. One 4-input AND gate, one inverter

44. What is the indication of a short to ground in the output of a driving gate?

A. Only the output of the defective gate is affected.

B. There is a signal loss to all load gates.

C. The node may be stuck in either the HIGH or the LOW state.

D. The affected node will be stuck in the HIGH state.

45. How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line
encoder, have?

A. 3 B. 4

C. 5 D. 6

UNIT-4
1).A ripple counter's speed is limited by the propagation delay of:

A. each flip-flop

B. all flip-flops and gates

C. the flip-flops only with gates

D. only circuit gates

2. To operate correctly, starting a ring counter requires:

A. clearing all the flip-flops

B. presetting one flip-flop and clearing all the others

C. clearing one flip-flop and presetting all the others

D. presetting all the flip-flops

3. What type of register would shift a complete binary number in one bit at a time and shift all the
stored bits out one bit at a time?

A. PIPO B. SISO

C. SIPO D. PISO

4. Synchronous counters eliminate the delay problems encountered with asynchronous (ripple)
counters because the:

A. input clock pulses are applied only to the first and last stages

B. input clock pulses are applied only to the last stage

 C. input clock pulses are not used to activate any of the counter stages

D. input clock pulses are applied simultaneously to each stage

5. One of the major drawbacks to the use of asynchronous counters is that:

A. low-frequency applications are limited because of internal propagation delays

B. high-frequency applications are limited because of internal propagation delays

Asynchronous counters do not have major drawbacks and are suitable for use in
C.
high- and low-frequency counting applications.

Asynchronous counters do not have propagation delays, which limits their use in
D.
high-frequency applications.

6. Which type of device may be used to interface a parallel data format with external equipment's
serial format?

A. key matrix

B. UART

C. memory chip

D. serial-in, parallel-out

7. When the output of a tri-state shift register is disabled, the output level is placed in a:

A. float state

B. LOW state

C. high impedance state

D. float state and a high impedance state

8. A comparison between ring and johnson counters indicates that:

A. a ring counter has fewer flip-flops but requires more decoding circuitry
 B. a ring counter has an inverted feedback path

C. a johnson counter has more flip-flops but less decoding circuitry

D. a johnson counter has an inverted feedback path

9. A sequence of equally spaced timing pulses may be easily generated by which type of counter
circuit?

A. shift register sequencer

B. clock

C. johnson

D. binary

10. What is meant by parallel-loading the register?

A. Shifting the data in all flip-flops simultaneously

B. Loading data in two of the flip-flops

C. Loading data in all four flip-flops at the same time

D. Momentarily disabling the synchronous SET and RESET inputs

11. What is a shift register that will accept a parallel input and can shift data left or right called?

A. tri-state

B. end around

C. bidirectional universal

D. conversion

12. What happens to the parallel output word in an asynchronous binary down counter whenever a
clock pulse occurs?

A. The output word decreases by 1.

 B. The output word decreases by 2.

C. The output word increases by 1.

D. The output word increases by 2.

13. Mod-6 and mod-12 counters are most commonly used in:

A. frequency counters

B. multiplexed displays

C. digital clocks

D. power consumption meters

UNIT-5
1. How many address bits are needed to select all memory locations in the 2118 16K 1 RAM?

A. 8 B. 10

C. 14 D. 16

2. The check sum method of testing a ROM:

A. indicates if the data in more than one memory location is incorrect.

provides a means for locating and correcting data errors in specific memory
B.
locations.

C. allows data errors to be pinpointed to a specific memory location.

D. simply indicates that the contents of the ROM are incorrect.

3. Refer to the given figures (a) and (b). A logic analyzer is used to check the circuit in figure (a)
and displays the waveforms shown in figure (b). The actual analyzer display shows all four data
outputs, Q0-Q3. The analyzer's cursor is placed at position X and all four of the data output
lines show a LOW level output. What is wrong, if anything, with the circuit?
 Nothing is wrong, according to the display. The outputs are in the open state and
A.
should show zero output voltage.

The circuit is in the READ mode and the outputs, Q0-Q3, should reflect the
B.
contents of the memory at that address. The chip is defective; replace the chip.

The circuit is in the mode and should be writing the contents of the selected
C.
address to Q0Q3.

The Q0Q3 lines can be either LOW or HIGH, since the chip is in the tristate mode
D.
in which case their level is unpredictable.

4. What is the meaning of RAM, and what is its primary role?

Readily Available Memory; it is the first level of memory used by the computer in
A.
all of its operations.
 Random Access Memory; it is memory that can be reached by any sub- system
B.
within a computer, and at any time.

Random Access Memory; it is the memory used for short-term temporary data
C.
storage within the computer.

Resettable Automatic Memory; it is memory that can be used and then

D.
automatically reset, or cleared, after being read from or written to.

5. The storage element for a static RAM is the ________.

A. diode B. resistor

C. capacitor D. flip-flop

6. In a DRAM, what is the state of R/W during a read operation?

A. Low

B. High

C. Hi-Z

D. None of the above

7. The condition occurring when two or more devices try to write data to a bus simultaneously is
called ________.

A. address decoding

B. bus contention

C. bus collisions

D. address multiplexing

8. Which is/are the basic refresh mode(s) for dynamic RAM?

A. Burst refresh

B. Distributed refresh
 C. Open refresh

D. Burst refresh and distributed refresh

9. For the given circuit, what memory location is being addressed?

A. 10111 B. 249

C. 5 D. 157

10. One of the most important specifications on magnetic media is the ________.

A. rotation speed

B. tracks per inch

C. data transfer rate

D. polarity reversal rate

11. A 64-bit word consists of ________.

A. 4 bytes

B. 8 bytes

C. 10 bytes
 D. 12 bytes

12. Which of the following RAM timing parameters determine its operating speed?

A. tACC

B. tAA and tACS

C. tCO and tOD

D. tRC and tWC

13. The reason the data outputs of most ROM ICs are tristate outputs is to:

A. allow for three separate data input lines.

B. allow the bidirectional flow of data between the bus lines and the ROM registers.

C. permit the connection of many ROM chips to a common data bus.

D. isolate the registers from the data bus during read operations.

14. Select the statement that best describes Read-Only Memory (ROM).

A. nonvolatile, used to store information that changes during system operation

B. nonvolatile, used to store information that does not change during system operation

C. volatile, used to store information that changes during system operation

D. volatile, used to store information that does not change during system operation

15. How many 2K 8 ROM chips would be required to build a 16K 8 memory system?

A. 2 B. 4

C. 8 D. 16

16. For the given circuit, which of the following is correct?

 A. The number 5 is being written to the memory at address location 203.

The chip has not been enabled, since the EN terminal is 0; therefore, nothing will be
B.
written to the chip and the output is tri-stated.

C. Decimal 10 is being written into memory location 211.

The read/write line is LOW; therefore, decimal 5 is being stored at memory location
D.
211.

17. What is the significance of the inverted triangles on the outputs of the device in the given
figure?

A. They represent inverters and mean that the outputs are active-LOW.
 They represent buffers and mean that the outputs can drive 40 TTL loads, instead of
B.
the normal 10.

It means that the outputs will be active only if a change has occurred at that memory
C.
location since the last read/write cycle.

D. The outputs are tristated.

18. What is the maximum time required before a dynamic RAM must be refreshed?

A. 2 ms

B. 4 ms

C. 8 ms

D. 10 ms

19. Which of the following best describes random-access memory (RAM)?

A. a type of memory in which access time depends on memory location

a type of memory that can be written to only once but can be read from an infinite
B.
number of times

C. a type of memory in which access time is the same for each memory location

D. mass memory

20. Why are ROMs called nonvolatile memory?

A. They lose memory when power is removed.

B. They do not lose memory when power is removed.

21. A CD-R disk is created by applying heat to special chemicals on the disk and these chemicals
reflect less light than the areas that are not burned, thus creating the same effect as a pit does on
a regular CD.

A. True B. False

22. The device shown in the given figure is checked with a logic probe and the output is HIGH.
 A. The device is working properly.

For the input conditions shown the output should be LOW; the input is shorted to
B.
ground.

For the input conditions shown the output should be neither HIGH nor LOW; the
C.
device is shorted to .

The device is probably alright; the problem is most likely caused by the stage
D.
connected to the output of the device.

23. Which of the following best describes static memory devices?

A. memory devices that are magnetic in nature and do not require constant refreshing

B. memory devices that are magnetic in nature and require constant refreshing

semiconductor memory devices in which stored data will not be retained with the
C.
power applied unless constantly refreshed

semiconductor memory devices in which stored data is retained as long as power is

D.
applied

24. Which is not a removable drive?

A. Zip B. Jaz

C. Hard D. SuperDisk

25. Which of the following best describes EPROMs?

A. EPROMs can be programmed only once.

 B. EPROMs can be erased by UV.

C. EPROMs can be erased by shorting all inputs to the ground.

D. All of the above.

26. How many storage locations are available when a memory device has 12 address lines?

A. 144 B. 512

C. 2048 D. 4096

27. FIFO is formed by an arrangement of ________.

A. diodes

B. transistors

C. MOS cells

D. shift registers

28. Why do most dynamic RAMs use a multiplexed address bus?

A. It is the only way to do it.

B. to make it faster

C. to keep the number of pins on the chip to a minimum

29. CCD stands for ________.

A. capacitor charging device

B. capacitor-capacitor drain

C. charged-capacitor device

D. charge-coupled device

30. What is the major difference between SRAM and DRAM?

 A. DRAMs must be periodically refreshed.

B. SRAMs can hold data via a static charge, even with power off.

The only difference is the terminal from which the data is removedfrom the FET
C.
Drain or Source.

Dynamic RAMs are always active; static RAMs must reset between data read/write
D.
cycles.

31. Which of the following best describes volatile memory?

A. memory that retains stored information when electrical power is removed

B. memory that loses stored information when electrical power is removed

C. magnetic memory

D. nonmagnetic

32. What is a major disadvantage of RAM?

A. Its access speed is too slow.

B. Its matrix size is too big.

C. It is volatile.

D. High power consumption

33. What two functions does a DRAM controller perform?

A. address multiplexing and data selection

B. address multiplexing and the refresh operation

C. data selection and the refresh operation

D. data selection and CPU accessing

34. The RAM circuit given below is suspected of being bad. A check with a logic probe shows
pulse activity on all of the address lines and data inputs. The / line and inputs are forced HIGH
and the data output lines are checked with the logic probe. Q0, Q2, and Q3 show a dim
indication on the logic probe; Q1 indicates a HIGH level on the logic probe. What, if anything,
is wrong with the circuit?

A. The Q0, Q2, and Q3 output lines are open; the chip is defective.

B. The Q1 line appears to be shorted to Vcc; replace the chip.

The outputs should be active only when the / line is held LOW, so the circuit is
C.
behaving normally considering the fact that the line is HIGH.

The EN input should be forced HIGH and the outputs rechecked; if they are still
D. giving the same indications as before, then the three outputs are definitely open and
the IC will have to be replaced.

35. Dynamic memory cells store a data bit in a ________.

A. diode B. resistor

C. capacitor D. flip-flop

36. Which is not part of a hard disk drive?

A. Spindle

B. Platter
 C. Read/write head

D. Valve

37. ROMs retain data when the ________.

A. power is off

B. power is on

C. system is down

D. all of the above

38. Typically, how often is DRAM refreshed?

A. 2 to 8 ms

B. 4 to 16 ms

C. 8 to 16 s

D. 1 to 2 s

39. Which type of ROM can be erased by an electrical signal?

A. ROM

B. mask ROM

C. EPROM

D. EEPROM

40. Suppose that a certain semiconductor memory chip has a capacity of 8K 8. How many bytes
could be stored in this device?

A. 8,000 B. 64,000

C. 65,536 D. 8,192
41. Data is written to and read from the disk via a magnetic ________ head mechanism in the
floppy drive.

A. cylinder B. read/write

C. recordable D. cluster

42. What does the term "random access" mean in terms of memory?

A. Addresses must be accessed in a specific order.

B. Any address can be accessed in any order.

43. A 64-Mbyte SIMM is installed into a system, but when a memory test is executed, the SIMM is
detected as a 32-Mbyte device. What is a possible cause?

A. The memory module was not installed properly.

B. The voltage on the memory module is incorrect.

C. The most significant address line is stuck high or low.

D. The address decoder on the SIMM is faulty.

44. Refer the given figure. The outputs (Q0Q3) of the memory are always LOW. The address lines
(A0A7) are checked with a logic probe and all are indicating pulse activity, except forA3,
which shows a constant HIGH, and A7, which shows a constant LOW; the select
lines, are checked and shows pulse activity, while indicates a constant HIGH.
What is wrong, and how can the memory be tested to determine whether it is defective or if the
external circuitry is defective?
 One of the inputs to the active-LOW select AND gate may be stuck high for some
reason; take both select lines LOW and check for pulse activity on the outputs,Q0
A.
Q3. If the outputs now respond, the problem is most likely in the program or
circuitry driving the select lines.

The problem appears to be in the two address lines that never change levels; the
B.
problem is probably in the program driving the memory address bus.

The output buffers are probably defective since they are all tied together; the
C.
common input line is most likely stuck LOW. Change the output buffer IC.

Since no data appears to be getting through to the output buffers, the problem may
D.
be in the X decoder; change the X decoder IC.

45. How many address lines would be required for a 2K 4 memory chip?

A. 8 B. 10

C. 11 D. 12

46. When a RAM module passes the checkerboard test it is:

A. able to read and write only 1s.

B. faulty.

C. probably good.
 D. able to read and write only 0s.

47. Which type of ROM has to be custom built by the factory?

A. ROM

B. mask ROM

C. EPROM

D. EEPROM

48. What is the computer main memory?

A. Hard drive and RAM

B. CD-ROM and hard drive

C. RAM and ROM

D. CMOS and hard drive

49. A major disadvantage of the mask ROM is that it:

A. is time consuming to change the stored data when system requirements change

B. is very expensive to change the stored data when system requirements change

C. cannot be reprogrammed if stored data needs to be changed

D. has an extremely short life expectancy and requires frequent replacement

50. The periodic recharging of DRAM memory cells is called ________.

A. multiplexing B. bootstrapping

C. refreshing D. flashing

51. Which of the following is normally used to initialize a computer system's hardware?

A. Bootstrap memory
 B. Volatile memory

C. External mass memory

D. Static memory

52. What is the difference between static RAM and dynamic RAM?

A. Static RAM must be refreshed, dynamic RAM does not.

B. There is no difference.

C. Dynamic RAM must be refreshed, static RAM does not.

53. Microprocessors and memory ICs are generally designed to drive only a single TTL load.
Therefore, if several inputs are being driven from the same bus, any memory IC must be
________.

A. buffered B. decoded

C. addressed D. stored

54. What are the typical values of tOE?

55. Which type of ROM can be erased by UV light?

A. ROM

B. mask ROM

C. EPROM

D. EEPROM

56. Which of the following is NOT a type of memory?

A. RAM B. ROM

C. FPROM D. EEPROM

57. How many address bits are required for a 4096-bit memory organized as a 512 8 memory?
 A. 2 B. 4

C. 8 D. 9

58. In general, the ________ have the smallest bit size and the ________ have the largest.

A. EEPROMs, Flash

B. SRAM, mask ROM

C. mask ROM, SRAM

D. DRAM, PROM

59. Advantage(s) of an EEPROM over an EPROM is/are:

A. the EPROM can be erased with ultraviolet light in much less time than an EEPROM

B. the EEPROM can be erased and reprogrammed without removal from the circuit

C. the EEPROM has the ability to erase and reprogram individual words

the EEPROM can be erased and reprogrammed without removal from the circuit,
D.
and can erase and reprogram individual words

60. The mask ROM is ________.

A. permanently programmed during the manufacturing process

B. volatile

C. easy to reprogram

D. extremely expensive

61. How many 1K 4 RAM chips would be required to build a 1K 8 memory system?

A. 2 B. 4

C. 8 D. 16
62. Which of the following memories uses a MOS capacitor as its memory cell?

A. SRAM B. DRAM

C. ROM D. FIFO

63. Which of the following faults will the checkerboard pattern test for in RAM?

A. Short between adjacent cells

B. Ability to store both 0s and 1s

C. Dynamically introduced errors between cells

D. All of the above

64. On a CD-ROM, ________ are raised areas representing a 1.

A. mounds B. lands

C. holes D. pits

65. The location of a unit of data in a memory array is called its ________.

A. storage B. RAM

C. address D. data

66. On a CD-ROM, ________ are recessed areas representing a 0.

A. mounds B. lands

C. holes D. pits

67. Why is a refresh cycle necessary for a dynamic RAM?

A. to clear the flip-flops

B. to set the flip-flops

C. The refresh cycle discharges the capacitor cells.

 D. The refresh cycle keeps the charge on the capacitor cells.

68. Which is not a magnetic storage device?

A. Magnetic disk

B. Magnetic tape

C. Magneto-optical disk

D. Optical disk

69. The time from the beginning of a read cycle to the end of tACS or tAA is referred to as:

A. access time

B. data hold

C. read cycle time

D. write enable time

70. Which of the following memories is volatile?

A. ROM B. EROM

C. RAM D. Flash

1. The refresh period for capacitors used in DRAMs is ________.

A. 2 ms

B. 2 s

C. 64 ms

D. 64 s

72. What is the principal advantage of using address multiplexing with DRAM memory?

A. reduced memory access time

 B. reduced requirement for constant refreshing of the memory contents

C. reduced pin count and decrease in package size

It eliminates the requirement for a chip-select input line, thereby reducing the pin
D. count.

73. What is a multitap digital delay line?

A. a series of inverter gates with RC circuits between each one

B. a series of inverter gates with RL circuits between each one

C. a series of NAND gates with RC circuits between each one

D. a series of NAND gates with RL circuits between each one

74. The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is
________.

A. 4096 B. 8129

C. 16358 D. 32768

75. How many 8 k 1 RAMs are required to achieve a memory with a word capacity of 8 k and a
word length of eight bits?

A. Eight B. Four

C. Two D. One

76. The mask ROM is ________.

A. MOS technology

B. diode technology

C. resistor-diode technology
 D. DROM technology

77. Which of the following is not a flash memory mode or operation?

A. Burst B. Read

C. Erase D. Programming

78. For the given circuit, what is the bit length of the output data word?

A. 3 B. 4

C. 8 D. 32

79. The smallest unit of binary data is the ________.

A. bit B. nibble

C. byte D. word

80. Select the statement that best describes the fusible-link PROM.

A. user-programmable, one-time programmable

B. manufacturer-programmable, one-time programmable

C. user-programmable, reprogrammable
 D. manufacturer-programmable, reprogrammable

81. How can UV erasable PROMs be recognized?

A. There is a small window on the chip.

B. They will have a small violet dot next to the #1 pin.

C. Their part number always starts with a "U", such as in U12.

They are not readily identifiable, since they must always be kept under a small
D.
cover.

82. What part of a Flash memory architecture manages all chip functions?

A. I/O pins

B. floating-gate MOSFET

C. command code

D. program verify code

83. An 8-bit address code can select ________.

A. 8 locations in memory

B. 256 locations in memory

C. 65,536 locations in memory

D. 131,072 locations in memory

84. Eight bits of digital data are normally referred to as a:

A. group. B. byte.

C. word. D. cell.

85. Which is not a hard disk performance parameter?

 A. Seek time

B. Break time

C. Latency period

D. Access time

86. The ideal memory ________.

A. has high storage capacity

B. is nonvolatile

C. has in-system read and write capacity

D. has all of the above characteristics

87. To which pin on the RAM chip does the address decoder connect in order to signal which
memory chip is being accessed?

A. The address input

B. The output enable

C. The chip enable

D. The data input

88. EEPROM stands for ________.

A. encapsulated electrical programmable read-only memory

B. elementary electrical programmable read-only memory

C. electrically erasable programmable read-only memory

D. elementary erasable programmable read-only memory

89. L1 is known as ________.

 A. primary cache

B. secondary cache

C. DRAM

D. SRAM

90. Describe the timing diagram of a write operation.

First the data is set on the data bus and the address is set, then the write pulse stores
A.
the data.

First the address is set, then the data is set on the data bus, and finally the read pulse
B.
stores the data.

First the write pulse stores the data, then the address is set, and finally the data is set
C.
on the data bus.

First the data is set on the data bus, then the write pulse stores the data, and finally
D.
the address is set.

91. What is the bit storage capacity of a ROM with a 1024 8 organization?

A. 1024 B. 2048

C. 4096 D. 8192

92. Which of the following is one of the basic characteristics of DRAMs?

A. DRAMs must have a constantly changing input.

B. DRAMs must be periodically refreshed in order to be able to retain data.

C. DRAMs have a broader "dynamic" storage range than other types of memories.

D. DRAMs are simpler devices than other types of memories.

93. The main advantage of semiconductor RAM is its ability to:

 A. retain stored data when power is interrupted or turned off

B. be written to and read from rapidly

C. be randomly accessed

D. be sequentially accessed

94. Which of the following describes the action of storing a bit of data in a mask ROM?

A. A 1 is stored in a bipolar cell by opening the base connection to the address line.

B. A 0 is stored in a bipolar cell by shorting the base connection to the address line.

C. A 1 is stored by connecting the gate of a MOS cell to the address line.

D. A 0 is stored by connecting the gate of a MOS cell to the address line.

95. Address decoding for dynamic memory chip control may also be used for:

A. controlling refresh circuits

B. read and write control

C. chip selection and address location

D. memory mapping
Previous Question Papers

Code No: R05210504

Set No. 1
II B.Tech I Semester Regular Examinations, November 2008
DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering, Information Technology
and Computer Science & Systems Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1.Convert the following to Decimal and then to Hexadecimal.

(e) 12348
(f) 12678
(g) 110011112
(h) 110111012
(i) 78610
(f) 55510 [3+3+3+3+2+2]

2. (a) Find the complement of the following and show that F.F = 0 and F + F = 1.
i. F = xy + xy
ii. F = (x + y + z)(x + z)(x + y).
(b) Obtain the Dual of the following Boolean expressions. [8+8]
BCD + (B + C + D) + BCDE
AB + (AC) + (AB + C)
ABC + ABC + ABC + ABC
AB + (AC) + ABC.

3. (a) Construct K-map for the following expression and obtain minimal SOP ex-
pression. Implement the function with 2-level NAND -NAND form.
f (A, B, C, D) = (A
+ C + D) A + B + D A + B + C A + B + D A + B + D
(b) Implement the following Boolean function F using the two - level form: [8+8]
i. NAND-AND
ii. AND-NOR F (A, B, C, D) = 0, 1, 2, 3, 4, 8, 9, 12

4. (a) Implement 64 1 multiplexer with four 16 1 and one 4 1 multiplexer. (Use

only block diagram).
(b) A combinational logic circuit is defined by the following Boolean functions.
F1 = ABC + AC
F2 = ABC + AB

F3 = ABC + AB
Design the circuit with a decoder and external gates. [8+8]
 Set No. 1

1 of 2

Code No: R05210504

5. A sequential circuit with 3 D-flip-flops A, B and C has only one input X and one
output X with following relationship
DA = B C X, DB = A, DC = B
(a) Draw the logic diagram of the circuit.
(b) Obtain logic diagram, state table and state diagram. [16]
6. (a) Draw and explain 4-bit universal shift register.
(b) Explain dierent types of shift registers. [8+8]
7. (a) Draw and explain the block diagram of PAL.
(b) Implement the following Boolean functions using PAL.
w(A,B,C,D) = m (0,2,6,7,8,9,12,13)
x (A,B,C,D) = m (0,2,6,7,8,9,12,13,14)
y (A,B,C,D) = m (2,3,8,9,10,12,13)
z (A,B,C,D) = m (1,3,4,6,9,12,14). [6+10]

8. (a) Describe the operation of the SR Latch using NAND gate with the help of truth
table, transition table and the circuit.

(b) Explain the operation and use of De bounce circuit. [8+8]

2 of 2
 Set No. 2
Code No: R05210504

II B.Tech I Semester Regular Examinations, November 2008

DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering, Information Technology and Computer
Science & Systems Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. (a) Perform the following using BCD arithmetic. [4+4]

i. 126310 + 968710
ii. 767210 + 337810
(b) Convert the following:
)
i. 99710 = ( 16
ii. 25710 = ( )8
iii. 65410 = ( )2
)
iv. 10116 = ( 10 [2+2+2+2]
2. (a) Express the following functions in sum of minterms and product of maxterms.
i. (xy + z) ( y + xz)
ii. BD + AD + BD.
(b) Obtain the complement of the following Boolean expressions. [8+8]
i. ABC + ABD + AB
ii. ABC + ABC + ABCD
iii. ABCD + ABCD? + ABCD
iv. AB + ABC.
3. (a) If
F1(A, B, C ) = A B C
F2 (A, B, C ) = A C B
Show that = F1 = F2
(b) Show that A B AB = A + B
(c) Obtain minimal SOP expression for the complement of the given expression:
F (A, B, C ) =Q (1, 2, 5, 7) And draw the circuit using NOR - gates. [4+4+8]

4. (a) A multiple output combinational logic circuit is defined by the following func-tions.
Draw the schematic circuits for F1 and F2.

F1 (A, B, C, D) = A AD A + BC
F2 (A, B, C, D) = AD A + BC
Using K-Maps simplify F1 and F2 and draw the reduced diagram circuit.

1 of 2
Code No: R05210504 Set No. 2

(b) Design a full - subtractor circuit with three inputs x,y,z and outputs D, B. The
circuit subtracts X - Y - Z where Z is the input borrow, B is the output
borrow and D is the dierence draw the circuit using NAND gates. [8+8]
5. (a) Define the following terms related to filp-flops.
i. set-up time
ii. hold time
iii. propagation delay
iv. preset and
v. clear.
(b) Distinguish between combinational logic and sequential logic. [10+6]
6. (a) Design a 4-bit ring counter using T- flip flops and draw the circuit diagram and
timing diagrams.
(b) Draw the block diagram and explain the operation of serial transfer between
two shift registers and draw its timing diagram. [8+8]

7. (a) Explain the block diagram of a memory unit. Explain the read and write operation
a RAM can perform.

(b) i. How many 32K * 8 RAM chips are needed to provide a memory capacity of
256K bytes.
ii. How many lines of the address must be used to access 256K bytes? How
many of these lines are connected to the address inputs of all chips?
iii. How many lines must be decoded for the chip select inputs? Specify the
size of the decoder. [8+8]
8. Reduce the number of states in the state table listed below. Use an implication
table. [16]

Present state Next state Output

x=0 x=1 x=0 x=1

a f b 0 0

b d c 0 0

c f e 0 0

d g a 0 0

e d c 0 0

f f b 1 1

g g h 0 1

h g a 1 0

2 of 2
 Set No. 3
Code No: R05210504

II B.Tech I Semester Regular Examinations, November 2008

DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering, Information Technology
and Computer Science & Systems Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. (a) Explain dierent methods used to represent negative numbers in binary sys-
tem. [6]
(b) Perform the subtraction with the following unsigned binary numbers by taking the
2s complement of the subtrahend. [52]
i. 11010 - 10110
ii. 11011 - 1001
iii. 100 - 110100
iv. 1010101 - 1010101
v. 11 - 1101.
2. (a) Convert the following expressions in to sum of products and product of sums.
i. (AB + C) ( B + CD)
ii. x + x(x + y)(y + z).
(b) Obtain the Dual of the following Boolean expressions. [8+8]
i. (AB + AC)(BC + BC)(ABC)
ii. ABC + ABC + ABC
iii. (ABC)(A + B + C)
iv. A + BC (A + B + C).

3. (a) Construct K-map for the following expression and obtain minimal SOP ex-
pression. Implement the function with 2-level NAND -NAND form.
f (A, B, C, D) = (A
+ C + D) A + B + D A + B + C A + B + D A + B + D
(b) Implement the following Boolean function F using the two - level form: [8+8]
i. NAND-AND
ii. AND-NOR F (A, B, C, D) = 0, 1, 2, 3, 4, 8, 9, 12

4. (a) Implement 64 1 multiplexer with four 16 1 and one 4 1 multiplexer. (Use

only block diagram).
(b) A combinational logic circuit is defined by the following Boolean functions.
F1 = ABC + AC
F2 = ABC + AB

F3 = ABC + AB
Design the circuit with a decoder and external gates. [8+8]
1 of 2
 Set No. 3
Code No: R05210504

5. A sequential circuit with 3 D-flip-flops A, B and C has only one input X and one
output X with following relationship
DA = B C X, DB = A, DC = B

(a) Draw the logic diagram of the circuit.

(b) Obtain logic diagram, state table and state diagram. [16]

6. Draw the sequential circuit for serial adder using shift registers, full adder and
D-FF. Explain its operation with state equations and state table . [16]

7. Derive the PLA programming table and the PLA structure for the combinational circuit
that squares a 3- bit number. Minimize the number of product terms. [16]

8. (a) What do you mean by hazard? Classify and explain.

(b) Draw the logic diagram of the product of sums expression:
Y= (x1 + x2) ( x2 + x3). Show that there is a 0-hazard when x1 and x3 are equal to
0 and x2 goes from 0 to 1. Find a way to remove the hazard by
adding one or more OR gate. [8+8]

2 of 2
 Set No. 4
Code No: R05210504

II B.Tech I Semester Regular Examinations, November 2008

DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering, Information Technology
and Computer Science & Systems Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. (a) Explain, How error occurred in a data transmission can be detected using
parity bit.
[6
]
(b) Perform the subtraction with the following unsigned binary numbers by taking the
2s complement of the subtrahend. [52]
i. 111011 - 111000
ii. 1110-110110
iii. 10010-1101
iv. 110-10100
v. 11011-10000.
2. (a) Reduce the following Boolean expressions.
i. (AB + AC)(BC + BC)(ABC)
ii. ABC + ABC + ABC
iii. (ABC)(A + B + C)
iv. A + BC (A + (BC))
(b) Obtain the Dual of the following Boolean expressions. [8+8]
i. ABC + AB + ABC
ii. (BC + AD)(AB + CD)
iii. xyz + xz
iv. xy + x (wz + wz).
3. (a) If F1= 3,4,7,8,11,14,15 and F2= 1,2,4,5,7,8,10,11,12,15 obtain minimal SOP
expression for F1 F 2 and draw the circuit using NAND gates.
(b) Draw the two -level NAND circuit for the following Boolean - expression:

AB + CD E + BC (A + B) also obtain minimal SOP expression and draw

the circuit using NAND gates. [8+8]

4. (a) Implement 64 1 multiplexer with four 16 1 and one 4 1 multiplexer. (Use

only block diagram).
(b) A combinational logic circuit is defined by the following Boolean functions.
F1 = ABC + AC
F2 = ABC + AB

F3 = ABC + AB
Design the circuit with a decoder and external gates. [8+8]
1 of 2
Code No: R05210504 Set No. 4

5. Convert the following:

(a) J-K flip-flop to T- flip-flop

(b) R-S flip-flop to J-K-flip-flop
(c) J-K flip-flop to D- flip-flop
(d) R-S flip-flop to D-flip-flop. [4+4+4+4]

6. (a) Explain synchronous and ripple counters. Compare their merits and demerits.
(b) Design a modulo -12 up synchronous counter using T- flip flops and draw the
circuit diagram. [8+8]

7. (a) Explain the block diagram of a memory unit. Explain the read and write operation
a RAM can perform.
(b) i. How many 32K * 8 RAM chips are needed to provide a memory capacity of
256K bytes.
ii. How many lines of the address must be used to access 256K bytes? How
many of these lines are connected to the address inputs of all chips?
iii. How many lines must be decoded for the chip select inputs? Specify the
size of the decoder. [8+8]

8. Reduce the number of states in the state table listed below. Use an implication
table. [16]

Present state Next state Output

x=0 x=1 x=0 x=1

a f b 0 0

b d c 0 0

c f e 0 0

d g a 0 0

e d c 0 0

f f b 1 1

g g h 0 1

h g a 1 0

2 of 2
Tutorial Sheet

Date: Topics Revised

Date: Topics Revised

Date: Topics Revised

Date: Topics Revised

 2

Date: Topics Revised

Date: Topics Revised

TOPICS BEYOND SYLLABUS

S.No. Topic

3.

4.

5.

6.
 3

ASSESMENT OF COURSE OUTCOMES: DIRECT

Blooms Taxonomy:
LEVEL 1 REMEMBERING Exhibit memory of previously learned material by recalling facts,
terms, basic concepts, and answers
LEVEL 2 UNDERSTANDING Demonstrate understanding of facts and ideas by organizing,
comparing, translating, interpreting, giving descriptions, and
stating main ideas.
LEVEL 3 APPLYING Solve problems to new situations by applying acquired
knowledge, facts, techniques and rules in a different way

LEVEL 4 ANALYZING Examine and break information into parts by identifying motives
or causes. Make inferences and find evidence to support
generalizations.
LEVEL 5 EVALUATING Present and defend opinions by making judgments about
information, validity of ideas, or quality of work based on a set of
criteria.
LEVEL 6 CREATING Compile information together in a different way by combining
elements in a new pattern or proposing alternative solutions.

*Attach course assessment sheet

 4

ASSESMENT OF COURSE OUTCOMES: INDIRECT

CSP Rubric
S.N Criteria
LEVEL ( Level : 3-Excellent Level :2-Good Level : 1-Poor)
0
Student speaks in phase with the given topic confidently using Audio-Visual aids. Vocabulary is
3
Communicati

good
Student speaking without proper planning, fair usage of Audio-Visual aids. Vocabulary is not
Oral

1 2
on

good
Student speaks vaguely not in phase with the given topic. No synchronization among the talk and
1
Visual Aids
Proper structuring of the document with relevant subtitles, readability of document is high with
3
Writing Skills

correct use of grammar. Work is genuine and not published anywhere else
Information is gathered without continuity of topic, sentences were not framed properly. Few
2 2
topics are copied from other documents
Information gathered was not relevant to the given task, vague collection of sentences. Content is
1
copied from other documents
Student identifies most potential ethical or societal issues and tries to provide solutions for them
3
Awareness

discussing with peers

Social and
Ethical

Student identifies the societal and ethical issues but fails to provide any solutions discussing with
3 2
peers
1 Student makes no attempt in identifying the societal and ethical issues
3 Student uses appropriate methods, techniques to model and solve the problem accurately
Knowledg
Content

2 Student tries to model the problem but fails to solve the problem
4 1 Student fails to model the problem and also fails to solve the problem
e

3 Listens carefully to the class and tries to answer questions confidently

Participat
Student

2 Listens carefully to the lecture but doesnt attempt to answer the questions
ion

5
1 Student neither listens to the class nor attempts to answer the questions
The program structure is well organized with appropriate use of technologies and methodology.
3 Code is easy to read and well documented. Student is able to implement the algorithm producing
analytical Skills
Technical and

accurate results
Program structure is well organized with appropriate use of technologies and methodology. Code
6 2 is quite difficult to read and not properly documented. Student is able to implement the algorithm
providing accurate results.
Program structure is not well organized with mistakes in usage of appropriate technologies and
1
methodology. Code is difficult to read and student is not able to execute the program
7 3 Independently able to write programs to strengthen the concepts covered in theory
Pr

tic
ac

al
 5

2 Independently able to write programs but not able to strengthen the concepts learned in theory
Not able to write programs and not able to strengthen the concepts learned in theory
1

Student uses appropriate methods, techniques to model and solve the problem accurately in the
3
Understanding of
Engineering core

context of multidisciplinary projects

Student tries to model the problem but fails to solve the problem in the context of
2
8 multidisciplinary projects
Student fails to model the problem and also fails to solve the problem in the context
1 of multidisciplinary projects

*Attach course assessment sheet

 6

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