This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2015.2424246, IEEE Transactions on Power Electronics
1

A New Multi-Input Three-Level DC/DC Converter

Serkan Dusmez, Student Member, IEEE, Xiong Li, Student Member, IEEE, and Bilal Akin, Senior Member, IEEE

Electrical and Computer Science Department, Power Electronics and Drives Laboratory
University of Texas at Dallas
Richardson, TX, USA
serkan.dusmez@utdallas.edu; li.xiong@utdallas.edu; bilal.akin@utdallas.edu

Abstract Power electronics solutions based on multiple

converter configurations offer cost-effective solutions by
integrating a number of components at input or output power
stages. This paper proposes a new multi-input isolated three-level
converter for renewable and sustainable energy systems adopting
high dc link voltage. Multiple dc sources are integrated to the
three-level dc/dc converter before the isolation stage, resulting in
reduced part-count, determining dc link voltage level and
allowing flexibility in transformer design. The proposed
architecture eliminates two boost switches which are present in
the two-stage counterpart. The input inductors are operated in
discontinuous conduction mode; thus, power can be shared
between input sources through proper selection of input
inductors. A low voltage prototype has been designed to serve as a
proof of concept.
Index Termsmulti-input converter, three-level converter,
renewable energies, dc/dc converter, pulsating current cell.
I. INTRODUCTION
Multi-input converters offer a cost effective solution in
applications which requires multiple input sources such as fuel
cell vehicles and renewable energy systems [1]-[12]. The basic
idea is to integrate a number of converters in either input dc/dc
conversion stage or in isolation stage, in addition to commonly
shared output stage. There are various multi-input topologies
proposed in literature based on non-isolated [13]-[18] and
isolated structures [19]-[22]. In [13], a non-isolated multi-
input buck/boost converter sharing the same switch has been
proposed. A similar concept has been applied to four-switch
bidirectional buck boost converter, where input sources are
connected in parallel [14]. Each input source is interfaced with
an individual buck switch, and the remaining three switches
are shared by the input sources. In [15], two boost converters
are connected in series and an auxiliary circuit is used to
achieve soft-switching. A general derivation for non-isolated
parallel-integrated multi-input converters including SEPIC and
Cuk has been reported in [16]. In [17], a different approach
based on switched capacitor converter has been reported.
For multi-input converters providing galvanic isolation,
majority of the work has been devoted to phase-shifted full-
bridge converters. In [19], two identical current fed full-bridge
converters are connected in parallel to interface a common
output rectifying diode-bridge. Similar concept has been
applied using individual output rectification stages but sharing
an integrated transformer in [20]. In [21], two current fed
bridges are controlled in a phase-shifted manner. In [22], the
S1 C1 Lo
L1n D1n
L11 D11 D7
V1n
V11 S2
Co Ro
L2n D2n D21
V2n
L21 S3
V21 D8
S4 C2
Fig. 1. Proposed multi input isolated three-level DC/DC converter.
the parallel connection of multi-input cells are first identified
as pulsating voltage-source cell and pulsating current-source
cell, and various topological combinations have been
presented. However, majority of the isolated multi-input
converters presented in literature are proposed as individual
converters or shares only the output stage on the secondary
side of the transformer. In [23], the concept of paralleling
multiple input sources at the primary side of the transformer
has been proposed.
In this study, a new multi-input converter based on three-
level structure for renewable energy systems is proposed, as
shown in Fig. 1. Following the concept proposed in [23],
pulsating current-source (PCC) cells are integrated to the same
bridge before the isolation stage, while the adopted bridge
offers utilizing low voltage rated upper and lower switches due
to the three-level structure. The control of PCCs is integrated
to the operation of the three-level bridge converter. Thus, the
control complexity of the proposed converter is similar to that
of a three-level dc/dc converter [24]. On the other hand, the
proposed converter provides reduced part-count and lower
voltage stress across the upper and lower switches. The input
inductors are operated in discontinuous conducting mode
(DCM), which allows autonomous power sharing between
input sources with proper selection of input inductors.
This manuscript is organized as follows: Section II
introduces the new multi-input three-level integrated DC/DC
converter and explains the operation modes in detail. In
Section III, the dynamics of converter is extracted, design
procedure is explained and a design example for variable input
sources is given. The simulation and experimental results for a
low-voltage prototype are presented in Section IV. Finally, the
study is summarized and conclusion is derived in Section V.

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2

0.5 The switches S2-S3, and S1-S4 have 180o phase shift with
D2 D1 respect to each other. The duty cycle of the middle switches
Dr2 Dr1 should be greater than 50% such that they allow a
freewheeling path for the transformer primary side current.
S1 The switching scheme is as follows; S1 is turned on right after
S3 is turned off, and similarly, S4 is turned on when S2 is turned
S2 off. A dead-time should be inserted in between the turning on
S3 instant of S1 and turning off instant of S3, and likewise between
switching of S2 and S4 to avoid short circuit.
S4
vL1 vL1 iL1 B. Operation Principle
iL1 v1 The operation modes of the circuits, which are given in
v1 v1-vdc Fig. 3, are explained in this section. It should be noted that
L1 L1 these operation modes are valid when iL2>iL1. For this case,
vL2 vL2 v1-vdc iL2 iL2,pk is higher than primary side of the transformer at steady-
iL2 v2
state. Under this condition, iL1,pk is smaller than primary side of
v2 v2-vdc the transformer at steady-state. If iL1>iL2, the equivalent circuits
L2 L2 would be different from the one presented here. Basically, the
v2-vdc charging/discharging current of C1 and C2 would be exhanged.
vtr vdc -2Nvo vdc Interval 1 [t<t0]: Before t0, S3 is off and S1 is on. The energy
vtr itr 2N2Lo 2 stored in L2 is released to the load through the primary winding
itr of the transformer. The excess energy is transferred to C1
-vo through conducting the body diode of S1. Thus, S1 can be
vdc
-vo NLo vdc turned on under zero voltage with proper time delay. The
2N -
iLo vLo 2
current of L1 increases linearly under V1. Total current of L2
charges C2. Meanwhile, Vdc/2 is applied to the primary side of
vLo the transformer.
iLo iL1 t V1 / L1
V v t v t / L
iL 2 t
2 C1 C2 2

-vo vC1 t iL 2 t / C1 NiLo t / C1

t0 t1 t2 t3 t4 t5 t6 t7 t8 d / dt
vC 2 t iL 2 t / C2
Fig. 2. Gating scheme and key waveforms. i t v t / NL v t / L
Lo C1 o Co o

II. PROPOSED MULTI-INPUT ISOLATED THREE-LEVEL DC/DC
v
Co t Lo o Co o o
i t / C v t / C R
(1)
CONVERTER
A. Topology Description Interval 2 [t0<t<t1]: At t=t0, the current of L1 becomes equal
to that of primary side of the transformer. From this moment
The proposed multi-input converter is essentially based on on, C1 discharges over the primary side of the transformer to
the operation of the three-level isolated dc/dc converter. The the load. The current of C2 is equal to that of L2. The state
secondary side rectifier can be either a half-bridge rectifier equations are same as in Eq. (1).
accompanied by a tapped winding for low output voltage
application, or a full-bridge rectifier for high output voltage Interval 3 [t1<t<t2]: At t=t1, the currents of L2 and C2 reach to
applications as shown in Fig. 1. Since the PWM scheme here zero. The load current is solely supplied by C1. The current of
is similar to that in three-level converters, the control L1 continues to store energy under the influence of V1.
complexity is not intensive. The boost inductors, connected to
iL1 t V1 / L1
the input sources of different voltages, are charged when S2
and S3 are turned on, respectively. When the related switch (S2 iL 2 t 0
or S3) is turned off, the energy stored in the inductor is vC1 t NiLo t / C1
d / dt
vC 2 t
transferred to the load. The excess or insufficient energy is 0

either absorbed or compensated by the dc link capacitors. At i t vC1 t / NLo vCo t / Lo
the same time, S1 to S4 are switched to apply Vdc/2, Vdc/2, and Lo

zero voltage across the primary side of the transformer. In vCo t iLo t / Co vCo t / Co Ro (2)
comparison with the two-stage counterpart, two active
switches and boost diodes are eliminated, while two blocking Interval 4 [t2<t<t3]: In the beginning of this interval, S1 is
diodes are added to block the reverse current from the dc link turned off. The current in the leakage inductance conducts D7
capacitors. and the primary side current freewheels, hence, zero voltage is
The switching scheme of the converter is given in Fig. 2.

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3

(a) (b) (c)

(d) (e) (f)

(g) (h) (j)

Fig. 3. Operation intervals of the converter; a) interval 1: t 0<t<t1, b) interval 2: t1<t<t2, c) interval 3: t2<t<t3, d) interval 4: t3<t<t4, e) interval 5: t4<t<t5, f)
interval 6: t5<t<t6, g) interval 7: t6<t<t7, h) interval 8: t7<t<t8, j) interval 8: t8<t<t9.

applied across the primary side of the transformer. The output before, peak current of L1 is smaller than the load current for
inductor voltage is equal to Vo and the output inductor current this case. Thus, C2 discharges over to the load and Vdc/2 is
decreases linearly. applied across the primary side of the transformer. The current
of L2 continues to store energy under the influence of V2.
iL1 t V1 / L1
iL1 t V1 vC1 t vC 2 t / L1
L2
i t 0
iL 2 t
V2 / L2
vC1 t 0
d / dt vC1 t iL1 t / C1
vC 2 t 0 d / dt
i t vCo t / Lo vC 2 t iL1 t / C2 NiLo t / C2
i t
vC 2 t / NLo vCo t / Lo
Lo

vCo t iLo t / Co vCo t / Co Ro Lo
(3) vCo t iLo t / Co vCo t / Co Ro
(5)
Interval 5 [t3<t<t4]: At t=t3, S3 is turned on, while S2 is kept
on. The primary side current continues to freewheel and zero Interval 7 [t5<t<t6]: At t=t5, the energy stored in L1 is
voltage is applied across the primary side; hence, the output completely transferred out. Its current reaches to zero at DCM.
inductor current continuous to decrease under output voltage. The load current is solely supplied by C2.
Meantime, V2 is applied across L2, and current increases iL1 t 0
linearly storing energy in L2.
iL 2 t V2 / L2
iL1 t V1 / L1 vC1 t 0
d / dt
iL 2 t V2 / L2 vC 2 t NiLo t / C2
vC1 t 0 i t v t / NL v t / L
d / dt Lo
C2 o Co o

vC 2 t 0 vCo t iLo t / Co vCo t / Co Ro (6)
i t vCo t / Lo
Lo

vCo t iLo t / Co vCo t / Co Ro (4)
Interval 8 [t6<t<t7]: In this interval, S4 is turned off. The
current in the leakage inductance conducts D8 and the primary
Interval 6 [t4<t<t5]: At t=t4, S2 is turned off. The stored side current freewheels, hence, zero voltage is applied across
energy in L1 is released to the load as well as to C1. As stated the primary side of the transformer. The current of L2

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continues to increase. iL1, pk

iL1 t 0
iL1 d1 d r1 (13)
2

iL 2 t V2 / L2 By substituting Eq. (11) into Eq. (13), an expression which
vC1 t 0 relates dr1 with d1 and iL1 can be derived.
d / dt
vC 2 t 0 d r1
2 iL1 L1
d1 (14)
i t vCo t / Lo V1d1Ts
Lo

vCo t iLo t / Co vCo t / Co Ro (7) The averaged inductor currents over the switching period can
be found by inserting Eq. (14) into Eq. (9) as
Interval 9 [t7<t<t8]: At t=t7, S2 is turned on while S3 remains vC1 vC 2 2i V v v
at on-state. The primary side current continues to circulate diL1 / dt d1 L1 1 C1 C 2 (15)
L1 d1Ts V1
through D8. The current of both inductors L1 and L2 increase
linearly under the applied input voltages. vC1 vC 2 2i V v v
diL 2 / dt d1 L 2 2 C1 C 2 (16)
iL1 t V1 / L1 L2 d1Ts V2

iL 2 t V2 / L2 By using the same conversion and principle, the averaged
vC1 t 0 expressions for the state variables of dc link capacitor
d / dt
C 2
v t 0 voltages, output inductor and voltage can be found

analogously. These state-equations are of paramount
i t v t / L
Lo
Co o
significance in analyzing the dynamic behavior of the
vCo t iLo t / Co vCo t / Co Ro converter as well as in designing the controller.
(8)
iL1 iL 2 d12Ts V2 V1 NiLo
III. ANALYSIS OF THE PROPOSED CONVERTER dvC1 / dt d2 (17)
C1 2C1 L2 L1 C1
A. Averaged State-Variables iL1 iL 2 d12Ts V2 V1 NiLo
In order to obtain the averaged values for state variables, the dvC 2 / dt d2 (18)
C2 2C2 L2 L1 C2
expressions for state variables given in Eq. (1) to Eq. (8) are
averaged over the given time intervals. The input inductor vC1 vC 2 v
current can be averaged over the switching period as diLo / dt d 2 Co (19)
NLo Lo
V V v v
diL1 / dt 1 d1 1 C1 C 2 d r1 (9) iLo v
L1 L1 dvCo / dt Co (20)
Co Co Ro
where, dr1 denotes the duty ratio of the time interval in which
inductor current decreases from its peak value to zero, when
the boost switch is turned off. dr1 is a function of state B. Design Considerations
variables; however it is yet neither a state nor a control As denoted in Section II, the minimum duty ratio of the
variable. To substitute dr1 with state variables, one can use middle two switches, D1, should be at least 50%, in order to
voltage-balance law of inductor. When the boost switch is apply zero voltage to the primary side of the transformer. The
turned on, the peak inductor current becomes remaining 50% is shared between the duty ratios of S1 and S4,
V denoted by D2, and control signal of S2 and S3, denoted by
iL1, pk 1 d1Ts (10) D1. This leaves a margin for the control of duty ratios of S2
L1
and S3.
When the boost switch is turned off, it becomes, D1 0.5 D1 (21)
V v v
iL1, pk 1 C1 C 2 d r1Ts (11) where,
L1
D1 0.5 D2,max (22)
Equalizing Eqs. (10) and (11), and solving it for dr1 yields
V1 1) Determination of Lo, D2, D1: The load side of the
d r1 d1 (12)
V1 vC1 vC 2 converter can be designed to operate in either CCM or DCM
This conversion expresses dr1 in terms of control variable, d1 mode. The output inductor current can be continuous or
and state variables vC1 and vC2. Substituting Eq. (12) into Eq. discontinuous depending on the design criteria, or else it might
(9) results in diL1/dt=0; thus losing the dynamic inductor be designed such that the operation of the converter can transit
current information, which can be referred as reduced order to DCM at light load condition to reduce the size of the output
modeling. In order to obtain a full order model, the average inductor. The required output inductance value can be
inductor current expression can be used for finding out dr1. determined by Eq. (23).

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5

0.5 D2 Drx 0.5 D2 Drx

S1 S1
S2 S2
S3 S3
S4 S4

vx vx vtr iLx
vtr iLx
ix vx ix vx
vtr vtr
vdc
Vx-
2
Vx- vdc Vx- vdc
(a) (b)
Fig. 4. DCM/CCM boundary cases; a) input inductor current reaches to zero within D2Ts, b) input inductor current reaches to zero within (D2+Drx)Ts,

Vo 2 0.5 Dmin
Lo
2 Px f s
where, Px represents the minimum output power at which the
converter is desired to be operated in CCM. When output
inductor operates in CCM mode, D2 can be expressed as in Eq.
(24) at steady-state.
NVo
D2,max
Vdc ,min
where, N represents the turns ratio of the transformer windings.
The equivalent duty ratio for DCM mode can be written as
2 Lo
D2
V
2
RTs dc 1 1
NVo
Depending on the operation mode, N can be found from
either Eq. (24) or Eq. (25). Once D2,max and Vdc,min are
determined, D1 and the limits for D1 can be found using Eq.
(21) and (22).
2) Determination of DCM Boundary and DC Link Voltage:
In this paper, the operation principle is based on operating
input inductors in DCM. This is due to the fact that input
sources are controlled by D1 and their voltages can be
different, only one of the cells would be able to operate in
CCM, while the other one would continue operating in DCM.
Once one of the input sources transits to CCM, the continuous
current forces to apply Vdc to the other input, which keeps the
voltage of latter at the same level; hence, latter continues to
provide same amount of power in DCM mode. The rest of the
necessary power is supplied from the input source operating in
CCM. This operation could be considered for applications
where output power of one of the input sources is maximized
to definite value, while the secondary input source provides
rest of the load power demand.
The operation modes shown in Fig. 3 has been given
considering that the input inductors are well chosen for DCM
operation under any load, and input inductor currents reach to
zero within D2Ts. In case this interval lasts longer depending
on the chosen parameters and output power, there could be one
(23) more operation mode, which was not shown in Fig. 3. It is yet
necessary to analyze this operation mode in order to define the
CCM/DCM boundary. In such a circumstance, after the
operation interval 7, the upper inductor would still continue to
provide energy to the upper capacitor even after S4 is turned
off under the influence of Vdc/2. The voltage of the primary
side of the transformer remains at zero since D8 conducts.
(24) Relevant waveforms are illustrated in Fig. 4.
To find the boundary operation point, one should consider
that the inductor current reaches to zero at the end of the
switching period. The critical dc link voltage can be found
through the expression of the voltage balance equality of the
inductor, as
(25)
V
Vx D1 Vdc ,crt Vx D2 dc ,crt Vx 1 D1 D2
2 (26)
where Vx denote the voltage of the input source that provides
higher output power. The lowest DC link voltage that should
be adopted for DCM operation can be expressed as,
2Vx
Vdc ,crt (27)
D2 D1 1
For DCM operation, the following condition should be
satisfied; Vdc,min>Vdc,crt.
3) Determination of L1 and L2: In this paper, the operation
principle is based on operating input inductors in DCM. For
the proposed converter, the duty ratios of S2 and S3 are the
same, and equal to D1. Hence, the output power of each cell is
proportional to the square of its input voltage, and inversely
proportional to the inductance. The total power fed by the
input sources can be expressed as
Vdc D12Ts n
Vn 2
Po L V (28)
dc Vn
2 1 n
Thus, with proper design of these parameters with respect to
behaviors of input source, an autonomous power sharing is
possible. Based on Eq. (28), there are various possibilities to
determine L. The bottom boundaries for Ln based on Vdc,min and

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250

P=1.4
200
P=1.0
L1(H)

150 P=0.7

100

50
80 140 200 240
L2(H)
Fig. 5. Inductance determination based on power sharing when V1=V1,min,
V2=V2,min.

Fig. 7. Power can be drawn from the second input source at Vdc=500V under
DCM mode.

Fig. 6. Power can be drawn from the first input source at Vdc=500V under
DCM mode.
output power are defined as
Vdc D1,max 2Ts n Vn,min 2
Pmax
2
L V
1 Vn,min
n dc ,min
(29)
The values of the inductances can be determined for rated
power, which would fall into the boundary defined above. The
determination of inductances depends on the application
needs. For instance, for PV generation systems, the
inductances can be calculated according to the desired load
sharing at the maximum power operation point.
C. Design Example
The design procedure for constant power loads with
constant input voltage sources is straight-forward. Thus, this
section illustrates a design procedure for an application with
dynamic variables having the parameters of V1,min=110V,
V1,max=130V, V2,min=100V, V2,max=150V, Vo=200V,
Ptot,max=1.2kW, fs=50kHz. In typical bridge-type isolated
converters, the duty ratio of the second stage, D2, is between
0.48 and 0.25. Since there is a limitation on the duty cycles in
the proposed converter, as stated in Eq. (21) and Eq. (22),
D1,max can be set to 0.7, where D1 becomes 0.2. In this case,
D2,max is equal to 0.3. Using Eq. (27), the critical dc link
voltage, Vdc,crt, is calculated as 500V; thus, Vdc,min is
determined as 500V. From Eq. (24), transformer turns ratio is
calculated as 0.75.
Based on the condition given in Eq. (29), all possible L1 and
Fig. 8. Power can be drawn from both input sources at various DC link
voltages when V1=V1,min, V2=V2,min.
L2 combinations can be found. Another criterion in
determining the inductances is the power ratio among the input
sources at desired input voltages. For this design, the power
ratio of the second input source to the first input source at
maximum output power and minimum input voltages, denoted
as P, is evaluated. Based on the chosen P, the values of the
inductances can be determined as shown in Fig. 5. In this
study, P is determined as 0.7, which means that the second
source provides 500W and the first source provides 700W
under maximum load when V1=V1,min, and V2=V2,min. The
corresponding L1 and L2 values, are selected from Fig. 5;
L1=108H, L2=122H.
The output power capability of the first and second input
sources according to D1 and their respected voltages are
plotted in Fig. 6 and Fig. 7, respectively. As it can be seen
from the figures, the first input source provides 700W, while
the second one provides 500W to fulfill the load demand at
their respected minimum input voltages. On the other hand, the
power ratio becomes 1.23 when the voltages of the input
sources reach to highest values. The selection of the power
ratio is completely dependent on the application needs, and it
can be modified analogously. The total power supplied from
the input sources as a function of duty ratio and dc link
voltages for V1=V1,min, and V2=V2,min is plotted in Fig. 8. As
expected, higher dc link voltage results in lower output power

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Transformer Primary and Input Inductor Voltages [V] Transformer Primary and Input Inductor Voltages [V]
500 400
vtr vtr
200

0 0
-200
vL2 vL2 -400 vL2 vL2
-500
(a) Time [4s/div] (a) Time [4s/div]
Input Boost Inductor Currents [A] Input Boost Inductor Currents [A]
20 20
15 iL2 15 iL1 iL2
10
iL1
10
5 5
0 0
-5 -5
(b) Time [4s/div] (b) Time [4s/div]
Transformer Primary and Output Inductor Currents [A] Transformer Primary and Output Inductor Currents [A]
15 itr 15
10 itr
5 5
0 iLo iLo
-5 -5
-10
-15 -15
-20
(c) Time [4s/div] (c)
DC Bus Capacitor Voltage Ripples [V] DC Bus Capacitor Voltage Ripples [V]

0.5 0.5
vC1
vC2
vC1 vC2
0 0
(d) Time [4s/div] (d) Time [4s/div]
DC Bus Capacitor Currents [A] DC Bus Capacitor Currents [A]
20 20
10 10
0 0
-10 iC1 -10 iC2
iC2 iC1
-20 -20
-30 -30
(e) Time [4s/div] (e) Time [4s/div]
Fig. 9. Simulation waveforms when V1=V2=150V, L1=200H, L2=100H; a) Fig. 10. Simulation waveforms when V1=150V, V2=50V, L1=L2=100H; a)
Transformers primary winding voltage, and input inductor voltages; b) Input Transformers primary winding voltage, and input inductor voltages; b) Input
boost inductor currents; c) Transformers primary winding current and output boost inductor currents; c) DC bus capacitor voltage ripples; d) DC bus
inductor current; d) DC bus capacitor voltage ripples; e) DC bus capacitor capacitor currents.
currents.

for the same output voltage. This figure is of significant
importance to evaluate the converters output power capability
at different dc link voltages. As it can be seen, the total power
drawn from the input sources can be adjusted for the given
reference dc link voltage.
It should be noted that this part only illustrated a design
framework for DCM operation; however, as stated earlier, one
of the input sources can transit to CCM mode and supply the
rest of the demand power, which can be preferred in fuel cell
applications. Another point is that advantages of the proposed
converter become more apparent when input voltages and dc
link voltages are higher. The voltage specifications given for
this design procedure and simulation results given in the
following section are determined rather low to be suitable with
the designed low voltage proof-of-concept prototype.
IV. SIMULATION AND EXPERIMENTAL RESULTS
The simulations are performed to illustrate the operation of
the converter with different set of parameters in MATLAB
using SimPower Toolbox. The first simulation is conducted for
same input voltage and different inductances, while the second
one aims to illustrate the operation when inductances are the
same with different voltages. The first set of parameters as
follows; V1=V2=150V, L1=200H, L2=100H,
C1=C2=100F, Lo=330H , fsw=50kHz. The results are shown
in Fig. 9. The second set of parameters are; V1=150V,
V2=50V, L1=L2=100H, C1=C2=100F, Lo=330H,
fsw=50kHz.
In Fig. 9(a), it can be observed that even though same
voltage is applied to the inductors, the output power
contribution is different due to the chosen different
inductances. For this case, the output power is 1.6kW and

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8

duty ratio.
10V/div
S1
S2
S3
S4

20s/div
Fig. 12. Experimental waveforms of gate signals when D1=0.6, D2=0.35.
Fig. 11. Photo of the designed prototype.

5A/div
vdc 5A/div vdc
vtr 250V/div vtr iL2
100V/div
iL1
iL2 iL1
10A/div
10A/div
100V/div
5us/div 100V/div
20s/div
Fig. 13. Experimental results of dc link voltage, transformer voltage, input 14. Simulation results of dc link voltage, transformer voltage, input inductor
inductor currents when D1=0.6, D2=0.35, V1=70V and V2=90V. currents when D1=0.6, D2=0.35, V1=70V and V2=90V.

2A/div
iLo vo 25V/div
iLo
100V/div
vo

vtr 5A/div
100V/div
20s/div
vtr 5us/div 100V/div
Fig. 16. Simulation results of output voltage, transformer voltage, output
Fig. 15. Experimental results of output voltage, transformer voltage, output
inductor current when D1=0.6, D2=0.35, V1=70V and V2=90V.
inductor current when D1=0.6, D2=0.35, V1=70V and V2=90V.

S1 10V/div
iL2,pk>iL1,pk. The charging/discharging current of C2 is higher
than that of C1, resulting in asymmetrical voltage ripples S2
across two dc bus capacitors.
The corresponding results for latter simulation are given in S3
Fig. 10. As it can be seen from Fig. 10(a), the applied voltages
are different while the chosen inductances are same. For this
case, iL1,pk>iL2,pk and the capacitor charging currents and
S4
thereby the capacitor voltage ripples are replaced. It is worth 20s/div
mentioning that the feedback voltage signal should be
averaged over the switching period for capacitor voltage Fig. 17. Experimental waveforms of gate signals when D1=0.7, D2=0.25.
balancing.
Due to the asymmetry of the voltage source, the capacitor A low voltage laboratory built prototype has been designed
currents are different, resulting in different capacitor voltage and tested, as shown in Fig. 11, to serve as a proof-of-concept.
ripples. Like in any other multi-level converter, the capacitor The input inductances (L1=L2) are 87H each, dc link
voltages should be balanced. For the proposed converter, this capacitances (C1=C2) are 470F each. The output capacitor
(Co) is 220F and output inductor (Lo) is 200H. The
can be achieved by adding a compensating signal to the duty
secondary side of the transformer has a tapped winding
ratio of S1 and S4, which either extends or shortens its effective
configuration followed by a half-bridge rectifier. The

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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9

transformer has 1:1 turns ratio for each secondary winding. in Fig. 17. In Fig. 18 and Fig. 19, both input source voltages
vdc 5A/div
vdc
5A/div
vtr 250V/div vtr
100V/div
iL2
iL1
iL2 iL1 10A/div
10A/div
100V/div
5us/div 100V/div
20s/div
Fig. 18. Experimental results of dc link voltage, transformer voltage, input Fig. 19. Simulation results of dc link voltage, transformer voltage, input
inductor currents when D1=0.7, D2=0.25, V1=70V and V2=70V. inductor currents when D1=0.7, D2=0.25, V1=70V and V2=70V.

vdc 5A/div vdc

5A/div
vtr 250V/div
100V/div
iL2 iL1
20s/div
Fig. 20. Experimental results of dc link voltage, transformer voltage, input
inductor currents when D1=0.7, D2=0.25, V1=70V and V2=100V.
5A/div
vtr vdc 5A/div
250V/div
100V/div
iL2
iL1
20s/div
Fig. 22. Experimental results of dc link voltage, transformer voltage, input
inductor currents when D1=0.7, D2=0.25, V1=60V and V2=110V.
The ratings of the switches are 600V/22A. The switching
frequency is 50kHz. The pulse pattern is generated using
Texas Instruments floating point DSP.
The tests are conducted for two different duty cycles. The
experimental results are verified with simulation results under
the same operation conditions. Fig. 12 portrays the switching
pattern when D1=0.6 and D2=0.35. It should be noted that the
inverse of the gating signals are shown here due to the
hardware configuration. The experimental and simulation
results for V1=70V and V2=90V are shown in Fig. 13, and Fig.
14, respectively. The peak current of the first inductor is 9.5A,
whereas the peak of the second inductor is 12.5A. In this
case, the power ratio of the second source to the first one is
1.8. The output voltage and current are around 75V, and 9.2A,
respectively, as shown in Fig. 15. On the other hand, these
values are little higher in the simulation due to ideal and
lossless components, as it can be seen from Fig. 16.
In the second set of experiments, D1 and D2 are adjusted to
0.7 and 0.25, respectively. The first source voltage is varied
between 60V-70V, while the second source voltage is swept
from 70V-110V. The gating signals of the switches are given
vtr iL2
iL1
10A/div
10A/div
100V/div
5us/div 100V/div
Fig. 21. Simulation results of dc link voltage, transformer voltage, input
inductor currents when D1=0.7, D2=0.25, V1=70V and V2=100V.
vdc
vtr iL2
iL1
10A/div
10A/div
100V/div
5us/div 100V/div
Fig. 23. Simulation results of dc link voltage, transformer voltage, input
inductor currents when D1=0.7, D2=0.25, V1=60V and V2=110V.
are set to 70V. As seen from the figures, both sources supply
9.5A peak current, and share the load demand equally. In Fig.
20 and Fig. 21, the second source voltage is set to 100V. The
peak current is increased to 14.5A. The power distribution of
the second source to the first source becomes 2.15. In Fig. 22
and Fig. 23, the experimental and simulation results for
V1=60V and V2=110V are given, from which a large difference
between the provided powers can be clearly observed. The
peak current of the second source is 17.5A, whereas the first
one provides peak current of 7A. The power distribution is
3.75.
The experimental efficiency data of the converter under
three different operating conditions are presented in Table I,
and divided into its individual loss components. The proposed
converter exhibited %87-%88.6 efficiency under the given test
conditions. For a fair comparison, a two-stage counterpart is
built by unplugging the input sources from the power
terminals, and connecting two interleaving boost legs to the dc
link. The switching scheme and operating conditions are kept
same as of the proposed converter. The two-stage counterpart
exhibits higher efficiency than the proposed one, between
%89.4-%90.1. Thus, the efficiency of the proposed single-

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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10

stage converter is %1.5-%2.4 lower than the two-stage V. CONCLUSIONS

Table I. Efficiency Comparison Data
In this study, a new multi-input dc/dc converter having same
V1=70V V2=90V V1=70V V2=100V V1=60V V2=70V
number of active switches as of three-level isolated dc/dc
D1=60 D2=35 D1=70 D2=25 D1=70 D2=25 converter without introducing additional switching actions is
Two- Prop. Two- Prop. Two- Prop. proposed. The circuit analysis and design consideration has
Stage Conv. Stage Conv. Stage Conv.
been provided in detail. With proper selection of input
Conduction Losses [W]
inductors, autonomous load sharing can be achieved. To verify
PBD_S1 0.02 0.9 0.02 0.7 0.01 0.75
the operation of the converter, simulations of different
PBD_S2 0.02 0.15 0.03 0.13 0.02 0.07
PBD_S3 0.01 0.05 0.01 0.02 0.01 0.02 parameters have been performed. A low voltage laboratory
PBD_S4 0.04 1.3 0.05 1.2 0.02 0.9 built prototype has been designed and tested under varying
PD_Clamp1 0.9 0.86 1.6 1.6 1.1 1.1 input voltages and duty cycles. The results prove the effective
PD_Clamp2 0.8 0.78 1.6 1.5 1.06 1.06 integrated operation of input sources with three-level isolated
PD_Boost1 0.6 - 0.4 - 0.5 -
PD_Boost2 1.2 - 1.1 - 0.78 - dc/dc structure, through operating four switches in a phase-
PD_Block1 - 2.3 - 2.8 - 2.1 shifted manner without introducing control complexity.
PD_Block2 - 3.4 - 4.4 - 2.7
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http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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11

[16] A. Kwasinski, Identification of Feasible Topologies for Multiple-

Input DCDC Converters, IEEE Trans Power Electron., vol. 24, no. 3, Bilal Akin (S03M08-SM13) received the B.S.
pp. 856-861, Mar. 2009. and M.S. degrees in electrical engineering from
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converter based on switched-capacitor, IET Power Electron., vol. 6, in 2000 and 2003, respectively, and the Ph.D.
no. 9, pp. 1909-1916, Nov. 2013. degree in electrical engineering from the Texas
[18] H. Wu, J. Zhang, and Y. Xing, A Family of Multi-Port Buck-Boost A&M University, College Station, TX, USA, in
Converters Based on DC-Link-Inductors (DLIs), IEEE Trans Power 2007.
Electron., vol. 30, no.2, pp. 735-746, Feb. 2015. He was an R&D Engineer with Toshiba Industrial
Division, Houston, TX, USA, from 2005 to 2008.
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From 2008 to 2012, he worked as an R&D Engineer at C2000 Embedded
Based on the Multiwinding Transformer for Renewable Energy
Control Group, Texas Instruments Incorporated. Since 2012, he has been with
Applications, IEEE Trans Ind. Appl., vol. 38, no. 4, pp. 1096-1104,
University of Texas at Dallas as Assistant Professor. His research interests
Jul/Aug. 2002. include advanced control methods in motor drives, real-time fault diagnosis
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30, no. 4, pp. 2050-2062, Apr. 2015.

Serkan Dusmez (S11) received the B.S. (Hons)

and M.S. degrees in electrical engineering from
Yildiz Technical University, Istanbul, Turkey, in
2009 and 2011, respectively. He received the M.S.
degree in electrical engineering from Illinois
Institute of Technology, Chicago, in 2013. He is
currently working toward the Ph.D. degree at the
University of Texas at Dallas.
From 2012-2013, he worked as a Faculty Research
Assistant in the Power Electronics, Energy
Harvesting and Renewable Energies Laboratory (PEHREL) in the Electrical
and Computer Engineering Department at the University of Maryland at
College Park. He is the author/co-author of over 40 journal and conference
papers. His research interests include design of power electronic interfaces
and energy management strategies for renewable energy sources, integrated
power electronic converters for plug-in electric vehicles, and real-time fault
diagnosis of power converters.

Xiong Li (S13) received his B. E. degree in

Electrical Engineering from the Central South
University, Changsha, China, in 2011. He has been
with the Power Electronics and Drives Lab since
Fall 2012. He is currently pursuing the Ph. D.
degree at the University of Texas at Dallas. His
research interests include design and control of
multilevel converters for renewable energy systems,
and integrated power electronic converters. He is
currently an intern at the Tesla Motors Inc.

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