Note:

PI Power input
PO Power output
I Signal input
O Signal output
I/O Signal input/output
Diff Differential signal

BGA
Pin Singal name Description I/O
pin Mode 0 Mode 1
1 5VIN 5V main power supply,up to 3A PI
2 GND Digital ground
3 5VIN 5V main power supply,up to 3A PI
4 GND Digital ground
5 5VIN 5V main power supply,up to 3A PI
6 GND Digital ground
7 5V_CONTRRL 5V main power supply control I
8 NC Not connected
9 3P3V 3.3V main power supply,up to 3A PO
10 2P5V 2.5V main power supply,up to 1A PO
11 3P3V 3.3V main power supply,up to 3A PO
12 RGMII_VDD2V5 2.5V main power supply for LAN PO
13 3P3V 3.3V main power supply,up to 3A PO
14 OTG_VBUS USB_OTG power supply PI/PO E9 USB_OTG_VBUS
15 VDD_RTC RTC backup power supply,up to PI
16 NC 50mA
Not connected
17 POR_B System reset I/O C11 SRC_POR_B
18 DISP0_DAT0 LCD data bus I/O P24 IPU1_DISP0_DAT JIPU2_DISP0_D
0 AT0
19 GPIO1_27 GPIO I/O W21 OSC32K_32K_O ENET_RDATA0
UT
20 DISP0_DAT1 LCD data bus I/O P22 IPU1_DISP0_DAT JIPU2_DISP0_D
1 AT1

21 LCD_PWR_EN LCD power enable O W20 MLB_MLBCLK ENET_TDATA1

22 DISP0_DAT2 LCD data bus I/O P23 IPU1_DISP0_DAT JIPU2_DISP0_D

2 AT2
23 UART2_TXD UART transmit data O E24 WEIM_WEIM_D2 IPU1_DI1_PIN11
6
24 DISP0_DAT3 LCD data bus I/O P21 IPU1_DISP0_DAT JIPU2_DISP0_D
3 AT3
25 UART2_RXD UART receive data I E25 WEIM_WEIM_D2 IPU1_DI1_PIN13
7
26 DISP0_DAT4 LCD data bus I/O P20 IPU1_DISP0_DAT JIPU2_DISP0_D
4 AT4
27 UART2_CTS UART clear to send I B13 USDHC3_CMD UART2_CTS

28 DISP0_DAT5 LCD data bus I/O R25 IPU1_DISP0_DAT JIPU2_DISP0_D

5 AT5

29 UART2_RTS UART require to send O D14 USDHC3_CLK UART2_RTS

30 DISP0_DAT6 LCD data bus I/O R23 IPU1_DISP0_DAT JIPU2_DISP0_D

6 AT6

31 CSPI1_CLK SPI clock I/O C25 WEIM_WEIM_D1 ECSPI1_SCLK

6
32 DISP0_DAT7 LCD data bus I/O R24 IPU1_DISP0_DAT JIPU2_DISP0_D
7 AT7

33 CSPI1_MISO SPI master input, slave output I F21 WEIM_WEIM_D1 ECSPI1_MISO

7
34 DISP0_DAT8 LCD data bus I/O R22 IPU1_DISP0_DAT JIPU2_DISP0_D
8 AT8

35 CSPI1_MOSI SPI master output, slave input O D24 WEIM_WEIM_D1 ECSPI1_MOSI

8
36 DISP0_DAT9 LCD data bus I/O T25 IPU1_DISP0_DAT JIPU2_DISP0_D
9 AT9

37 CSPI1_CS1 SPI chip select I/O W6 ECSPI1_SS1 ENET_RDATA2

38 DISP0_DAT10 LCD data bus I/O R21 IPU1_DISP0_DAT JIPU2_DISP0_D

10 AT10

39 CSPI4_CLK SPI clock I/O H20 WEIM_WEIM_D2 ECSPI4_SCLK

1
40 DISP0_DAT11 LCD data bus I/O T23 IPU1_DISP0_DAT JIPU2_DISP0_D
11 AT11

41 CSPI4_MISO SPI master input, slave output I E23 WEIM_WEIM_D2 ECSPI4_MISO

2
42 DISP0_DAT12 LCD data bus I/O T24 IPU1_DISP0_DAT JIPU2_DISP0_D
12 AT12

43 CSPI4_MOSI SPI master output, slave input O G23 WEIM_WEIM_D2 I2C1_SDA

44 DISP0_DAT13 LCD data bus I/O R20 8
IPU1_DISP0_DAT JIPU2_DISP0_D
13 AT13

45 CSPI4_CS0 SPI chip select I/O J19 WEIM_WEIM_D2 IPU1_DI1_PIN15

9
46 DISP0_DAT14 LCD data bus I/O U25 IPU1_DISP0_DAT JIPU2_DISP0_D
14 AT14

47 CSPI4_CS1 SPI chip select I/O H19 WEIM_WEIM_A2 ECSPI4_SS1

5
48 DISP0_DAT15 LCD data bus I/O T22 IPU1_DISP0_DAT JIPU2_DISP0_D
15 AT15

49 GND Digital ground

50 DISP0_DAT16 LCD data bus I/O T21 IPU1_DISP0_DAT JIPU2_DISP0_D
16 AT16
51 SD2_CLK MMC/SD/SDIO clock I/O C21 USDHC2_CLK ECSPI5_SCLK

52 DISP0_DAT17 LCD data bus I/O U24 IPU1_DISP0_DAT JIPU2_DISP0_D

17 AT17
53 SD2_DATA0 MMC/SD/SDIO data bus I/O A22 USDHC2_DAT0 ECSPI5_MISO

54 DISP0_DAT18 LCD data bus I/O V25 IPU1_DISP0_DAT JIPU2_DISP0_D

18 AT18
55 SD2_DATA1 MMC/SD/SDIO data bus I/O E20 USDHC2_DAT1 ECSPI5_SS0

56 DISP0_DAT19 LCD data bus I/O U23 IPU1_DISP0_DAT JIPU2_DISP0_D

19 AT19
57 SD2_DATA2 MMC/SD/SDIO data bus I/O A23 USDHC2_DAT2 ECSPI5_SS1

58 DISP0_DAT20 LCD data bus I/O U22 IPU1_DISP0_DAT JIPU2_DISP0_D

20 AT20

59 SD2_DATA3 MMC/SD/SDIO data bus I/O B22 USDHC2_DAT3 ECSPI5_SS3

60 DISP0_DAT21 LCD data bus I/O T20 IPU1_DISP0_DAT JIPU2_DISP0_D

21 AT21
61 SD2_DATA4 MMC/SD/SDIO data bus I/O A19 RAWNAND_D4 USDHC1_DAT4

62 DISP0_DAT22 LCD data bus I/O V24 IPU1_DISP0_DAT JIPU2_DISP0_D

22 AT22
63 SD2_DATA5 MMC/SD/SDIO data bus I/O B18 RAWNAND_D5 USDHC1_DAT5

64 DISP0_DAT23 LCD data bus I/O W24 IPU1_DISP0_DAT JIPU2_DISP0_D

23 AT23
65 SD2_DATA6 MMC/SD/SDIO data bus I/O E17 RAWNAND_D6 USDHC1_DAT6

66 DISP0_HSYNC LCD horizontal sync O N25 IPU1_DI0_PIN2 IPU2_DI0_PIN2

67 SD2_DATA7 MMC/SD/SDIO data bus I/O C18 RAWNAND_D7 USDHC1_DAT7

68 DISP0_VSYNC LCD vertical sync O N20 IPU1_DI0_PIN3 IPU2_DI0_PIN3

69 SD2_WP MMC/SD/SDIO data write protect O T1 ESAI1_FST OBSERVE_MUX

_OBSRV_INT_O
UT2
70 DISP0_DRDY LCD enable O N21 IPU1_DI0_PIN15 IPU2_DI0_PIN15

71 SD2_CMD MMC/SD/SDIO command I/O F19 USDHC2_CMD ECSPI5_MOSI

72 DISP0_CLK LCD pixel clock O N19 IPU1_DI0_DISP_ IPU2_DI0_DISP_

CLK CLK
73 SD2_CD SD card detect I R6 ESAI1_HCKT OBSERVER_MU
X_OBSRV_INT_
OUT3
74 UART3_CTS UART clear to send I D25 WEIM_WEIM_D2 IPU1_DI0_D0_C
3 S
75 GND Digital ground
76 UART3_RTS UART require to send O D15 USDHC3_RST UART3_RTS

77 SD1_CLK MMC/SD/SDIO clock I/O D20 USDHC1_CLK ECSPI5_SCLK

78 UART3_TXD UART transmit data O F22 WEIM_WEIM_D2 ECSPI4_SS2

4
79 SD1_WP MMC/SD/SDIO data write protect O W22 MLB_MLBSIG ENET_RDATA1

80 UART3_RXD UART receive data I G22 WEIM_WEIM_D2 ECSPI4_SS3

5
81 SD1_CMD MMC/SD/SDIO command I/O B21 USDHC1_CMD ECSPI5_MOSI
82 GND Digital ground
83 SD1_CD SD card detect I B15 USDHC3_DAT3 UART3_CTS
84 SATA_RXP Positive differential SATA receive Diff B14 SATA_RXP
signal
85 SD1_DATA0 MMC/SD/SDIO data bus I/O A21 USDHC1_DAT0 ECSPI5_MISO

86 SATA_RXN Negative differential SATA receive Diff A14 SATA_RXN

signal
87 SD1_DATA1 MMC/SD/SDIO data bus I/O C20 USDHC1_DAT1 ECSPI5_SS0

88 SATA_TXN Negative differential SATA transmit Diff B12 SATA_TXN

signal
89 SD1_DATA2 MMC/SD/SDIO data bus I/O E19 USDHC1_DAT2 ECSPI5_SS1

90 SATA_TXP Positive differential SATA transmit Diff A12 SATA_TXP

signal
91 SD1_DATA3 MMC/SD/SDIO data bus I/O F18 USDHC1_DAT3 ECSPI5_SS2

92 GND Digital ground

93 SD1_DATA4 MMC/SD/SDIO data bus I/O A18 RAWNAND_D0 USDHC1_DAT4

94 PCIE_RXM Negative differential PCIE receive Diff B1 PCIE_RXM

signal
95 SD1_DATA5 MMC/SD/SDIO data bus I/O C17 RAWNAND_D1 USDHC1_DAT5

96 PCIE_RXP Positive differential PCIE receive Diff B2 PCIE_RXP

signal
97 SD1_DATA6 MMC/SD/SDIO data bus I/O F16 RAWNAND_D2 USDHC1_DAT6

98 PCIE_TXM Negative differential PCIE transmit Diff A3 PCIE_TXM

signal
99 SD1_DATA7 MMC/SD/SDIO data bus I/O D17 RAWNAND_D3 USDHC1_DAT7

100 PCIE_TXP Positive differential PCIE transmit Diff B3 PCIE_TXP

signal
101 GPIO7_6 GPIO I/O A15 USDHC3_DAT2

102 PCIE_WAKEn Wake-up by PCIE I R7 ESAI1_HCKR OBSERVE_MUX

_OBSRV_INT_O
UT0
103 UART1_RXD UART receive data I E13 USDHC3_DAT6 UART1_RXD_M
UX

104 PRSNT2_N_X1 PCIE reset O R2 ESAI1_TX3_RX2 ENET_1588_EVE

NT2_IN
105 UART1_TXD UART transmit data O F13 USDHC3_DAT7 UART1_TXD_MU
X

106 PCIE_REFCLK_DN Negative differential PCIE reference Diff C7 PCIE_REFCLK_D

clock signal N
107 uP_NMIn Touch panel interrupt O F15 RAWNAND_CE0
N
108 PCIE_REFCLK_DP Positive differential PCIE reference Diff D7 PCIE_REFCLK_D
clock signal P
109 GPIO6_9 GPIO I/O E15 RAWNAND_RES IPU2_SISG5
ETN

110 GND Digital ground

111 GPIO6_16 GPIO I/O D16 RAWNAND_CE3 IPU1_SISG1
N

112 HDMI_D2P Positive differential HDMI transmit Diff K4 HDMI_D2P

signal of channel 2
113 GPIO6_7 GPIO I/O C15 RAWNAND_CLE IPU2_SISG4

114 HDMI_D2M Negative differential HDMI transmit Diff K3 HDMI_D2M

signal of channel 2
115 GPIO6_10 GPIO I/O B16 RAWNAND_REA IPU2_DI0_PIN1
DY0

116 HDMI_D1P Positive differential HDMI transmit Diff J4 HDMI_D1P

signal of channel 1
117 GPIO6_15 GPIO I/O A17 RAWNAND_CE2 IPU1_SISG0
N
118 HDMI_D1M Negative differential HDMI transmit Diff J3 HDMI_D1M
signal of channel 1
119 GND Digital ground
120 HDMI_D0P Positive differential HDMI transmit Diff K6 HDMI_D0P
signal of channel 0
121 USB_HOST_DN Negative differential USB signal I/O F10 USB_H1_DN
122 HDMI_D0M Negative differential HDMI transmit Diff K5 HDMI_D0M
signal of channel 0
123 USB_HOST_DP Positive differential USB signal I/O E10 USB_H1_DP
124 HDMI_CLKP Positive differential HDMI clock Diff J6 HDMI_CLKP
125 USB_RSTn signal
USB reset O P6 ESAI1_TX ENET_RX_CLK

126 HDMI_CLKM Negative differential HDMI clock Diff J5 HDMI_CLKM

signal
127 GND Digital ground
128 HDMI_HPD HDMI hot plug detection I K1 HDMI_HPD
129 USB_OTG_DN Negative differential USB OTG I/O B6 USB_OTG_DN
130 GND signal
Digital ground
131 USB_OTG_DP Positive differential USB signal I/O A6 USB_OTG_DP
132 I2C1_SDA I2C data I/O N6 IPU1_CSI0_D8 WEIM_WEIM_D6

133 USB_OTG_ID Use this pin to detect the ID pin if I W23 NO_NAME_USB ENET_RX_ER
you use USB OTG. OTG_ID
134 I2C1_SCL I2C clock I/O N5 IPU1_CSI0_D9 WEIM_WEIM_D7

135 USB_H1_OC USB host over current signal I J20 WEIM_WEIM_D3 IPU1_DISP1_DA
0 T21
136 CAN1_TXD DCAN transmit data O R3 ESAI1_TX4_RX1 ECSPI5_RDY

137 USB_OTG_PWR_EN USB OTG power enable O V5 CAN2_RXCAN IPU1_SISG5

138 CAN1_RXD DCAN receive data I R5 ESAI1_TX5_RX0

139 USB_OTG_OC USB OTG over current signal I T6 CAN2_TXCAN IPU1_SISG4

140 I2C3_SCL I2C clock I/O R4 ESAI1_TX2_RX3 OBSERVE_MUX
_OBSRV_INT_O
UT4

141 GND Digital ground

142 I2C3_SDA I2C data I/O T3 ESAI1_SCKT OBSERVE_MUX
_OBSRV_INT_O
UT1
143 CSI_CLK0M Negative differential CSI clock Diff F4 CSI_CLK0M
144 UART5_TXD signal
UART transmit data O U7 ECSPI1_MISO ENET_MDIO

145 CSI_CLK0P Positive differential CSI clock signal Diff F3 CSI_CLK0P

146 UART5_RXD UART receive data I U6 ECSPI1_SS0 ENET_COL

147 CSI_D0M Negative differential CSI signal of Diff E4 CSI_D0M

channel 0
148 I2C2_SCL I2C clock I/O U5 ECSPI1_SS3 ENET_CRS

149 CSI_D0P Positive differential CSI signal of Diff E3 CSI_D0P

channel 0
150 I2C2_SDA I2C data I/O T7 OSC32K_32K_O ASRC_ASRC_EX
UT T_CLK
151 CSI_D1M Negative differential CSI signal of Diff D1 CSI_D1M
channel 1
152 GPIO7_1 GPIO I/O D13 USDHC3_DAT4 UART2_RXD_M
UX

153 CSI_D1P Positive differential CSI signal of Diff D2 CSI_D1P

channel 1
154 GPIO1_1 GPIO I/O T4 ESAI1_SCKR WDOG2_WDOG
_B
155 GND Digital ground
156 Touch_Int Touch panel interrupt O C16 RAWNAND_CE1 USDHC4_VSELE
N CT

157 CSI0_DAT12 CSI data bus I/O M2 IPU1_CSI0_D12 WEIM_WEIM_D8

158 LED_PWR_EN LED power enable O R1 ESAI1_TX0 ENET_1588_EVE

NT3_IN
159 CSI0_DAT13 CSI data bus I/O L1 IPU1_CSI0_D13 WEIM_WEIM_D9

160 RESET_N_B Reset signal O

161 CSI0_DAT14 CSI data bus I/O M4 IPU1_CSI0_D14 WEIM_WEIM_D1
0

162 GND Digital ground

163 CSI0_DAT15 CSI data bus I/O M5 IPU1_CSI0_D15 WEIM_WEIM_D1
1

164 LVDS0_TX3_N Negative differential LVDS transmit Diff W2 LDB_LVDS0_TX3

signal of channel 3 _N
165 CSI0_DAT16 CSI data bus I/O L4 IPU1_CSI0_D16 WEIM_WEIM_D1
2

166 LVDS0_TX3_P Positive differential LVDS transmit Diff W1 LDB_LVDS0_TX3

signal of channel 3 _P
167 CSI0_DAT17 CSI data bus I/O L3 IPU1_CSI0_D17 WEIM_WEIM_D1
3

168 LVDS0_TX2_N Negative differential LVDS transmit Diff V2 LDB_LVDS0_TX2

signal of channel 2 _N
169 CSI0_DAT18 CSI data bus I/O M6 IPU1_CSI0_D18 WEIM_WEIM_D1
4

170 LVDS0_TX2_P Positive differential LVDS transmit Diff V1 LDB_LVDS0_TX2

signal of channel 2 _P
171 CSI0_DAT19 CSI data bus I/O L6 IPU1_CSI0_D19 WEIM_WEIM_D1
5

172 LVDS0_TX1_N Negative differential LVDS transmit Diff U4 LDB_LVDS0_TX1

signal of channel 1 _N
173 CSI0_PIXCLK CSI pixel clock O P1 IPU1_CSI0_PIXC
LK

174 LVDS0_TX1_P Positive differential LVDS transmit Diff U3 LDB_LVDS0_TX1

signal of channel 1 _P
175 CSI0_HSYNC CSI horizontal sync O P4 IPU1_CSI0_HSY
NC

176 LVDS0_TX0_N Negative differential LVDS transmit Diff U2 LDB_LVDS0_TX0

signal of channel 0 _N
177 CSI0_VSYNC CSI vertical sync O N2 IPU1_CSI0_VSY WEIM_WEIM_D1
NC

178 LVDS0_TX0_P Positive differential LVDS transmit Diff U1 LDB_LVDS0_TX0

signal of channel 0 _P
179 CAM_RST CSI reset O G20 WEIM_WEIM_D2 ECSPI4_SS0
180 LVDS0_CLK_P Positive differential LVDS clock Diff V3 0
LDB_LVDS0_CLK
signal _P
181 CAM_EN CSI enable O G21 WEIM_WEIM_D1 ECSPI1_SS1
9
182 LVDS0_CLK_N Negative differential LVDS clock Diff V4 LDB_LVDS0_CLK
signal _N
183 CAM_MCLK CSI master clock O T5 CCM_CLKO

184 GND Digital ground

185 GND Digital ground
186 TRP0 Positive differential media- Diff
dependent interface 0 of Giga LAN
187 AUD3_TXC I2S bit clock O N1 IPU1_CSI0_D4 WEIM_WEIM_D2
188 TRN0 Negative differential media- Diff
dependent interface 0 of Giga LAN
189 AUD3_TXD I2S transmit data O P2 IPU1_CSI0_D5 WEIM_WEIM_D3

190 TRP1 Positive differential media- Diff

dependent interface 1 of Giga LAN
191 AUD3_TXFS I2S frame clock O N4 IPU1_CSI0_D6 WEIM_WEIM_D4

192 TRN1 Negative differential media- Diff

dependent interface 1 of Giga LAN
193 AUD3_RXD I2S receive data I N3 IPU1_CSI0_D7 WEIM_WEIM_D5

194 TRP2 Positive differential media- Diff

dependent interface 2 of Giga LAN
195 GND Digital ground
196 TRN2 Negative differential media- Diff
dependent interface 2 of Giga LAN
197 GPIO1_9 GPIO I/O T2 ESAI1_FSR WDOG1_WDOG
_B
198 TRP3 Positive differential media- Diff
dependent interface 3 of Giga LAN
199 TP_BUSY Touch panel busy signal I P5 KPP_COL5 ENET_1588_EVE
NT0_OUT
200 TRN3 Negative differential media- Diff
dependent interface 3 of Giga LAN
201 GPIO4_7 GPIO I/O V6 ECSPI1_MOSI ENET_TDATA3

202 LED_ACT LAN led active blinking I/O

203 GPIO4_6 GPIO I/O W5 ECSPI1_SCLK ENET_RDATA3

204 LED_LINK LAN led linking I/O

 Pin muxing
Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

ECSPI3_SCLK USDHC1_USDH SDMA_DEBUG GPIO4_21 MMDC_MMDC_

C_DEBUG0 _CORE_RUN DEBUG5
ESAIL1_HCKT SPDIF_OUT1 GPIO1_27 PHY_TMS

ECSPI3_MOSI USDHC1_USDH SDMA_DEBUG GPIO4_22 MMDC_MMDC_ PL301_MX6Q_P

C_DEBUG1 _EVENT_CHAN DEBUG6 ER1_HADDR12
NEL_SEL
ESAIL_TX2_RX ENET_1588_EV GPIO1_29 SATA_PHY_TDO
3 ENT0_IN
ECSPI3_MISO USDHC1_USDH SDMA_DEBUG GPIO4_23 MMDC_MMDC_ PL301_MX6Q_P
C_DEBUG2 _MODE DEBUG7 ER1_HADDR13
IPU1_CSI0_D1 IPU2_CSI1_D14 UART2_TXD_M GPIO3_26 IPU1_SISG2 IPU1_DISP1_DA
UX T22
ECSPI3_SS0 USDHC1_USDH SDMA_DEBUG GPIO4_24 MMDC_MMDC_ PL301_MX6Q_P
C_DEBUG3 _BUS_ERROR DEBUG8 ER1_HADDR14
IPU1_CSI0_D0 IPU2_CSI1_D13 UART2_RXD_M GPIO3_27 IPU1_SISG3 IPU1_DISP1_DA
UX T23
ECSPI3_SS1 USDHC1_USDH SDMA_DEBUG GPIO4_25 MMDC_MMDC_ PL301_MX6Q_P
C_DEBUG4 _BUS_RWB DEBUG9 ER1_HADDR15
CAN1_TXCAN USBOH3_UH3_ USBOH3_UH2_ GPIO7_2 MIPI_CORE_DP
DFD_OUT4 DFD_OUT4 HY_TEST_IN16
ECSPI3_SS2 AUDMUX_AUD6 SDMA_DEBUG GPIO4_26 MMDC_MMDC_ PL301_MX6Q_P
_RXFS _MATCHED_D DEBUG10 ER1_HADDR16
MBUS
CAN1_RXCAN USBOH3_UH3_ USBOH3_UH2_ GPIO7_3 MIPI_CORE_DP
DFD_OUT5 DFD_OUT5 HY_TEST_IN17
ECSPI3_SS3 AUDMUX_AUD6 SDMA_DEBUG GPIO4_27 MMDC_MMDC_ PL301_MX6Q_P
_RXC _RTBUFFER_W DEBUG11 ER1_HADDR17
RITE
IPU1_DI0_PIN5 IPU2_CSI1_D18 HDMI_TX_DDC GPIO3_16 I2C2_SDA
_SDA
ECSPI3_RDY USDHC1_USDH SDMA_DEBUG GPIO4_28 MMDC_MMDC_ PL301_MX6Q_P
C_DEBUG5 _EVENT_CHAN DEBUG12 ER1_HADDR18
NEL0
IPU1_DI0_PIN6 IPU2_CSI1_PIX DCIC1_DCIC_O GPIO3_17 I2C2_SCL PL301_MX6Q_P
CLK UT ER1_HBURST1
PWM1_PWMO WDOG1_WDOG SDMA_DEBUG GPIO4_29 MMDC_MMDC_ PL301_MX6Q_P
_B _EVENT_CHAN DEBUG13 ER1_HADDR19
NEL1
IPU1_DI0_PIN7 IPU2_CSI1_D17 PUI1_DI1_D0_C GPIO3_18 I2C3_SDA PL301_MX6Q_P
S ER1_HBURST2
PWM2_PWMO WDOG2_WDOG SDMA_DEBUG GPIO4_30 MMDC_MMDC_ PL301_MX6Q_P
_B _EVENT_CHAN DEBUG14 ER1_HADDR20
NEL2
CAN1_TXCAN KPP_COL2 ENET_MDC GPIO4_10 USBOH3_H1US PL301_MX6Q_P
B_PWRCTL_WA ER1_HADDR3
KEUP
USDHC1_USDH SDMA_DEBUG GPIO4_31 MMDC_MMDC_ PL301_MX6Q_P
C_DEBUG6 _EVENT_CHAN DEBUG15 ER1_HADDR21
NEL3
IPU1_DI0_PIN1 IPU2_CSI1_D11 USBOH3_USB GPIO3_21 I2C1_SCL SPDIF_IN1
7 OTG_OC
USDHC1_USDH SDMA_DEBUG GPIO5_5 MMDC_MMDC_ PL301_MX6Q_P
C_DEBUG7 _EVENT_CHAN DEBUG16 ER1_HADDR22
NEL4
IPU1_DI0_PIN1 IPU2_CSI1_D10 USBOH3_USB GPIO3_22 SPDIF_OUT1 PL301_MX6Q_P
OTG_PWR ER1_HWRITE
SDMA_DEBUG GPIO5_6 MMDC_MMDC_ PL301_MX6Q_P
_EVENT_CHAN DEBUG17 ER1_HADDR23
NEL5
ECSPI4_MOSI IPU2_CSI1_D12 UART2_CTS GPIO3_28 IPU1_EXT_TRIG IPU1_DI0_PIN13
AUDMUX_AUD5 SDMA_DEBUG GPIO5_7 MMDC_MMDC_ PL301_MX6Q_P
_RXFS _EVT_CHN_LIN DEBUG18 ER1_HADDR24
ES0
ECSPI4_SS0 UART2_RTS GPIO3-29 IPU2_CSI1_VSY IPU1_DI0_PIN14
NC
AUDMUX_AUD5 SDMA_DEBUG GPIO5_8 MMDC_MMDC_
_RXC _EVT_CHN_LIN DEBUG19
ES1
ECSPI2_RDY IPU1_DI1_PIN12 IPU1_DI0_D1_C GPIO5_2 HDMI_TX_CEC_ PL301_MX6Q_P
S LINE ER1_HBURST0
ECSPI1_SS1 ECSPI2_SS1 SDMA_DEBUG GPIO5_9 MMDC_MMDC_ PL301_MX6Q_P
_EVT_CHN_LIN DEBUG20 ER1_HADDR25
ES2

ECSPI2_MOSI AUDMUX_AUD5 SDMA_SDMA_ GPIO5_10 MMDC_MMDC_ PL301_MX6Q_P

_TXC EXT_EVENT0 DEBUG21 ER1_HADDR26
KPP_COL5 AUDMUX_AUD4 PCIE_CTRL_DI GPIO1_10 PHY_DTB1 SATA_PHY_DTB
_RXFS AG_STATUS_B 1
US_MUX9
ECSPI2_MISO AUDMUX_AUD5 SDMA_SDMA_ GPIO5_11 MMDC_MMDC_ PL301_MX6Q_P
_TXD EXT_EVENT1 DEBUG22 ER1_HADDR27
AUDMUX_AUD4 KPP_ROW7 GPIO1_15 DCIC2_DCIC_O
_RXD UT
ECSPI2_SS0 AUDMUX_AUD5 AUDMUX_AUD GPIO5_12 MMDC_MMDC_ WEIM_WEIM_C
_TXFS 4_RXFS DEBUG23 S2
WEIM_WEIM_C AUDMUX_AUD4 KPP_COL7 GPIO1_14 OCM_WAIT
S2 _TXFS
ECSPI2_SCLK AUDMUX_AUD5 AUDMUX_AUD GPIO5_13 MMDC_MMDC_ WEIM_WEIM_C
_RXD 4_RXC DEBUG24 S3
WEIM_WEIM_C AUDMUX_AUD4 KPP_ROW6 GPIO1_13 OCM_STOP
S3 _TXD
ECSPI1_SCLK AUDMUX_AUD4 SDMA_DEBUG GPIO5_14 MMDC_MMDC_ PL301_MX6Q_P
_TXC _EVT_CHN_LIN DEBUG25 ER1_HADDR28
ES7
KPP_COL6 AUDMUX_AUD4 PCIE_CTRL_DI GPIO1_12 SJC_DONE
_TXC AG_STATUS_B
US_MUX11
ECSPI1_MOSI AUDMUX_AUD4 SDMA_DEBUG GPIO5_15 MMDC_MMDC_ PL301_MX6Q_P
_TXD _BUS_DEVICE0 DEBUG26 ER1_HADDR29
GPU3D_GPU_D USBOH3_UH2_ USBOH3_UH3_ GPIO2_4 IPU1_IPU_DIAG IPU2_IPU_DIAG
EBUG_OUT4 DFD_OUT20 DFD_OUT20 _BUS4 _BUS4
ECSPI1_MISO AUDMUX_AUD4 SDMA_DEBUG GPIO5_16 MMDC_MMDC_ PL301_MX6Q_P
_TXFS _BUS_DEVICE1 DEBUG27 ER1_HADDR30
GPU3D_GPU_D USBOH3_UH2_ USBOH3_UH3_ GPIO2_5 IPU1_IPU_DIAG IPU2_IPU_DIAG
EBUG_OUT5 DFD_OUT21 DFD_OUT21 _BUS5 _BUS5
ECSPI1_SS0 AUDMUX_AUD4 SDMA_DEBUG GPIO5_17 MMDC_MMDC_ PL301_MX6Q_P
_RXD _BUS_DEVICE2 DEBUG28 ER1_HADDR31
GPU3D_GPU_D USBOH3_UH2_ USBOH3_UH3_ GPIO2_6 IPU1_IPU_DIAG IPU2_IPU_DIAG
EBUG_OUT6 DFD_OUT22 DFD_OUT22 _BUS6 _BUS6
AUDMUX_AUD6 MIPI_CORE_DP SDMA_DEBUG GPIO4_18 MMDC_MMDC_ PL301_MX6Q_P
_TXD HY_TEST_OUT3 _CORE_SATAE DEBUG2 ER1_HADDR9
GPU3D_GPU_D 0
USBOH3_UH2_ 2USBOH3_UH3_ GPIO2_7 IPU1_IPU_DIAG IPU2_IPU_DIAG
EBUG_OUT7 DFD_OUT23 DFD_OUT23 _BUS7 _BUS7
AUDMUX_AUD6 MIPI_CORE_DP SDMA_DEBUG GPIO4_19 MMDC_MMDC_ PL301_MX6Q_P
_TXFS HY_TEST_OUT3 _CORE_SATAE DEBUG3 ER1_HADDR10
KPP_ROW6 1
CCM_CCM_OU 3 CSU_CSU_ALA GPIO1_2 USDHC2_WP MLB_MLBDAT
T_1 RM_AUT0

AUDMUX_AUD6 MIPI_CORE_DP SDMA_DEBUG GPIO4_17 MMDC_MMDC_

_TXC HY_TEST_OUT2 _CORE_STATE DEBUG1
KPP_ROW5 9
AUDMUX_AUD4 1PCIE_CTRL_DI GPIO1_11
_RXC AG_STATUS_B
US_MUX10
MIPI_CORE_DP SDMA_DEBUG GPIO4_16 MMDC_MMDC_
HY_TEST_OUT2 _CORE_STATE DEBUG0
KPP_COL7 8
CCM_CCM_OU 0 CSU_CSU_ALA GPIO1_4 USDHC2_CD OCOTP_CTRL_
T_2 RM_AUT1 WRAPPER_FUS
E_LATCHED
UART3_CTS UART1_DCD IPU2_CSI1_DAT GPIO3_23 IPU1_DI1_PIN2 IPU1_DI1_PIN14
A_EN

PCIE_CTRL_DI USBOH3_UH3_ USBOH3_UH2_ GPIO7_8 MIPI_CORE_DP

AG_STATUS_B DFD_OUT10 DFD_OUT10 HY_TEST_IN22
US_MUX30
OSC32K_32K_ GPT_CLKIN GPIO1_20 PHY_DTB0 SATA_PHY_DTB
OUT 0
UART3_TXD_M ECSPI1_SS2 ECSPI2_SS2 GPIO3_24 AUDMUX_AUD5 UART1_DTR
UX _RXFS
ESAI1_FST ENET_1588_EV GPIO1_26 PHY_TCK
ENT3_OUT
UART3_RXD_M ECSPI1_SS3 ECSPI2_SS3 GPIO3_25 AUDMUX_AUD5 UART1_DSR
UX _RXC
PWM4_PWMO GPT_CMPOUT1 GPIO1_18

PCIE_CTRL_DI USBOH3_UH3_ USBOH3_UH2_ GPIO7_7 MIPI_CORE_DP

AG_STATUS_B DFD_OUT9 DFD_OUT9 HY_TEST_IN21
US_MUX29
CAAM_WRAPP GPT_CAPIN1 PCIE_CTRL_DI GPIO1_16 HDMI_TX_OPHY
ER_RNG_OSC_ AG_STATUS_B DTB1
OBS US_MUX8

PWM3_PWMO GPT_CAPIN2 PCIE_CTRL_DI GPIO1_17 HDMI_TX_OPHY

AG_STATUS_B DTB0
US_MUX7

GPT_CMPOUT2 PWM2_PWMO WDOG1_WDO GPIO1_19 WDOG1_WDOG

G_B _RST_B_DEB

GPT_CMPOUT3 PWM1_PWMO WDOG2_WDO GPIO1_21 WDOG2_WDOG

G_B _RST_B_DEB

GPU3D_GPU_D USBOH3_UH2_ USBOH3_UH3_ GPIO2_0 IPU1_IPU_DIAG IPU2_IPU_DIAG

EBUG_OUT0 DFD_OUT16 DFD_OUT16 _BUS0 _BUS0

GPU3D_GPU_D USBOH3_UH2_ USBOH3_UH3_ GPIO2_1 IPU1_IPU_DIAG IPU2_IPU_DIAG

EBUG_OUT1 DFD_OUT17 DFD_OUT17 _BUS1 _BUS1

GPU3D_GPU_D USBOH3_UH2_ USBOH3_UH3_ GPIO2_2 IPU1_IPU_DIAG IPU2_IPU_DIAG

EBUG_OUT2 DFD_OUT18 DFD_OUT18 _BUS2 _BUS2

GPU3D_GPU_D USBOH3_UH2_ USBOH3_UH3_ GPIO2_3 IPU1_IPU_DIAG IPU2_IPU_DIAG

EBUG_OUT3 DFD_OUT19 DFD_OUT19 _BUS3 _BUS3

PCIE_CTRL_DI USBOH3_UH3_ USBOH3_UH2_ GPIO7_6 MIPI_CORE_DP

AG_STATUS_B DFD_OUT8 DFD_OUT8 HY_TEST_IN20
US_MUX28
I2C3_SCL CCM_CLKO2 GPIO1_3 USBOH3_USBH MLB_MLBCLK
1_OC

PCIE_CTRL_DI USBOH3_UH3_ USBOH3_UH2_ GPIO6_18 MIPI_CORE_DP

AG_STATUS_B DFD_OUT1 DFD_OUT1 HY_TEST_IN13
US_MUX25
USDHC1_LCTL SPDIF_IN1 GPIO7_11 I2C3_SDA SJC_DE_B

PCIE_CTRL_DI USBOH3_UH3_ USBOH3_UH2_ GPIO6_17 MIPI_CORE_DP

AG_STATUS_B DFD_OUT0 DFD_OUT0 HY_TEST_IN12
US_MUX24

USBOH3_UH3_ USBOH3_UH2_ GPIO6_11 PL301_MX6Q_P

DFD_OUT15 DFD_OUT15 ER1_HSIZE2

PCIE_CTRL_DI USBOH3_UH3_ USBOH3_UH2_ GPIO6_9 MIPI_CORE_DP PL301_MX6Q_P

AG_STATUS_B DFD_OUT13 DFD_OUT13 HY_TEST_IN32 ER1_HSIZE0
US_MUX1
ESAI1_TX1 WEIM_WEIM_A PCIE_CTRL_DI GPIO6_16 IPU2_SISG1 TPSMP_CLK
26 AG_STATUS_B
US_MUX4

PCIE_CTRL_DI USBOH3_UH3_ USBOH3_UH2_ GPIO6_7 MIPI_CORE_DP TPSMP_HTRAN

AG_STATUS_B DFD_OUT11 DFD_OUT11 HY_TEST_IN23 S0
US_MUX31

PCIE_CTRL_DI USBOH3_UH3_ USBOH3_UH2_ GPIO6_10 MIPI_CORE_DP PL301_MX6Q_P

AG_STATUS_B DFD_OUT14 DFD_OUT14 HY_TEST_IN33 ER1_HSIZE1
US_MUX2

ESAI1_TX0 WEIM_WEIM_C CCM_CLKO2 GPIO6_15 IPU2_SISG0

RE

USDHC3_VSEL SDMA_SDMA_E ASRC_ASRC_E GPIO7_13 SNVS_HP_WRA SRC_SYSTEM_

ECT XT_EVENT1 XT_CLK PPER_SNVS_VI RST
O_5_CTL

ECSPI1_SCLK KPP_COL7 I2C1_SDA GPIO5_26 MMDC_MMDC_ ARM CORTEX

DEBUG47 A9 MPCORE
PLATFORM_TR
ACE5

ESAI1_HCKR SPDIF_IN1 ENET_1588_EV GPIO1_24 PHY_TDI

ENT2_OUT
ECSPI2_MOSI KPP_ROW7 I2C1_SCL GPIO5_27 MMDC_MMDC_ ARM CORTEX
DEBUG48 A9 MPCORE
PLATFORM_TR
ACE6

IPU1_DIO_PIN1 IPU1_CSI0_D3 UART3_CTS GPIO3_30 USBOH3_USBH PL301_MX6Q_P

1 1_OC ER1_HPROT0
EPIT1_EPITO CAN1_TXCAN UART2_TXD_M GPIO1_7 SPDIF_PLOCKUSBOH3_OTGU
UX SB_HOST_MOD
USBOH3_USBO KPP_ROW4 UART5_CTS GPIO4_15 MMDC_MMDC_ E
PL301_MX6Q_P
TG_PWR DEBUG50 ER1_HADDR8
EPIT2_EPITO CAN1_RXCAN UART2_RXD_M GPIO1_8 SPDIF_SRCLK USBOH3_OTGU
UX SB_PWRCTL_W
AKEUP
USBOH3_USBO KPP_COL4 UART5_RTS GPIO4_14 MMDC_MMDC_ PL301_MX6Q_P
TC_OC DEBUG49 ER1_HADDR7
KPP_ROW7 CCM_CLKO CSU_CSU_ALA GPIO1_5 I2C3_SCL ARM CORTEX
RM_AUT2 A9 MPCORE
PLATFORM_EV
ENTI

I2C3_SDA CCM_CCM_OU CSU_CSU_INT GPIO1_6 USDHC2_LCTL MLB_MLBSIG

T_0 _DEB

AUDMXU_AUD5 KPP_COL1 UART5_TXD_M GPIO4_8 USDHC1_VSELE PL301_MX6Q_P

_TXFS UX CT ER1_HADDR1

AUDMXU_AUD5 KPP_ROW1 UART5_RXD_M GPIO4_9 USDHC2_VSELE PL301_MX6Q_P

_RXD UX CT ER1_HADDR2

HDMI_TX_DDC KPP_COL3 I2C2_SCL GPIO4_12 SPDIF_IN1 PL301_MX6Q_P

_SCL ER1_HADDR5

HDMI_TX_DDC KPP_ROW3 I2C2_SDA GPIO4_13 USDHC1_VSELE PL301_MX6Q_P

_SDA CT ER1_HADDR6

PCIE_CTRL_DI USBOH3_UH3_ USBOH3_UH2_ GPIO7_1 MIPI_CORE_DP

AG_STATUS_B DFD_OUT3 DFD_OUT3 HY_TEST_IN15
US_MUX27

KPP_ROW5 PWM2_PWMO GPIO1_1 USDHC1_CD SRC_TESTER_

ACK

USDHC3_VSEL PCIE_CTRL_DI GPIO6_14 PL301_MX6Q_P

ECT AG_STATUS_B ER1_HREADYO
US_MUX3 UT
PCIE_CTRL_DI UART4_TXD_M SDMA_DEBUG GPIO5_30 MMDC_MMDC_ ARM CORTEX
AG_STATUS_B UX _PC6 DEBUG35 A9 MPCORE
US_MUX16 PLATFORM_TR
ACE9

CCM_PMIC_RD SDMA_SDMA_E SPDIF_OUT1 GPIO7_12 SJC_JTAG_ACT

Y XT_EVENT0
PCIE_CTRL_DI UART4_RXD_M SDMA_DEBUG GPIO5_31 MMDC_MMDC_ ARM CORTEX
AG_STATUS_B UX _PC7 DEBUG36 A9 MPCORE
US_MUX17 PLATFORM_TR
ACE10

PCIE_CTRL_DI UART5_TXD_M SDMA_DEBUG GPIO6_0 MMDC_MMDC_ ARM CORTEX

AG_STATUS_B UX _PC8 DEBUG37 A9 MPCORE
US_MUX18 PLATFORM_TR
ACE11

PCIE_CTRL_DI UART5_RXD_M SDMA_DEBUG GPIO6_1 MMDC_MMDC_ ARM CORTEX

AG_STATUS_B UX _PC9 DEBUG38 A9 MPCORE
US_MUX19 PLATFORM_TR
ACE12
PCIE_CTRL_DI UART4_RTS SDMA_DEBUG GPIO6_2 MMDC_MMDC_ ARM CORTEX
AG_STATUS_B _PC10 DEBUG39 A9 MPCORE
US_MUX20 PLATFORM_TR
ACE13

PCIE_CTRL_DI UART4_CTS SDMA_DEBUG GPIO6_3 MMDC_MMDC_ ARM CORTEX

AG_STATUS_B _PC11 DEBUG40 A9 MPCORE
US_MUX21 PLATFORM_TR
ACE14

PCIE_CTRL_DI UART5_RTS SDMA_DEBUG GPIO6_4 MMDC_MMDC_ ARM CORTEX

AG_STATUS_B _PC12 DEBUG41 A9 MPCORE
US_MUX22 PLATFORM_TR
ACE15

PCIE_CTRL_DI UART5_CTS SDMA_DEBUG GPIO6_5 MMDC_MMDC_

AG_STATUS_B _PC13 DEBUG42
US_MUX23

DIAG_STATUS_ SDMA_DEBUG GPIO5_18 MMDC_MMDC_ ARM CORTEX

BUS_MUX12 _PC0 DEBUG A9 MPCORE
PLATFORM
EVENTO

PCIE_CTRL_DI CCM_CLKO SDMA_DEBUG GPIO5_19 MMDC_MMDC_ ARM CORTEX

AG_STATUS_B _PC1 DEBUG30 A9 MPCORE
US_MUX13 PLATFORM_TR
CTL

PCIE_CTRL_DI SDMA_DEBUG GPIO5_21 MMDC_MMDC_ ARM CORTEX

AG_STATUS_B _PC3 DEBUG32 A9 MPCORE
US_MUX15 PLATFORM_TR
ACE0

IPU1_DI0_PIN1 IPU2_CSI1_D15 UART1_RTS GPIO3_20 EPIT2_EPITO

6

IPU1_DI0_PIN8 IPU2_CSI1_D16 UART1_CTS GPIO3_19 EPIT1_EPITO PL301_MX6Q_P

ER1_HRESP

KPP_COL5 ASRC_ASRC_E EPIT1_EPITO GPIO1_0 USBOH3_USBH SNVC_HP_WRA

XT_CLK 1_PWR P_PER_SNVC_
VIO_5

ECSPI1_SCLK KPP_COL5 AUDMUX_AUD GPIO5_22 MMDC_MMDC_ ARM CORTEX

3_TXC DEBUG43 A9 MPCORE
PLATFORM_TR
ACE1
ECSPI1_MOSI KPP_ROW5 AUDMUX_AUD GPIO5_23 MMDC_MMDC_ ARM CORTEX
3_TXD DEBUG44 A9 MPCORE
PLATFORM_TR
ACE2

ECSPI1_MISO KPP_COL6 AUDMUX_AUD GPIO5_24 MMDC_MMDC_ ARM CORTEX

3_TXFS DEBUG45 A9 MPCORE
PLATFORM_TR
ACE3

ECSPI1_SS0 KPP_ROW6 AUDMUX_AUD GPIO5_25 MMDC_MMDC_ ARM CORTEX

3_RXD DEBUG46 A9 MPCORE
PLATFORM_TR
ACE4

KPP_COL6 CCM_REF_EN_ PWM1_PWMO GPIO1_9 USDHC1_WP SRC_EARLY_R

B ST

SPDIF_OUT1 CCM_CLKO ECSPI1_RDY GPIO4_5 ENET_TX_ER SRC_INT_BOOT

AUDMUX_AUD5 KPP_ROW0 UART4_RXD_M GPIO4_7 DCIC2_DCIC_O PL301_MX6Q_P

_TXD UX UT ER1_HADDR0

AUDMUX_AUD5 KPP_COL0 UART4_TXD_M GPIO4_6 DCIC1_DCIC_O SRC_ANY_PU_

_TXC UX UT RST