2. HIGH SPEED IP BASED blocks. The designers will have to rely on pre-
existing building blocks with already verified
ARCHITECTURE FOR TELE COMMAND
functionality, with documentation and production test
SYSTEM Proceedings of Third IRF
vectors being available, and which have ultimately
International Conference, 07th March-2015,
been validated on silicon.
Mysore, India, ISBN: 978-93-82702-74-0
4. DESIGN OF SPACE DATA LINK
An IP (intellectual property) core is a block of logic
SUBLAYEROF TELECOMMAND
or data that is used for making a field programmable
DECODER USING CCSDS PROTOCOL-
gate array ( FPGA ) or application-specific integrated
ISSN (Print): 2278-5140, Volume-2, Issue 2,
circuit ( ASIC ) for a product. Design reuse IP cores
are part of the growing electronic design automation 2013
(EDA ) industry which allows the repeated use of This paper deals with the design of Space Data Link
previously designed components. Using many IP layer of a Telecommand Decoder using CCSDS
cores a system itself can be designed, System on protocol. Telecommand Decoder is a part of
Chip (SoC) offers this requirement. In the current Telecommand subsystem which receives uplinked
telecommand communication method, excess number data/ commands and distributes it to all subsystems.
of physical devices is present, which cause a major All commands received will be validated and
communication delay. Combining many of the thereafter depending on the address, commands will
predesigned internal blocks in to a single chip can be delivered to their respective destinations. Space
solve this problem. Data Link sublayer was designed to meet the
3. Designing Space Applications Using requirements of space missions for efficient transfer
of space application data or commands to control the
Synthesisable Cores- European Space Agency
Spacecraft. Space Data Link modules are designed
European Space Research and Technology
using CCSDS protocol and VHDL code for the same.
Centre (ESTEC) Postbus 299, NL-2200 AG
Simulation is performed using modelsim.
Noordwijk, The Netherlands
II. OBJECTIVE
Very high integration levels of microelectronics will
be required to fulfil the ever-increasing demands for The main objective of the project is to design and develop
high processing performance, low mass and power. architecture for Design of Tele command soc IP by using
With an increasing number of available gates on AES cryptographic method using VHDL. To overcome the
silicon, the functionality being implemented will shortfall of the present design where the major drawback has
move away from the use of traditional components to been the increased delay and decrease in frequency for
more advanced and complex systems within a single transmission of data packets. The new architecture is designed
device. To develop such complex circuits the design
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IDL - International Digital Library Of
Technology & Research
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Consumer demands for high performance and rich [6] Dr. PS. Sathyanarayana Concepts of Information Theory
industry to the integration of multiple complex components [7] Proximity-1 SPACE LINK PROTOCOLCODING AND
onto a single chip. As the complexity of the remotely located SYNCHRONIZATION SUBLAYER Recommended
physical devices increases, the requirement for a greater standard, Blue book, CCSDS 211.2-B1, April 2003.
telecommanding capability and efficiency arises, but present [8] Telecommand Part 1.Channel Service. Recommendation
IP Core Based Architecture of telecommand System-on-a- for Space Data System Standards, CCSDS 201.0-B-3.Blue
Chip (SoC) has increased delay in transmission of data Book. Issue 3. Washington, D.C.: CCSDS, June2000.
packets. The increase in demand for better throughput and [9] Packet Telemetry. Recommendation for Space Data
increase features has lead to the motivation of this project. System Standards, CCSDS 102.0B-5.Blue Book. Issue 5.
Washington, D.C.: CCSDS, November 2000.
IV. SOLUTION
[10] Telecommand Part 2.1.Command Operation Procedures.
In this proposed design, plan to achieve by
Recommendation for Space Data System Standards, CCSDS
embedding pre-designed functions into a single SoC, which
202.1-B-2.Blue Book. Issue 2. Washington, D.C.: CCSDS,
utilizes specialized reusable core (IP cores) architecture into
June 2001.
complex chip. The conventional telecommand system is
[11] Rajesvari., Manoj G, Angelin Ponrani.M )IP Core Based
designed with Telecommand Processor and they are integrated
Architecture of Telecommand System-on-Chip (SoC) for
onto a chip .In this project, which reduces the utilization of
Spacecraft applications International Conference on Signal
slices and hence time delay is reduced.
Processing, Image Processing and Pattern Recognition- 2013
Since IP cores are pre-designed and pre-verified, the
[12] SoC: A Real Platform for IP Reuse, IP Infringement, and
designer can concentrate on the complete system without
IP Protection Debasri Saha and Susmita Sur-Kolay Advanced
having to worry about the correctness or performance of the
Computing and Microelectronics Unit, Indian Statistical
individual components.
Institute, Kolkata 700108, India, Received 12 October 2010;
REFERENCES
Revised 4 January 2011; Accepted 24 January 2011
[1] "TC SPACE DATA LINK PROTOCOL Recommended
[13] Reduced Precision Redundancy for Satellite
standard, Blue book issue 1, CCSDS 231.0-B1, SEP 2003.
Telecommand Receiver Module on FPGA Salman Sadruddin
[2] "TC SPACE DATA LINK PROTOCOL Recommended
and Arshad Aziz,National University of Science and
standard, Blue book issue 2, CCSDS 231.0-B2, Sep 2010.
Technology (NUST), H-12, Islamabad, Pakistan, Hindawi
[3] Detailed Design Review Document of TTCB/B System of
Publishing Corporation ,Chinese Journal of
INSAT-4B ISRO, Aug 2005.
Engineering,Volume 2013, Article ID 453872, 8 pages.
[4] Baseline Design Review Document of TTCB/B System
[14] The International Journal Of Engineering And Science
of INSAT-4B ISRO, Mar 2011.
(IJES) || Volume || 3 || Issue || 6 || Pages || 17-24 || 2014 || ISSN
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IDL - International Digital Library Of
Technology & Research
Volume 1, Issue 3, Mar 2017 Available at: www.dbpublications.org