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AREA DELAY POWER EFFICIENT CARRY SELECT ADDER 2014

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February2,2017
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AreaDelayPowerEfficientCarrySelectAdder2014 Phone

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In this brief, the logic operations involved in conventional carry select adder
(CSLA) and binary to excess1 converter (BEC)based CSLA are analyzed to
studythedatadependenceandtoidentifyredundantlogicoperations.Wehave Subject

eliminated all the redundant logic operations present in the conventional CSLA Re: Area Delay Power Efficient Carry Select Adder 2014
and proposed a new logic formulation for CSLA. In the proposed scheme, the
carryselect(CS)operationisscheduledbeforethecalculationoffinalsum,which Message

isdifferentfromtheconventionalapproach.Bitpatternsoftwoanticipatingcarry
words(correspondingtocin=0and1)andfixedcinbitsareusedforlogicoptimizationofCSandgenerationunits.AnefficientCSLA
designisobtainedusingoptimizedlogicunits.TheproposedCSLAdesigninvolvessignificantlylessareaanddelaythantherecently
proposed BECbased CSLA. Due to the small carryoutput delay, the proposed CSLA design is a good candidate for squareroot
(SQRT)CSLA.AtheoreticalestimateshowsthattheproposedSQRTCSLAinvolvesnearly35%lessareadelayproduct(ADP)than
the BECbased SQRTCSLA, which is best among the existing SQRTCSLA designs, on average, for different bitwidths. The
applicationspecifiedintegratedcircuit(ASIC)synthesisresultshowsthattheBECbasedSQRTCSLAdesigninvolves48%moreADP
andconsumes50%moreenergythantheproposedSQRTCSLA,onaverage,fordifferentbitwidths.

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