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DESIGN & ANALYSIS OF 16 BIT RISC PROCESSOR USING LOW POWER PIPELINING 2015

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Design&Analysisof16bitRISCProcessorUsinglowPowerPipelining2015 Phone

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A16bitlowpowerpipelinedRISCprocessorisproposedbyusinthispaper,the
RISC processor consists of the block mainly ALU, Universal shift register and
Barrel Shifter. We have used modified Harvard architecture that uses separate Subject

memories for its instruction & data memory response where as in the other Re: Design & Analysis of 16 bit RISC Processor Using low Power Pipelining 2015
architecture by von Neumann, has only one shared memory for instruction and
data,withonedatabusandaddressbuswithbetweendatamemory&processor Message

memory. The remedial architectural modification has been made in incremental

circuit utilized in carry select adder unit of the ALU in the RISC Processor. Operation in the core RISC Processor Fetch, Decode,
execute,writebackisimplementedinthe2stagepipeliningwiththepositiveedge&negativeEdge.Theprocesshasbeenrealized
usingXILINXISEDesignsuit13.2&theDynamicpowerisminimizedintheRISCCorethroughtheclockgatingtechniquethatisan
efficient power technique and the total power estimation is done by the X Power analyzer. All the implementation is done in XILINX
KINTEXXC7K16073fbg676initkit28nmtechnologyareused.Thesimulationillustratethetotalpowerdissipatedbytheprocessorto
be0.220watt,andtheLatencyis1.5cycle.

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