Powering digital circuits

with millivolt-level
alternating current sources

Anirban Chatterjee

T
he growth of elec-
tronics during the
last century has seen
remarkable achievements
in the fields of high-speed,
high-performance, robust,
and highly compact devices.
These developments have
had a profound impact in
the digital world of elec-
tronics, causing each de-
vice generation to be nearly
twice as fast as the previ-
ous version. Recently, the

BOLT PHOTO COURTESY OF STOCK.XCHNG/BRANDON BLINKENBERG.

growth curve of device

CIRCUIT PHOTO COURTESY OF STOCK.XCHNG/JAYANTA BEHERA.

speed started stagnating,
bringing another aspect of
device performance into
the limelightpower con-
sumption. The lower the
power consumed, the more
portable the device.
While most often engi-
neers look at ways to reduce
the power consumption
of the device themselves,
some venture into finding
alternate power sources. Al-
ternate power sources are
nonconventional, other than
battery or good old electricity sources. However, such sources and piezoelectric generators, there is a golden possibility of
can be harnessed only on a large scalewindmills, huge so- powering commonly used electronic devices by using only
lar panels, and hydroelectric plants. We need to design non- their ambient energyno batteries at all. The impact of such a
conventional energy sources at the micrometer level. This feat design on day-to-day life activities could be manifold. Consider
seems difficult to achieve. However, advances in VLSI design the lucrative idea of working on a smart phone that utilizes
have opened up a plethora of opportunities in the field of mi- power generated by a piezoelectric material attached to your
cro-fabrication. shoes (Fig. 1) or listening to a favorite composition on a por-
We now possess the required know-how to penetrate sev- table player that draws energy from ambient radio waves. The
eral layers of dimensions to create such power sources at the possibilities are amazing.
nanometer level. With the meager power generated using There is a serious hurdle on the path to our goal: These
sources such as radio-frequency identification transponders power sources generate ac power, whereas all digital de-
vices use dc power. Then, there arises a necessity to convert
Digital Object Identifier 10.1109/MPOT.2012.2195214 ac power into dc. A bit of know-how in the field of electri-
Date of publication: 27 July 2012 cal engineering suggests voltage rectification (such as using

38 0278-6648/12/$31.00 2012 IEEE IEEE POTENTIALS

a diode) as a possible solution to this
problem. However, using a rectifying di-
ode is not a feasible option. The voltage
drop across a diode is fairly high (our
signal is around 250 milli-volts). Using
an operational amplifier-based circuit is
not an option either. We do not have a
dc source to power the amplifier. The
rectification circuit should not only pow-
er itself but also provide power to the
digital device.
This article discusses the implementa-
tion of an ac-dc converter circuit that
achieves the desired feat by employing a
voltage clamping technique to gener-
ate dc power from an ac source,
rather than using standard rectification
techniques.
CMOS-based ac-dc converter
Complementary metaloxidesemi-
conductor (CMOS) technology has been
extensively used in the domain of digital
circuits. Extremely low static power con-
sumption and fabrication ease are two of
the vast array of benefits that they offer.
Figure 2 provides the schematic for the
proposed ac-dc conversion circuit, imple-
mented in CMOS technology.
A differential ac signal of magnitude
250 mV and frequency 20 kHz is applied
to the first CMOS pair (each pair shall be
called a stage). The applied voltage
being lesser than the threshold voltage of
the metal-oxide-semiconductor field-
effect transistors (MOSFETs) forces all the
transistors to operate in the subthreshold
region. At the end of every cycle, the sig-
nals deposit residual charge on the tran-
sistors causing a dc voltage offset to
appear in the output signal. The higher
the charge deposited, the higher the dc
offset. We know that a charge stored by
an electrical entity is directly proportional
to its capacitance. MOSFETs operating in
the subthreshold region offer very little
capacitance. Hence, the offset voltage pro-
duced by the first stage itself is quite
low (~50 mV). This exposes a serious
drawback in our design. This drawback
however, is outweighed by the remark-
ably low power consumption of the MOS-
FETs operating in the subthreshold region.
To increase the output voltage magnitude,
we employ succeeding stages (cascaded
stages in Fig. 2) that perform the job by a
process called charge pumping.
The next two stages introduce more dc
voltage in the output signal from the first
stage, resulting in an offset voltage of about
200 mV. This voltage magnitude should be
enough to power a digital device if we use
a 150 mV digital logic (that is, instead of
JULY/AUGUST 2012
Fig. 1 Piezoelectric harvesters attached
to shoes.
considering a 5 V as logic 1, use 150 mV as
logic 1). The higher the logic 1 voltage
used, the better is the noise immunity that
can be obtained in a circuit. In our circuit,
it is possible to achieve even higher dc
By controlling the aspect
ratios, we can easily design
an inverter that can switch
at the required voltage.
Cascading two such invert-
ers generates a compara-
tor circuit that can detect
whether an input voltage
is higher than a particular
threshold voltage.
voltages simply by cascading more stages.
However, more stages imply more power
consumed by the converter circuit itself
and consequently less power transferred to
the device.
We have to strike a tradeoff between
the dc voltage level we desire and the
converter circuit power consumption we
Cascaded Stages (for Charge Pumping) Comparator Cell (for Clock Extraction)
First Stage
Fig. 2 Different stages in the proposed ac-dc conversion circuit (implemented in
CMOS).
can afford. We were satisfied with two
cascaded stages and carried out simula-
tions, the results of which we briefly
present below.
Simulation results
The output signal is plotted in Fig.3.
The input ac signal is plotted in green
while the output is plotted in red on the
same axis.
The shift in dc level is clearly visible
in Fig. 3 and is numerically equal to the
difference in the peak voltage values
between the two plots. The peak power
consumed by the circuit is nearly 5 nW.
This extremely low power consumption
of the converter circuit ensures that it
will waste negligible power in its opera-
tion, offering the majority of the power
available to the digital device. The circuit
also provides excellent thermal and
noise stability.
Designing a comparator
One way to test the functionality of
the converter circuit is to operate a digital
circuit solely on the power generated by
our ac-dc converter circuit. One particu-
larly useful and probably the simplest
digital circuit is a comparator, a circuit
that can detect if an input voltage is
higher than a particular threshold value.
The key component of a comparator is a
simple CMOS inverter. Microelectronics
tells us that the switching threshold volt-
age of an inverter, or simply stated, the
switching voltage of an inverter, depends
on the aspect ratios of the n-moses and
p-moses. Hence, by controlling the
aspect ratios, we can easily design an
inverter that can switch at the required
voltage. Cascading two such inverters
generates a comparator circuit that can
detect whether an input voltage is higher
than a particular threshold voltage.
The last stage in Fig. 2 represents a
comparator circuit. Figure 4 shows the
39

Fig. 3 Output of the circuit. Note the difference between the output voltage (in red)
and the input (in green).
transfer characteristic of this comparator
when operated on the voltage generated
by the ac-dc converter circuit. The input
voltage has been swept across a range of
values and the output has been recorded.
The comparator output is displayed in
yellow. The aspect ratios of the transis-
tors have been adjusted to provide a
threshold voltage of 100 mV. Beyond
100 mV, the output of the comparator
saturates at supply voltage and below
100 mV, the output saturates at ground
voltageexactly complying with the
theoretical performance characteristic of
a comparator.
Fig. 4 Transfer charactersitic of the comparator running on power generated by our
circuit.
Fig. 5 Extracting a clock signal from an ac source with our circuit.
40
Once the signal voltage
exceeds the comparator
threshold voltage, the
comparator immediately
switches to high (logic 1),
causing a square wave-
form to be generated as
an output, which can be
used as a clock signal.
Extracting a clock signal
from an ac source
To achieve a method of converting an
ac signal source to a digital clock signal,
we pass the ac signal through the com-
parator circuit presented in the previous
section. The comparator can have only
positive threshold values. Hence, for the
entire negative cycle of the ac signal, the
signal generated by the comparator is low
and remains low as long as the signal
voltage level is lesser than the comparator
threshold voltage. Once the signal voltage
exceeds the comparator threshold volt-
age, the comparator immediately switches
to high (logic 1), causing a square wave-
form to be generated as an output, which
can be used as a clock signal.
This behavior, however, imposes a
serious restriction on the clock signals
that can be generated by the circuit: This
circuit can only generate those clock sig-
nals that have a duty cycle less than 50%.
We designed a clock extraction circuit
using a single inverter (instead of the pair
which resulted in a comparator). This
allowed us to extract a clock signal with
a duty cycle greater than 50%. Such a
signal extraction is possible since the
inverter output goes high when the ac
voltage level is negative and remains
high until the ac voltage magnitude
exceeds the threshold voltage of the
inverter, a behavior just opposite to the
one demonstrated by the design involv-
ing a comparator.
Figure 5 shows the output of the latter
design. The clock signal switches at
voltage levels around 50 mV, which is
precisely the switching threshold voltage
for which the inverter has been designed.
Conclusion
This article presented the design of
an ac-dc converter circuit. Instead of rec-
tifying the input signal, the circuit oper-
ates by introducing a dc component in
the input ac signal, providing a scope for
the extraction of the dc voltage. A com-
parator circuit using two CMOS inverters
in series was designed and made to
operate on the generated dc voltage.
The performance of the comparator cell
was found to be in total agreement with
the theoretical prediction.
A clock signal was then successfully
extracted from an input ac signal. With
the design of an inverter cell and a clock
signal, it is possible to implement other
complex forms of digital logic using these
fundamental blocks. However, this ac-dc
converter circuit suffers from voltage sta-
bility degradation at higher fan-outs
IEEE POTENTIALS
owing to higher current consumption.
Many such ac-dc converter circuits oper-
ating in parallel can be a workaround in
such cases.
There are other minor performance
flaws in this design as well. As can be
observed from Fig. 5, the clock edges
generated appear rather smoothed out
and not sharp. This occurs due to
nonidealities present in the voltage trans-
fer characteristics of the inverter cells
used in the comparator block. The mag-
nitude of this error can be reduced by
cascading two more inverters in series.
However, this adds to signal propagation
delay. Hence, a suitable tradeoff has to be
reached, which might vary with specifica-
tions provided in the design or restric-
tions imposed on the performance of the
digital device. The simulations have been
carried out in a Cadence Spectre Simula-
tor environment with Virtuoso schematic
editor. 500 nm MOS technology has been
used in the design and simulations have
been carried out at a 27 C temperature.
Acknowledgment
I would like to express my gratitude
to the Electrical and Electronics Engi-
neering Department of the Birla Insti-
tute of Technology and Science (BITS)
This ac-dc converter circuit
suffers from voltage stability
degradation at higher fan-
outs owing to higher current
consumption. Many such
ac-dc converter circuits
operating in parallel can be
a workaround in such cases.
Pilani for providing me with the op-
portunity to use the CAD resources and
electronic design automation tools avail-
able at Oyster Lab, BITS Pilani.
Read more about it
J. Rabaey, A. Chandrakasan, and
B. Nikolic, Digital Integrated Circuits
A Design Perspective, 2nd ed. Engle-
wood Cliffs, NJ: Prentice-Hall, January
2003, pp. 1530.
S. Mandal and R. Sarpeshkar,
Low power CMOS rectifier design for
RFID applications, IEEE Trans. Circuits
Syst., vol. 54, no. 6, pp. 11771188, June
2007.
T. Le, Efficient power conversion
interface circuits for energy harvesting
applications, Doctor of Philosophy
Thesis, Oregon State Univ., Feb. 2008.
T. Le, K. Mayaram, and T. Fiez,
Efficient far-field radio frequency
energy harvesting for passively powered
sensor networks, IEEE J. Solid State Cir-
cuits, vol. 43, no. 5, pp. 12871302, 2008.
R. Sarpeshkar, Ultra Low Power
Bioelectronics: Fundamentals, Biomedi-
cal Applications and Bio-inspired Sys-
tems. Cambridge, U.K.: Cambridge Univ.
Press, Feb. 2010, pp. 2550.
J. Kymisis, C. Kendall, J. Paradiso,
and N. Gershenfeld, Parasitic power
harvesting in shoes, in Proc. 2nd IEEE
Int. Conf. Wearable Computing (ISWC),
IEEE Computer Society Press, Oct. 1998,
pp. 132139.
About the author
Anirban Chatterjee (anirbanchatterjee.
bits@gmail.com) is a final-year unde-
graduate student pursuing a degree in
electrical and electronics engineering at
BITS Pilani, India. He holds an interest
in power scavenging techniques and the
automation of low power design and is
currently working with the OMAP team
of Texas Instruments.

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JULY/AUGUST 2012 41