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A B C D E

1 1

Compal Confidential
2 2

JDW50/JDY70 Schematics Document


Intel Merom Processor with Crestline(PM945/GM945) + DDRII + ICH7M
(With ATI MXM/B)

3 2007-4-12 3

REV: 0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 1 of 44
A B C D E
A B C D E

Compal Confidential
Intel Merom Processor Thermal Sensor Clock Generator
Fan Control
Model Name : JDW50/70 page 33
ADM1032
uPGA-478 Package page 4 page 14
File Name : LA-3771P
(Socket M) page 4,5
1 1
FSB
H_A#(3..35) 533/667MHz H_D#(0..63)
DVI-D Conn. LCD Conn. CRT & TV-out
page 16 page 16 page 17
Intel Memory BUS(DDRII)
LVDS 200pin DDRII-SO-DIMM X2
LVDS SDVO
945/PM/GM/943GML Dual Channel BANK 0, 1, 2, 3 page 12,13
DVI
1.8V DDRII 533/667
uFCBGA-1466
PCI-Express page 6,7,8,9,10,11

MXM II VGA/B
DMI C-Link USB conn x2 Bluetooth CMOS
page 15
page 26
Conn page 27
Camera page 16
USB port 0, 2 USB port 5 USB port 3
PCI-Express
2
Intel ICH7-M 3.3V 48MHz USB
2

3.3V 24.576MHz/48Mhz HD Audio


PCI BUS
3.3V 33 MHz 3.3V ATA-100 IDE
IDSEL:AD20 BGA-652
(PIRQA#,
S-ATA
New Card MINI Card x1 LAN(GbE) GNT#2, page 20,21,22,23
REQ#2)
Socket WLAN Boardcom CDROM MDC 1.5 HDA Codec
page 27 page 26 page 24 ALC268
Card Reader port 0, 1 Conn.
page 22
Conn
page 30 page 31
USB port 1 USB port 7
ENE MR510
page 23

RJ45 SATA HDD


page 25
Conn. page 22
4 in 1 Audio AMP
socket page 32
page 23 LPC BUS
3 3
Phone Jack x3
BTN/B Conn. LS3553P
ENE KB926 page 32
RTC CKT. page 28
page 29
page 30

Power On/Off CKT. LED/B Conn. LS3557P Touch Pad Int.KBD


page 29 page 29 page 29
page 30

USB Conn. EC I/O Buffer BIOS


DC/DC Interface CKT. LS3551P page 29 page 29
USB port 4, 6
page 34 page 26

Power Circuit DC/DC AUDIO/B Conn. LS3558P

4 w/Woofer(JDY70) 4

page 35 page 32

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 2 of 44
A B C D E
A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8V 1.8V power rail for DDR ON ON OFF Vcc 3.3V +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail for SB ON ON X 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V_LAN 3.3V power rail for LAN ON ON X 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS 3.3V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VALW 5V always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VS 5V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+VSB VSB always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
2 2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOARD ID Table BTO Option Table


External PCI Devices Board ID PCB Revision BTO Item BOM Structure
0 0.1 Discrete PM@
Device IDSEL# REQ#/GNT# Interrupts
Card Reader AD16 0 PIRQE
1 UMA GM@
2
3 DVI DVI@
4 SATA*1 SATA*1@
5 SATA*2 SATA*2@
6 Dbg Dbg@
7

EC SM Bus1 address EC SM Bus2 address


3 3
Device Address Device Address
Smart Battery 0001 011X b ADI ADM1032 1001 100X b
EEPROM(24C16/02) 1010 000X b
GMT G781-1 1001 101X b

ICH7M SM Bus address


Device Address

Clock Generator 1101 001Xb


(ICS9LPRS365)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 3 of 44
A B C D E
5 4 3 2 1

JP22A

H_A#3 J4 E22 H_D#0


H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2
H_D#[0..63]
H_D#[0..63] 6
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4
M1 A7# D4# F23
H_A#8 N2 G25 H_D#5
H_A#9 A8# D5# H_D#6 H_A#[3..31]
J1 A9# D6# E25 H_A#[3..31] 6
H_A#10 N3 E23 H_D#7
H_A#11 A10# D7# H_D#8 H_REQ#[0..4]
P5 A11# D8# K24 H_REQ#[0..4] 6
H_A#12 P2 G24 H_D#9
H_A#13 A12# D9# H_D#10 H_RS#[0..2]
L1 A13# D10# J24 H_RS#[0..2] 6
D H_A#14 P4 J23 H_D#11 D
H_A#15 A14# D11# H_D#12
P1 A15# D12# H26
H_A#16 R1 F26 H_D#13
H_A#17 A16# D13# H_D#14
Y2 A17# D14# K22
H_A#18 U5 H25 H_D#15
H_A#19 A18# D15# H_D#16
R3 A19# D16# N22
H_A#20 W6 K25 H_D#17
H_A#21 A20# D17# H_D#18
U4 A21# D18# P26
H_A#22 Y5 R23 H_D#19
H_A#23 A22# D19# H_D#20
U2 A23# D20# L25
H_A#24 R4 L22 H_D#21
H_A#25 A24# D21# H_D#22
T5 A25# ADDR GROUP DATA GROUP D22# L23
H_A#26 T3 M23 H_D#23
H_A#27 A26# D23# H_D#24
W3 A27# D24# P25
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28
Y1 A31# D28# R24
L26 H_D#29
H_REQ#0 D29# H_D#30
K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31 +1.05VS
H_REQ#2 REQ1# D31# H_D#32
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33
H_REQ#4 REQ3# D33# H_D#34
L5 REQ4# D34# V24
V26 H_D#35 XDP_TDI R59 2 1 56_0402_5%
D35# H_D#36
6 H_ADSTB#0 L2 ADSTB0# D36# W25
V4 U23 H_D#37
6 H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
D38# H_D#39 XDP_TDO R525 2 56_0402_5%
D39# U22 1
C AB25 H_D#40 C
D40# H_D#41
D41# W22
Y23 H_D#42
D42# H_D#43 XDP_TMS R63 56_0402_5%
14 CLK_CPU_BCLK A22 BCLK0 D43# AA26 2 1
A21 HOST CLK Y26 H_D#44
14 CLK_CPU_BCLK# BCLK1 D44#
Y22 H_D#45
D45# H_D#46
D46# AC26
AA24 H_D#47 H_PROCHOT# R114 2 1 75_0402_5%
D47# H_D#48
6 H_ADS# H1 ADS# D48# AC22
6 H_BNR# E2 AC23 H_D#49
BNR# D49# H_D#50
6 H_BPRI# G5 BPRI# D50# AB22
F1 AA21 H_D#51 XDP_BPM#5 R46 2 1 56_0402_5%
6 H_BR0# BR0# D51#
6 H_DEFER# H5 AB21 H_D#52
DEFER# D52# H_D#53
6 H_DRDY# F21 DRDY# D53# AC25
G6 AD20 H_D#54
6 H_HIT# HIT# D54#
E4 CONTROL AE22 H_D#55 H_IERR# R113 2 1 56_0402_5%
6 H_HITM# HITM# D55#
H_IERR# D20 AF23 H_D#56
IERR# D56# H_D#57
6 H_LOCK# H4 LOCK# D57# AD24
6 H_RESET# H_RESET# B1 AE21 H_D#58
RESET# D58# H_D#59
D59# AD21
AE25 H_D#60
H_RS#0 D60# H_D#61 XDP_TRST# R57 56_0402_5%
F3 RS0# D61# AF25 2 1
H_RS#1 F4 AF22 H_D#62
H_RS#2 RS1# D62# H_D#63 XDP_TCK R37 56_0402_5%
G3 RS2# D63# AF26 2 1
6 H_TRDY# G2 TRDY# TEST1 R526 2 1 @ 1K_0402_5%
DINV0# J26 H_DINV#0 6
M26 TEST2 R527 2 1 51_0402_5%
DINV1# H_DINV#1 6
AD4 BPM0# DINV2# V23 H_DINV#2 6
B B
AD3 BPM1# DINV3# AC20 H_DINV#3 6
AD1 BPM2#
AC4 BPM3#
DSTBN0# H23 H_DSTBN#0 6
20 XDP_DBRESET# XDP_DBRESET# C20 M24
DBR# DSTBN1# H_DSTBN#1 6
6 H_DBSY# E1 DBSY# DSTBN2# W24 H_DSTBN#2 6
19 H_DPSLP# B5 DPSLP# DSTBN3# AD23 H_DSTBN#3 6
19,42 H_DPRSTP# E5 DPRSTP# DSTBP0# G22 H_DSTBP#0 6
6 H_DPW R# D24 DPWR# DSTBP1# N25 H_DSTBP#1 6
AC2 MISC Y25 +3VS
PRDY# DSTBP2# H_DSTBP#2 6
XDP_BPM#5 AC1 AE24 C485
PREQ# DSTBP3# H_DSTBP#3 6
H_PROCHOT# D21 0.1U_0402_16V4Z
PROCHOT#
1 2
H_PW RGOOD D6
19 H_PW RGOOD PWRGOOD
H_CPUSLP# D7
6 H_CPUSLP# SLP#
XDP_TCK AC5
XDP_TDI TCK
AA6 TDI A20M# A6 H_A20M# 19
XDP_TDO AB3 A5 1 U21
TDO FERR# H_FERR# 19
TEST1 C26 C4 C484 1 8
TEST1 IGNNE# H_IGNNE# 19 VDD SCLK EC_SMB_CK2 28
TEST2 D25 B3
TEST2 INIT# H_INIT# 19
XDP_TMS AB5 C6 2200P_0402_50V7K THERMDA 2 7
TMS LINT0 H_INTR 19 2 D+ SDATA EC_SMB_DA2 28
XDP_TRST# AB6 B4
TRST# LINT1 H_NMI 19
LEGACY CPU THERMDC 3 6
D- ALERT#
THERMAL
THERMDA A24 D5 4 5
THERMDC THERMDA DIODE STPCLK# H_STPCLK# 19 THERM# GND
A25 THERMDC SMI# A3 H_SMI# 19
6,19 H_THERMTRIP# C7 THERMTRIP# ADM1032ARMZ_MSOP8
A A
FOX_PZ47903-2741-42_YONAH

Layout Note: Security Classification Compal Secret Data Compal Electronics, Inc.
THERMDA & THERMDC Trace / Space = 10 / 10 mil Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (1/2)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 4 of 44
5 4 3 2 1
5 4 3 2 1

+CPU_CORE
JP22C
100_0402_1% +CPU_CORE
+CPU_CORE 2 1 JP22B 3 x 330uF(9mOhm/3) AE18 K1
R20 VCC VSS
AE17 VCC VSS J2
42 VCCSENSE VCCSENSE AF7 AB26 1 1 1 AB15 M2
VSSSENSE AE7 VCCSENSE VSS VCC VSS
20mils 42 VSSSENSE VSSSENSE VSS AA25
+ C669 + C670 + C671
AA15 VCC VSS N1
2 1 R21 VSS AD25 @ AD15 VCC VSS T1
100_0402_1% AE26 AC15 R2
VSS 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 VCC VSS
+1.5VS B26 VCCA VSS AB23 AF15 VCC VSS V2
2 2 2
VSS AC24 AE15 VCC VSS W1
D 1 1 +1.05VS K6 VCCP VSS AF24 AB14 VCC VSS A26 D
C148 C153 J6 AE23 South Side Secondary AA13 D26
VCCP VSS VCC VSS
M6 VCCP VSS AA22 AD14 VCC VSS C25
10U_0805_10V4Z 0.01U_0402_16V7K N6 AD22 AC13 F25
2 2
T6
VCCP
VCCP
YONAH VSS
VSS AC21
+CPU_CORE
AF14
VCC
VCC
VSS
VSS B24
R6 VCCP VSS AF21 AE13 VCC VSS A23
K21 VCCP VSS AB19 3 x 330uF(9mOhm/3) AB12 VCC VSS D23
J21 AA19 AA12 E24
Layout Note: M21
VCCP
VCCP
VSS
VSS AD19 1 1 1 AD12
VCC
VCC
YONAH VSS
VSS B21
N21 AC19 AC12 C22
Place C626 near Pin B26 T21
VCCP VSS
AF19 + C672 + C673 + C674 AF12
VCC VSS
F22
VCCP VSS @ VCC VSS
R21 VCCP VSS AE19 AE12 VCC VSS E21
V21 AB16 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 AB10 B19
VCCP VSS 2 2 2 VCC VSS
W21 VCCP VSS AA16 AB9 VCC VSS A19
V6 AD16 AA10 D19

POWER, GROUNG, RESERVED SIGNALS AND NC


VCCP VSS VCC VSS
G21 VCCP VSS AC16 North Side Secondary AA9 VCC VSS C19
VSS AF16 AD10 VCC VSS F19
VSS AE16 AD9 VCC VSS E19
AE6 AB13 +CPU_CORE AC10 B16
+1.05VS 42 PSI# PSI# VSS VCC VSS
VSS AA14 AC9 VCC VSS A16
42 CPU_VID0 AD6 AD13 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AF10 D16
VID0 VSS VCC VSS
42 CPU_VID1 AF5 VID1 VSS AC14 1 1 1 1 1 1 1 1 AF9 VCC VSS C16
42 CPU_VID2 AE5 AF13 C675 C676 C677 C678 C679 C680 C681 C649 AE10 POWER, GROUND F16
VID2 VSS VCC VSS
2

42 CPU_VID3 AF4 VID3 VSS AE14 AE9 VCC VSS E16


R366 42 CPU_VID4 AE3 AB11 AB7 B13
VID4 VSS 2 2 2 2 2 2 2 2 VCC VSS
1K_0402_1% 42 CPU_VID5 AF2 VID5 VSS AA11 AA7 VCC VSS A14
42 CPU_VID6 AE2 AD11 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AD7 D13
VID6 VSS (Place these capacitors on South side,Secondary Layer) VCC VSS
AC11 AC7 C14
1

VSS VCC VSS


C
Trace Close CPU < 0.5' GTL_REF0 VSS AF11
+CPU_CORE
B20 VCC VSS F13
C
AD26 GTLREF VSS AE11 A20 VCC VSS E14
VSS AB8 F20 VCC VSS B11
14 CPU_BSEL0 B22 AA8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M E20 A11
BSEL0 VSS VCC VSS
2

14 CPU_BSEL1 B23 BSEL1 VSS AD8 1 1 1 1 1 1 B18 VCC VSS D11


R369 14 CPU_BSEL2 C21 AC8 C685 C682 C686 C683 C684 C687 B17 C11
BSEL2 VSS VCC VSS
2K_0402_1% VSS AF8 A18 VCC VSS F11
27.4_0402_1% 2 1 R376 COMP0 R26 AE8 A17 E11
54.9_0402_1% COMP0 VSS 2 2 2 2 2 2 VCC VSS
2 1 R375 COMP1 U26 AA5 D18 B8
1

27.4_0402_1% COMP1 VSS VCC VSS


2 1 R54 COMP2 U1 COMP2 VSS AD5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M D17 VCC VSS A8
54.9_0402_1% 2 1 R56 COMP3 V1 AC6 (Place these capacitors on South side,Secondary Layer) C18 D8
COMP3 VSS VCC VSS
VSS AF6 C17 VCC VSS C8
AB4 +CPU_CORE F18 F8
VSS VCC VSS
+CPU_CORE E7 VCC VSS AC3 F17 VCC VSS E8
AB20 AF3 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M E18 G26
VCC VSS VCC VSS
AA20 VCC VSS AE4 1 1 1 1 1 1 E17 VCC VSS K26
AF20 AB1 C688 C689 C690 C691 C692 C693 B15 J25
VCC VSS VCC VSS
AE20 VCC VSS AA2 A15 VCC VSS M25
AB18 VCC VSS AD2 D15 VCC VSS N26
2 2 2 2 2 2
AB17 VCC VSS AE1 C15 VCC VSS T26
AA18 B6 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M F15 R25
VCC VSS (Place these capacitors on North side,Secondary Layer) VCC VSS
AA17 VCC VSS C5 E15 VCC VSS V25
AD18 VCC VSS F5 B14 VCC VSS W26
AD17 E6 +CPU_CORE A13 H24
VCC VSS VCC VSS
AC18 VCC VSS H6 D14 VCC VSS G23
AC17 J5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C13 K23
VCC VSS VCC VSS
AF18 VCC VSS M5 1 1 1 1 1 1 1 1 F14 VCC VSS L24
AF17 L6 C694 C695 C696 C697 C698 C699 C700 C668 E13 P24
VCC VSS VCC VSS
VSS P6 B12 VCC VSS N23
VSS R5 A12 VCC VSS T23
B 2 2 2 2 2 2 2 2 B
D2 RSVD VSS V5 D12 VCC VSS U24
F6 U6 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C12 Y24
RSVD VSS (Place these capacitors on North side,Secondary Layer) VCC VSS
D3 RSVD VSS Y6 F12 VCC VSS W23
C1 RSVD VSS A4 E12 VCC VSS H21
AF1 RSVD VSS D4 B10 VCC VSS J22
D22 RSVD VSS E3 B9 VCC VSS M22
C23 RSVD VSS H3 +CPU-CORE C,uF ESR, mohm ESL,nH A10 VCC VSS L21
C24 G4 A9 P21
AA1
RSVD VSS
K4 Decoupling D10
VCC VSS
R22
RSVD VSS VCC VSS
AA4 RSVD VSS L3 SPCAP,Polymer 6X330uF 9m ohm/6 1.8nH/6 D9 VCC VSS V22
AB2 RSVD VSS P3 C10 VCC VSS U21
AA3 RSVD VSS N4 MLCC 0805 X5R 32X22uF 3m ohm/32 0.6nH/32 C9 VCC VSS Y21
M4 RSVD VSS T4 F10 VCC
N5 RSVD VSS U3 F9 VCC
T2 RSVD VSS Y3 E10 VCC
V3 RSVD VSS W4 E9 VCC
B2 RSVD VSS D1 B7 VCC
C3 C2 +1.05VS A7
RSVD VSS VCC
T22 RSVD VSS F2 F7 VCC
B25 G1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
RSVD VSS
1
1 1 1 1 1 1 1 1 FOX_PZ47903-2741-42_YONAH
C701 + C702 C703 C704 C705 C706 C707 C708 C709
FOX_PZ47903-2741-42_YONAH @ @
220U_D2_2VMR15
2 2 2 2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


A A

TRACE CLOSELY CPU < 0.5'


COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) Security Classification Compal Secret Data Compal Electronics, Inc.
COMP1, COMP3 layout : Space 25mils (55Ohms) Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (2/2)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 5 of 44
5 4 3 2 1
5 4 3 2 1

H_A#[3..31] 4
4 H_D#[0..63] U41A
H_D#0 F1 H9 H_A#3
HD0# HA3#
H_D#1 J1 HD1# HA4# C9 H_A#4 Description at page10
H_D#2 H1 E11 H_A#5 U41B
H_D#3 HD2# HA5# H_A#6
J6 HD3# HA6# G11
H_D#4 H3 F11 H_A#7 DMI_ITX_MRX_N0 AE35 K16 MCH_CLKSEL0
HD4# HA7# 20 DMI_ITX_MRX_N0 DMIRXN0 CFG0 MCH_CLKSEL0 14
H_D#5 K2 G12 H_A#8 DMI_ITX_MRX_N1 AF39 K18 MCH_CLKSEL1
HD5# HA8# 20 DMI_ITX_MRX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 14
H_D#6 G1 F9 H_A#9 DMI_ITX_MRX_N2 AG35 J18 MCH_CLKSEL2
HD6# HA9# 20 DMI_ITX_MRX_N2 DMIRXN2 CFG2 MCH_CLKSEL2 14
H_D#7 G2 H11 H_A#10 DMI_ITX_MRX_N3 AH39 F18 CFG3 PAD
HD7# HA10# 20 DMI_ITX_MRX_N3 DMIRXN3 CFG3 T17
H_D#8 K9 J12 H_A#11 E15 CFG4 PAD
HD8# HA11# CFG4 T22
H_D#9 K1 G14 H_A#12 F15 CFG5
HD9# HA12# CFG5 CFG5 10
D H_D#10 K7 D9 H_A#13 DMI_ITX_MRX_P0 AC35 E18 CFG6 PAD D
HD10# HA13# 20 DMI_ITX_MRX_P0 DMIRXP0 CFG6 T20
H_D#11 J8 J14 H_A#14 DMI_ITX_MRX_P1 AE39 D19 CFG7
HD11# HA14# 20 DMI_ITX_MRX_P1 DMIRXP1 CFG7 CFG7 10
H_D#12 H4 H13 H_A#15 DMI_ITX_MRX_P2 AF35 D16 CFG8 PAD
HD12# HA15# 20 DMI_ITX_MRX_P2 DMIRXP2 CFG8 T19

DMI
H_D#13 J3 J15 H_A#16 DMI_ITX_MRX_P3 AG39 G16 CFG9
HD13# HA16# 20 DMI_ITX_MRX_P3 DMIRXP3 CFG9 CFG9 10
H_D#14 K11 F14 H_A#17 E16 CFG10 PAD
HD14# HA17# CFG10 T18
H_D#15 G4 D12 H_A#18 D15 CFG11
HD15# HA18# CFG11 CFG11 10
H_D#16 T10 A11 H_A#19 DMI_MTX_IRX_N0 AE37 G15 CFG12
HD16# HA19# 20 DMI_MTX_IRX_N0 DMITXN0 CFG12 CFG12 10
H_D#17 W11 C11 H_A#20 DMI_MTX_IRX_N1 AF41 K15 CFG13
HD17# HA20# 20 DMI_MTX_IRX_N1 DMITXN1 CFG13 CFG13 10
H_D#18 H_A#21 DMI_MTX_IRX_N2 CFG14

CFG
T3 HD18# HA21# A12 20 DMI_MTX_IRX_N2 AG37 DMITXN2 CFG14 C15 PAD T15
H_D#19 U7 A13 H_A#22 DMI_MTX_IRX_N3 AH41 H16 CFG15 PAD
HD19# HA22# 20 DMI_MTX_IRX_N3 DMITXN3 CFG15 T21
H_D#20 U9 E13 H_A#23 G18 CFG16
HD20# HA23# CFG16 CFG16 10
H_D#21 U11 G13 H_A#24 H15 CFG17 PAD
HD21# HA24# CFG17 T16
H_D#22 T11 F12 H_A#25 DMI_MTX_IRX_P0 AC37 J25 CFG18
HD22# HA25# 20 DMI_MTX_IRX_P0 DMITXP0 CFG18 CFG18 10
H_D#23 W9 B12 H_A#26 DMI_MTX_IRX_P1 AE41 K27 CFG19
HD23# HA26# 20 DMI_MTX_IRX_P1 DMITXP1 CFG19 CFG19 10
H_D#24 T1 B14 H_A#27 DMI_MTX_IRX_P2 AF37 J26 CFG20
HD24# HA27# 20 DMI_MTX_IRX_P2 DMITXP2 CFG20 CFG20 10
H_D#25 T8 C12 H_A#28 DMI_MTX_IRX_P3 AG41
HD25# HA28# 20 DMI_MTX_IRX_P3 DMITXP3
H_D#26 T4 A14 H_A#29
H_D#27 HD26# HA29# H_A#30 CLK_MCH_3GPLL
W7 HD27# HA30# C14 G_CLKP AG33 CLK_MCH_3GPLL 14
H_D#28 U5 D14 H_A#31 AY35 AF33 CLK_MCH_3GPLL#
HD28# HA31# 12 DDRA_CLK0 SM_CK0 G_CLKN CLK_MCH_3GPLL# 14
H_D#29 T9 AR1
HD29# 12 DDRA_CLK1 SM_CK1
H_D#30 W6 AW7 A27 CLK_DREF_96M#

CLK
HD30# 13 DDRB_CLK0 SM_CK2 D_REF_CLKN CLK_DREF_96M# 14
H_D#31 T5 AW40 A26 CLK_DREF_96M

HOST
HD31# H_REQ#[0..4] 4 13 DDRB_CLK1 SM_CK3 D_REF_CLKP CLK_DREF_96M 14
H_D#32 AB7 D8 H_REQ#0
H_D#33 HD32# HREQ#0 H_REQ#1 CLK_DREF_SSC#
AA9 HD33# HREQ#1 G8 12 DDRA_CLK0# AW35 SM_CK0# D_REF_SSCLKN C40 CLK_DREF_SSC# 14
H_D#34 W4 B8 H_REQ#2 AT1 D41 CLK_DREF_SSC
HD34# HREQ#2 12 DDRA_CLK1# SM_CK1# D_REF_SSCLKP CLK_DREF_SSC 14
H_D#35 W3 F8 H_REQ#3 AY7
HD35# HREQ#3 13 DDRB_CLK0# SM_CK2#
H_D#36 Y3 A8 H_REQ#4 AY40 H32 MCH_CLKREQ#
HD36# HREQ#4 13 DDRB_CLK1# SM_CK3# CLK_REQ# MCH_CLKREQ# 14
H_D#37 Y7
H_D#38 HD37#
W5 HD38# 12 DDRA_CKE0 AU20 SM_CKE0

DDR MUXING
C H_D#39 Y10 B9 H_ADSTB#0 AT20 C
HD39# HADSTB#0 H_ADSTB#0 4 12 DDRA_CKE1 SM_CKE1
H_D#40 AB8 C13 H_ADSTB#1 BA29 A3
HD40# HADSTB#1 H_ADSTB#1 4 13 DDRB_CKE0 SM_CKE2 NC0
H_D#41 W2 AY29 A39
HD41# 13 DDRB_CKE1 SM_CKE3 NC1
H_D#42 AA4 AG1 CLK_MCH_BCLK# A4
HD42# HCLKN CLK_MCH_BCLK# 14 NC2
H_D#43 AA7 AG2 CLK_MCH_BCLK AW13 A40
HD43# HCLKP CLK_MCH_BCLK 14 12 DDRA_SCS#0 SM_CS0# NC3
H_D#44 AA2 AW12 AW1
HD44# 12 DDRA_SCS#1 SM_CS1# NC4
H_D#45 AA6 K4 H_DSTBN#0 AY21 AW41
HD45# HDSTBN#0 H_DSTBN#0 4 13 DDRB_SCS#0 SM_CS2# NC5
H_D#46 AA10 T7 H_DSTBN#1 AW21 AY1
HD46# HDSTBN#1 H_DSTBN#1 4 13 DDRB_SCS#1 SM_CS3# NC6
H_D#47 Y8 Y5 H_DSTBN#2 BA1

NC
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 H_DSTBN#2 4 NC7
AA1 HD48# HDSTBN#3 AC4 H_DSTBN#3 4 T37 PAD AL20 SM_OCDCOMP0 NC8 BA2
H_D#49 AB4 K3 H_DSTBP#0 PAD AF10 BA3
HD49# HDSTBP#0 H_DSTBP#0 4 T38 SM_OCDCOMP1 NC9
H_D#50 AC9 T6 H_DSTBP#1 BA39
H_D#51 HD50# HDSTBP#1 H_DSTBP#2 H_DSTBP#1 4 NC10
AB11 HD51# HDSTBP#2 AA5 H_DSTBP#2 4 12 DDRA_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#52 AC11 AC5 H_DSTBP#3 BA12 BA41
HD52# HDSTBP#3 H_DSTBP#3 4 12 DDRA_ODT1 SM_ODT1 NC12
H_D#53 AB3 AY20 C1
+1.05VS H_D#54 HD53# +1.8V13 DDRB_ODT0 SM_ODT2 NC13
AC2 HD54# 13 DDRB_ODT1 AU21 SM_ODT3 NC14 AY41
H_D#55 AD1 J7 H_DINV#0 B2
H_D#56 HD55# HDINV#0 H_DINV#1 H_DINV#0 4 R426 180.6_0402_1% SMRCOMP NC15
AD9 HD56# HDINV#1 W8 H_DINV#1 4 2 AV9 SM_RCOMPN NC16 B41
H_D#57 AC1 U3 H_DINV#2 R425 1 2 SMRCOMP# AT9 C41
H_D#58 HD57# HDINV#2 H_DINV#3 H_DINV#2 4 80.6_0402_1% SM_RCOMPP NC17
AD7 HD58# HDINV#3 AB10 H_DINV#3 4 NC18 D1
2

H_D#59 AC6 AK1


54.9_0402_1%

54.9_0402_1%

H_D#60 HD59# SM_VREF SM_VREF0


AB5 HD60# AK41 SM_VREF1
R528

R529

H_D#61 AD10 B7 H_RESET# 4 T32


H_D#62 HD61# HCPURST# H_ADS# RESERVED1
AD4 HD62# HADS# E8 H_ADS# 4 RESERVED2 R32
H_D#63 AC8 E7 H_TRDY# 20 PM_BMBUSY# G28 F3
H_TRDY# 4
1

HD63# HTRDY# H_DPW R# PM_EXTTS#0 PM_BMBUSY# RESERVED3


HDPWR# J9 H_DPW R# 4 12,13 PM_EXTTS#0 F25 PM_EXTTS0# RESERVED4 F7

PM
H8 H_DRDY# PM_EXTTS#1 H26 AG11

RESERVED
HDRDY# H_DRDY# 4 PM_EXTTS1# RESERVED5
J13 C3 H_DEFER# 4,19 H_THERMTRIP# R5301 0_0402_5%
2 G6 AF11
HVREF0 HDEFER# H_DEFER# 4 PM_THERMTRIP# RESERVED6
H_VREF K13 D4 H_HITM# GMCH_PW ROK AH33 H7
B HVREF1 HHITM# H_HITM# 4 PWROK RESERVED7 B
H_XRCOMP E1 D3 H_HIT# MCH_RSTIN# AH34 J19
HXRCOMP HHIT# H_HIT# 4 RSTIN# RESERVED8
H_XSCOMP E2 B3 H_LOCK# A41
HXSCOMP HLOCK# H_LOCK# 4 RESERVED9
H_YRCOMP Y1 C7 H_BR0# 18 MCH_ICH_SYNC# K28 A34
HYRCOMP HBREQ0# H_BR0# 4 ICH_SYNC# RESERVED10
H_YSCOMP U1 C6 H_BNR# D28
HYSCOMP HBNR# H_BNR# 4 RESERVED11
H_SW NG0 E4 F6 H_BPRI# D27
HXSWING HBPRI# H_BPRI# 4 RESERVED12
H_SW NG1 W1 A7 H_DBSY# A35
HYSWING HDBSY# H_DBSY# 4 RESERVED13
E3 H_CPUSLP#
HCPUSLP# H_CPUSLP# 4
CALISTOGA_FCBGA1466~D
24.9_0402_1%

24.9_0402_1%
1

H_RS#[0..2] 4 PM@
R531

R532

B4 H_RS#0
HRS0# H_RS#1
HRS1# E6
D6 H_RS#2
HRS2# MCH_RSTIN#
18,20,22,24,28 PLT_RST#
2

R326 100_0402_5% reserve VGATE for GMCH_PWROK


CALISTOGA_FCBGA1466~D +1.8V
PM@ VGATE 1 2 GMCH_PW ROK
14,20,42 VGATE
R333 @ 0_0402_5%

2
+1.05VS +1.05VS SYS_PW ROK 1 2
20,30 SYS_PW ROK
R334 R332 0_0402_5%
+1.05VS 100_0402_1%
1

20/20mil
221_0603_1%

221_0603_1%

1
2

SM_VREF
100_0402_1%

R534

R535

2
R533

1
1 C354 R335
2

H_SW NG0 H_SW NG1 C894 100_0402_1% PM_EXTTS#0 +3VS


1

H_VREF @ 0.1U_0402_16V4Z R183 10K_0402_5%


0.1U_0402_16V4Z 2 PM_EXTTS#1
1 2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

20,42 PM_DPRSLPVR

1
A A
2

2 R536 0_0402_5% R196 @ 10K_0402_5%


100_0402_1%

100_0402_1%

1 1
0.1U_0402_16V4Z
1

200_0603_1%

1
R537

R538

C711

R539

C712
C710

2 2
1

2
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Layout Note: Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title


H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
H_SWNG1 trace width and spacing is 10/20. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 6 of 44
5 4 3 2 1
5 4 3 2 1

DDRB_SDQ[0..63]
13 DDRB_SDQ[0..63]
DDRA_SDQ[0..63]
12 DDRA_SDQ[0..63] DDRB_SMA[0..13]
13 DDRB_SMA[0..13]
DDRA_SMA[0..13]
12 DDRA_SMA[0..13]
D D

U41D U41E

AU12 AJ35 DDRA_SDQ0 AT24 AK39 DDRB_SDQ0


12 DDRA_SBS0# SA_BS0 SA_DQ0 13 DDRB_SBS0# SB_BS0 SB_DQ0
AV14 AJ34 DDRA_SDQ1 AV23 AJ37 DDRB_SDQ1
12 DDRA_SBS1# SA_BS1 SA_DQ1 13 DDRB_SBS1# SB_BS1 SB_DQ1
BA20 AM31 DDRA_SDQ2 AY28 AP39 DDRB_SDQ2
12 DDRA_SBS2# SA_BS2 SA_DQ2 13 DDRB_SBS2# SB_BS2 SB_DQ2
AM33 DDRA_SDQ3 AR41 DDRB_SDQ3
SA_DQ3 DDRA_SDQ4 SB_DQ3 DDRB_SDQ4
SA_DQ4 AJ36 SB_DQ4 AJ38
12 DDRA_SDM[0..7] AK35 DDRA_SDQ5 13 DDRB_SDM[0..7] AK38 DDRB_SDQ5
DDRA_SDM0 SA_DQ5 DDRA_SDQ6 DDRB_SDM0 SB_DQ5 DDRB_SDQ6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDRA_SDM1 AM35 AH31 DDRA_SDQ7 DDRB_SDM1 AR38 AP41 DDRB_SDQ7
DDRA_SDM2 SA_DM1 SA_DQ7 DDRA_SDQ8 DDRB_SDM2 SB_DM1 SB_DQ7 DDRB_SDQ8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDRA_SDM3 AN22 AP33 DDRA_SDQ9 DDRB_SDM3 BA31 AV41 DDRB_SDQ9
DDRA_SDM4 SA_DM3 SA_DQ9 DDRA_SDQ10 DDRB_SDM4 SB_DM3 SB_DQ9 DDRB_SDQ10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDRA_SDM5 AL9 AP31 DDRA_SDQ11 DDRB_SDM5 AH8 AV38 DDRB_SDQ11
DDRA_SDM6 SA_DM5 SA_DQ11 DDRA_SDQ12 DDRB_SDM6 SB_DM5 SB_DQ11 DDRB_SDQ12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDRA_SDM7 AH4 AM36 DDRA_SDQ13 DDRB_SDM7 AN4 AR40 DDRB_SDQ13
SA_DM7 SA_DQ13 DDRA_SDQ14 SB_DM7 SB_DQ13 DDRB_SDQ14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDRA_SDQ15 AY38 DDRB_SDQ15
SA_DQ15 DDRA_SDQ16 SB_DQ15 DDRB_SDQ16
SA_DQ16 AK26 SB_DQ16 BA38
AL27 DDRA_SDQ17 AV36 DDRB_SDQ17
DDRA_SDQS0 SA_DQ17 DDRA_SDQ18 DDRB_SDQS0 SB_DQ17 DDRB_SDQ18
12 DDRA_SDQS0 AK33 SA_DQS0 SA_DQ18 AM26 13 DDRB_SDQS0 AM39 SB_DQS0 SB_DQ18 AR36
C DDRA_SDQS1 AT33 AN24 DDRA_SDQ19 DDRB_SDQS1 AT39 AP36 DDRB_SDQ19 C
12 DDRA_SDQS1 DDRA_SDQS2 SA_DQS1 SA_DQ19 DDRA_SDQ20 13 DDRB_SDQS1 DDRB_SDQS2 SB_DQS1 SB_DQ19 DDRB_SDQ20
12 DDRA_SDQS2 AN28 SA_DQS2 SA_DQ20 AK28 13 DDRB_SDQS2 AU35 SB_DQS2 SB_DQ20 BA36
DDR SYS MEMORY A

DDR SYS MEMORY B


DDRA_SDQS3 AM22 AL28 DDRA_SDQ21 DDRB_SDQS3 AR29 AU36 DDRB_SDQ21
12 DDRA_SDQS3 DDRA_SDQS4 SA_DQS3 SA_DQ21 DDRA_SDQ22 13 DDRB_SDQS3 DDRB_SDQS4 SB_DQS3 SB_DQ21 DDRB_SDQ22
12 DDRA_SDQS4 AN12 SA_DQS4 SA_DQ22 AM24 13 DDRB_SDQS4 AR16 SB_DQS4 SB_DQ22 AP35
DDRA_SDQS5 AN8 AP26 DDRA_SDQ23 DDRB_SDQS5 AR10 AP34 DDRB_SDQ23
12 DDRA_SDQS5 DDRA_SDQS6 SA_DQS5 SA_DQ23 DDRA_SDQ24 13 DDRB_SDQS5 DDRB_SDQS6 SB_DQS5 SB_DQ23 DDRB_SDQ24
12 DDRA_SDQS6 AP3 SA_DQS6 SA_DQ24 AP23 13 DDRB_SDQS6 AR7 SB_DQS6 SB_DQ24 AY33
DDRA_SDQS7 AG5 AL22 DDRA_SDQ25 DDRB_SDQS7 AN5 BA33 DDRB_SDQ25
12 DDRA_SDQS7 SA_DQS7 SA_DQ25 DDRA_SDQ26 13 DDRB_SDQS7 SB_DQS7 SB_DQ25 DDRB_SDQ26
SA_DQ26 AP21 SB_DQ26 AT31
AN20 DDRA_SDQ27 AU29 DDRB_SDQ27
DDRA_SDQS0# SA_DQ27 DDRA_SDQ28 DDRB_SDQS0# SB_DQ27 DDRB_SDQ28
12 DDRA_SDQS0# AK32 SA_DQS0# SA_DQ28 AL23 13 DDRB_SDQS0# AM40 SB_DQS0# SB_DQ28 AU31
DDRA_SDQS1# AU33 AP24 DDRA_SDQ29 DDRB_SDQS1# AU39 AW31 DDRB_SDQ29
12 DDRA_SDQS1# DDRA_SDQS2# SA_DQS1# SA_DQ29 DDRA_SDQ30 13 DDRB_SDQS1# DDRB_SDQS2# SB_DQS1# SB_DQ29 DDRB_SDQ30
12 DDRA_SDQS2# AN27 SA_DQS2# SA_DQ30 AP20 13 DDRB_SDQS2# AT35 SB_DQS2# SB_DQ30 AV29
DDRA_SDQS3# AM21 AT21 DDRA_SDQ31 DDRB_SDQS3# AP29 AW29 DDRB_SDQ31
12 DDRA_SDQS3# DDRA_SDQS4# SA_DQS3# SA_DQ31 DDRA_SDQ32 13 DDRB_SDQS3# DDRB_SDQS4# SB_DQS3# SB_DQ31 DDRB_SDQ32
12 DDRA_SDQS4# AM12 SA_DQS4# SA_DQ32 AR12 13 DDRB_SDQS4# AP16 SB_DQS4# SB_DQ32 AM19
DDRA_SDQS5# AL8 AR14 DDRA_SDQ33 DDRB_SDQS5# AT10 AL19 DDRB_SDQ33
12 DDRA_SDQS5# DDRA_SDQS6# SA_DQS5# SA_DQ33 DDRA_SDQ34 13 DDRB_SDQS5# DDRB_SDQS6# SB_DQS5# SB_DQ33 DDRB_SDQ34
12 DDRA_SDQS6# AN3 SA_DQS6# SA_DQ34 AP13 13 DDRB_SDQS6# AT7 SB_DQS6# SB_DQ34 AP14
DDRA_SDQS7# AH5 AP12 DDRA_SDQ35 DDRB_SDQS7# AP5 AN14 DDRB_SDQ35
12 DDRA_SDQS7# SA_DQS7# SA_DQ35 DDRA_SDQ36 13 DDRB_SDQS7# SB_DQS7# SB_DQ35 DDRB_SDQ36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDRA_SDQ37 AM16 DDRB_SDQ37
SA_DQ37 DDRA_SDQ38 SB_DQ37 DDRB_SDQ38
SA_DQ38 AL14 SB_DQ38 AP15
DDRA_SMA0 AY16 AL12 DDRA_SDQ39 DDRB_SMA0 AY23 AL15 DDRB_SDQ39
DDRA_SMA1 SA_MA0 SA_DQ39 DDRA_SDQ40 DDRB_SMA1 SB_MA0 SB_DQ39 DDRB_SDQ40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDRA_SMA2 AW16 AN7 DDRA_SDQ41 DDRB_SMA2 AY24 AH10 DDRB_SDQ41
DDRA_SMA3 SA_MA2 SA_DQ41 DDRA_SDQ42 DDRB_SMA3 SB_MA2 SB_DQ41 DDRB_SDQ42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDRA_SMA4 BA17 AK7 DDRA_SDQ43 DDRB_SMA4 AT27 AN10 DDRB_SDQ43
DDRA_SMA5 SA_MA4 SA_DQ43 DDRA_SDQ44 DDRB_SMA5 SB_MA4 SB_DQ43 DDRB_SDQ44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDRA_SMA6 AV17 AN9 DDRA_SDQ45 DDRB_SMA6 AU27 AH11 DDRB_SDQ45
DDRA_SMA7 SA_MA6 SA_DQ45 DDRA_SDQ46 DDRB_SMA7 SB_MA6 SB_DQ45 DDRB_SDQ46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDRA_SMA8 AW17 AL5 DDRA_SDQ47 DDRB_SMA8 AV27 AJ8 DDRB_SDQ47
B DDRA_SMA9 SA_MA8 SA_DQ47 DDRA_SDQ48 DDRB_SMA9 SB_MA8 SB_DQ47 DDRB_SDQ48 B
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDRA_SMA10 AU13 AW2 DDRA_SDQ49 DDRB_SMA10 AV24 AW10 DDRB_SDQ49
DDRA_SMA11 SA_MA10 SA_DQ49 DDRA_SDQ50 DDRB_SMA11 SB_MA10 SB_DQ49 DDRB_SDQ50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDRA_SMA12 AV20 AN2 DDRA_SDQ51 DDRB_SMA12 AY27 AW4 DDRB_SDQ51
DDRA_SMA13 SA_MA12 SA_DQ51 DDRA_SDQ52 DDRB_SMA13 SB_MA12 SB_DQ51 DDRB_SDQ52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDRA_SDQ53 AY9 DDRB_SDQ53
SA_DQ53 DDRA_SDQ54 SB_DQ53 DDRB_SDQ54
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDRA_SDQ55 AY5 DDRB_SDQ55
SA_DQ55 DDRA_SDQ56 SB_DQ55 DDRB_SDQ56
12 DDRA_SCAS# AY13 SA_CAS# SA_DQ56 AG7 13 DDRB_SCAS# AR24 SB_CAS# SB_DQ56 AV4
AW14 AF9 DDRA_SDQ57 AU23 AR5 DDRB_SDQ57
12 DDRA_SRAS# SA_RAS# SA_DQ57 13 DDRB_SRAS# SB_RAS# SB_DQ57
AY14 AG4 DDRA_SDQ58 AR27 AK4 DDRB_SDQ58
12 DDRA_SW E# SA_WE# SA_DQ58 13 DDRB_SW E# SB_WE# SB_DQ58
PAD SA_RCVENIN# AK23 AF6 DDRA_SDQ59 PAD SB_RCVENIN# AK16 AK3 DDRB_SDQ59
T28 SA_RCVENIN# SA_DQ59 T29 SB_RCVENIN# SB_DQ59
PAD SA_RCVENOUT# AK24 AG9 DDRA_SDQ60 PAD SB_RCVENOUT# AK18 AT4 DDRB_SDQ60
T30 SA_RCVENOUT# SA_DQ60 T31 SB_RCVENOUT# SB_DQ60
AH6 DDRA_SDQ61 AK5 DDRB_SDQ61
SA_DQ61 DDRA_SDQ62 SB_DQ61 DDRB_SDQ62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDRA_SDQ63 AJ3 DDRB_SDQ63
SA_DQ63 SB_DQ63

CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D
PM@ PM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 7 of 44
5 4 3 2 1
5 4 3 2 1

U41C
H27 D40 PEG_COMP 1 2 +1.5VS_PCIE
SDVOCTRL_DATA EXP_COMPI R540 24.9_0402_1%
H28 SDVOCTRL_CLK EXP_COMPO D38 10mils
F34 PCIE_GTX_C_MRX_N0
GMCH_TXOUT0+ EXP_RXN0 PCIE_GTX_C_MRX_N1 PCIE_MTX_C_GRX_N[0..15]
16 GMCH_TXOUT0+ B37 LA_DATA0 EXP_RXN1 G38 PCIE_MTX_C_GRX_N[0..15] 15
GMCH_TXOUT1+ B34 H34 PCIE_GTX_C_MRX_N2
16 GMCH_TXOUT1+ LA_DATA1 EXP_RXN2 PCIE_MTX_C_GRX_P[0..15]
GMCH_TXOUT2+ A36 J38 PCIE_GTX_C_MRX_N3
16 GMCH_TXOUT2+ LA_DATA2 EXP_RXN3 PCIE_MTX_C_GRX_P[0..15] 15
L34 PCIE_GTX_C_MRX_N4
GMCH_TXOUT0- EXP_RXN4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N[0..15]
16 GMCH_TXOUT0- C37 LA_DATA#0 EXP_RXN5 M38 PCIE_GTX_C_MRX_N[0..15] 15
D GMCH_TXOUT1- B35 N34 PCIE_GTX_C_MRX_N6 D
16 GMCH_TXOUT1- LA_DATA#1 EXP_RXN6 PCIE_GTX_C_MRX_P[0..15]
GMCH_TXOUT2- A37 P38 PCIE_GTX_C_MRX_N7
16 GMCH_TXOUT2- LA_DATA#2 EXP_RXN7 PCIE_GTX_C_MRX_P[0..15] 15
R34 PCIE_GTX_C_MRX_N8
GMCH_TZOUT0+ EXP_RXN8 PCIE_GTX_C_MRX_N9
16 GMCH_TZOUT0+ F30 LB_DATA0 EXP_RXN9 T38
GMCH_TZOUT1+ D29 V34 PCIE_GTX_C_MRX_N10

LVDS
16 GMCH_TZOUT1+ LB_DATA1 EXP_RXN10
GMCH_TZOUT2+ F28 W38 PCIE_GTX_C_MRX_N11
16 GMCH_TZOUT2+ LB_DATA2 EXP_RXN11
Y34 PCIE_GTX_C_MRX_N12
GMCH_TZOUT0- EXP_RXN12 PCIE_GTX_C_MRX_N13
16 GMCH_TZOUT0- G30 LB_DATA#0 EXP_RXN13 AA38
GMCH_TZOUT1- D30 AB34 PCIE_GTX_C_MRX_N14
16 GMCH_TZOUT1- LB_DATA#1 EXP_RXN14
GMCH_TZOUT2- F29 AC38 PCIE_GTX_C_MRX_N15
16 GMCH_TZOUT2- LB_DATA#2 EXP_RXN15
GMCH_TXCLK+ A32 D34 PCIE_GTX_C_MRX_P0
16 GMCH_TXCLK+ LA_CLK EXP_RXP0
GMCH_TXCLK- A33 F38 PCIE_GTX_C_MRX_P1
16 GMCH_TXCLK- LA_CLK# EXP_RXP1
GMCH_TZCLK+ E26 G34 PCIE_GTX_C_MRX_P2
16 GMCH_TZCLK+ LB_CLK EXP_RXP2
GMCH_TZCLK- E27 H38 PCIE_GTX_C_MRX_P3
16 GMCH_TZCLK- LB_CLK# EXP_RXP3

PCI-EXPRESS GRAPHICS
J34 PCIE_GTX_C_MRX_P4
R541 GM@ 0_0402_5% EXP_RXP4
16 DPST_PW M 1@ R7372 D32 LBKLT_CTL EXP_RXP5 L38 PCIE_GTX_C_MRX_P5
15,28 ENBKL 1 2 LBKLT_EN 0_0402_5% LBKLT_EN J30 LBKLT_EN EXP_RXP6 M34 PCIE_GTX_C_MRX_P6
LCTLA_CLK H30 N38 PCIE_GTX_C_MRX_P7
LCTLB_DATA LCTLA_CLK EXP_RXP7 PCIE_GTX_C_MRX_P8
H29 LCTLB_DATA EXP_RXP8 P34
16 GMCH_LCD_CLK GMCH_LCD_CLK G26 R38 PCIE_GTX_C_MRX_P9
GMCH_LCD_DATA LDDC_CLK EXP_RXP9 PCIE_GTX_C_MRX_P10
16 GMCH_LCD_DATA G25 LDDC_DATA EXP_RXP10 T34
GMCH_ENVDD F32 V38 PCIE_GTX_C_MRX_P11
16 GMCH_ENVDD LVDD_EN EXP_RXP11
LIBG B38 W34 PCIE_GTX_C_MRX_P12
LIBG EXP_RXP12 PCIE_GTX_C_MRX_P13
C35 LVBG EXP_RXP13 Y38
C33 AA34 PCIE_GTX_C_MRX_P14
LVREFH EXP_RXP14 PCIE_GTX_C_MRX_P15
C32 LVREFL EXP_RXP15 AB38

F36 PCIE_MTX_GRX_N0 C179 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0


GMCH_TV_COMPS EXP_TXN0 PCIE_MTX_GRX_N1 C188 1
C
17 GMCH_TV_COMPS A16 TVDAC_A EXP_TXN1 G40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1 C
GMCH_TV_LUMA C18 H36 PCIE_MTX_GRX_N2 C195 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
17 GMCH_TV_LUMA TVDAC_B EXP_TXN2
GMCH_TV_CRMA A19 J40 PCIE_MTX_GRX_N3 C201 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
17 GMCH_TV_CRMA TVDAC_C EXP_TXN3

TV
L36 PCIE_MTX_GRX_N4 C212 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
EXP_TXN4
1 2 TV_IREF J20 TV_IREF EXP_TXN5 M40 PCIE_MTX_GRX_N5 C217 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
R542 4.99K_0402_1% N36 PCIE_MTX_GRX_N6 C229 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
EXP_TXN6 PCIE_MTX_GRX_N7 C240 1
B16 TV_IRTNA EXP_TXN7 P40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
B18 R36 PCIE_MTX_GRX_N8 C246 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
TV_IRTNB EXP_TXN8 PCIE_MTX_GRX_N9 C252 1
B19 TV_IRTNC EXP_TXN9 T40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
V36 PCIE_MTX_GRX_N10 C261 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
EXP_TXN10 PCIE_MTX_GRX_N11 C270 1
J29 TV_DCONSEL1 EXP_TXN11 W40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
K30 Y36 PCIE_MTX_GRX_N12 C277 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
TV_DCONSEL0 EXP_TXN12 PCIE_MTX_GRX_N13 C285 1
EXP_TXN13 AA40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
AB36 PCIE_MTX_GRX_N14 C296 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
EXP_TXN14 PCIE_MTX_GRX_N15 C304 1
EXP_TXN15 AC40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
GMCH_CRT_CLK C26
17 GMCH_CRT_CLK DDCCLK

CRT
GMCH_CRT_DATA C25 D36 PCIE_MTX_GRX_P0 C176 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
17 GMCH_CRT_DATA DDCDATA EXP_TXP0
F40 PCIE_MTX_GRX_P1 C180 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
EXP_TXP1 PCIE_MTX_GRX_P2 C189
17 GMCH_CRT_VSYNC H23 VSYNC EXP_TXP2 G36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
G23 H40 PCIE_MTX_GRX_P3 C198 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
17 GMCH_CRT_HSYNC HSYNC EXP_TXP3
E23 J36 PCIE_MTX_GRX_P4 C204 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
17 GMCH_CRT_B BLUE EXP_TXP4
2 1 D23 L40 PCIE_MTX_GRX_P5 C214 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
R543 150_0402_1% BLUE# EXP_TXP5 PCIE_MTX_GRX_P6 C219
17 GMCH_CRT_G C22 GREEN EXP_TXP6 M36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
2 1 B22 N40 PCIE_MTX_GRX_P7 C232 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
R544 150_0402_1% GREEN# EXP_TXP7 PCIE_MTX_GRX_P8 C241
17 GMCH_CRT_R A21 RED EXP_TXP8 P36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
2 1 B21 R40 PCIE_MTX_GRX_P9 C248 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
R545 150_0402_1% RED# EXP_TXP9 PCIE_MTX_GRX_P10 C253
EXP_TXP10 T36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
V40 PCIE_MTX_GRX_P11 C263 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
EXP_TXP11
1 2 CRT_IREF J22 CRT_IREF EXP_TXP12 W36 PCIE_MTX_GRX_P12 C272 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
B R546 255_0402_1% PCIE_MTX_GRX_P13 C283 1 B
EXP_TXP13 Y40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
10mils AA36 PCIE_MTX_GRX_P14 C288 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
EXP_TXP14 PCIE_MTX_GRX_P15 C297 1
EXP_TXP15 AB40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
+3VS

CALISTOGA_FCBGA1466~D
R547 1 2 10K_0402_5% GMCH_LCD_CLK PM@

R548 1 2 10K_0402_5% GMCH_LCD_DATA

R549 1 2 10K_0402_5% LCTLB_DATA

R550 1 2 10K_0402_5% LCTLA_CLK

R551 1 2 4.7K_0402_5% GMCH_CRT_CLK

R552 1 2 4.7K_0402_5% GMCH_CRT_DATA

R553 1 2 100K_0402_5% LBKLT_EN

R554 1 2 1.5K_0402_1% LIBG

R555 1 2 150_0402_1% GMCH_TV_COMPS

R556 1 2 150_0402_1% GMCH_TV_LUMA

A
R557 1 2 150_0402_1% GMCH_TV_CRMA A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 8 of 44
5 4 3 2 1
5 4 3 2 1

D +2.5VS D

U41H +1.5VS_DPLLA L56 +1.5VS_DPLLB L57


+1.05VS H22 1 2 MBK1608301YZF_0603 MBK1608301YZF_0603
VCC_SYNC C714 2 1 +1.5VS 2 1 +1.5VS
AC14 (60mA) 0.1U_0402_16V4Z
VTT0

0.1U_0402_16V4Z

0.1U_0402_16V4Z
(800mA) AB14 B30 +2.5VS
VTT1 VCCTX_LVDS0
W14 VTT2 VCCTX_LVDS1 C30 1 1
V14 A30 +1.5VS_PCIE R558
VTT3 VCCTX_LVDS2 1 1

C715

C717
T14 0_0805_5% + C716 + C718
R14
VTT4
VTT5 VCC3G0 AB41 W=60 mils 2 1 +1.5VS
P14 AJ41 330U_D2E_2.5VM 330U_D2E_2.5VM
VTT6 VCC3G1 2 2 2 2

10U_0805_10V4Z

10U_0805_10V4Z
N14 L41 (1500mA) 1
VTT7 VCC3G2
M14 N41 1 1
VTT8 VCC3G3 C719 +
L14 R41
VTT9 VCC3G4 +2.5VS

C720

C721
AD13 V41
VTT10 VCC3G5

0.1U_0402_16V4Z
AC13 Y41 220U_D2_2VMR15
VTT11 VCC3G6 2 2 2
AB13 1
VTT12
1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VS_3GPLL

C722
Y13 G41 +2.5VS
C713 + VTT14 VCCA_3GBG (2mA) +3VS_TVDACB L59 +3VS +3VS_TVDACA L60 +3VS
W13 H41
VTT15 VSSA_3GBG L58 2 MBK1608301YZF_0603 MBK1608301YZF_0603
V13
220U_D2_2VMR15 VTT16 MBK1608301YZF_0603
U13 VTT17 2 1 2 1
2

0.022U_0402_16V7K

0.022U_0402_16V7K
T13 E21 (70mA) +2.5VS_CRTDAC 2 1
VTT18 VCCA_CRTDAC0 +2.5VS

0.022U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R13 F21 1
VTT19 VCCA_CRTDAC1

0.1U_0402_16V4Z
N13 VTT20 VSSA_CRTDAC2 G21 1 close pin G41 1 1 1 1
+ C727
M13 1 1
VTT21

C724

C725

C726

C730
L13 + C729
VTT22

C723

C728
AB12 VTT23 VCCA_DPLLA B26 (50mA) +1.5VS_DPLLA 220U_D2_4VM
AA12 C39 (50mA) 220U_D2_4VM 2 2 2 2 2
VTT24 VCCA_DPLLB +1.5VS_DPLLB 2 2 2
Y12 AF1 (45mA) +1.5VS_HPLL
VTT25 VCCA_HPLL
C
W12
VTT26 CRTDAC: Route caps within C
V12 VTT27
U12 A38 (10mA) +2.5VS
250mil of Alviso. Route FB
VTT28 VCCA_LVDS
T12
VTT29 VSSA_LVDS
B39 within 3" of Calistoga
R12 VTT30
P12 VTT31
AF2 (45mA)
N12
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL +3VS_TVDACC L61 +3VS
+2.5VS
2.2U_0805_10V6K
4.7U_0805_10V4Z

L12 H20 +3VS_TVBG MBK1608301YZF_0603


VTT34 VCCA_TVBG
R11 VTT35 VSSA_TVBG G20 2 1

0.022U_0402_16V7K
1 1 P11 (120mA)
VTT36
C731

C732

0.01U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N11 VTT37
M11 E19 +3VS_TVDACA 1 1
VTT38 VCCA_TVDACA0
R10 VTT39 VCCA_TVDACA1 F19
2 2

C735

C736
P10 C20 +3VS_TVDACB 1 1
VTT40 VCCA_TVDACB0

C733

C734
N10 D20
VTT41 VCCA_TVDACB1 2 2
M10 E20 +3VS_TVDACC
VTT42 VCCA_TVDACC0
P9 F20
VTT43 VCCA_TVDACC1 2 2
N9
VTT44
M9
VTT45
R8 VTT46 VCCD_HMPLL0 AH1 (150mA) +1.5VS
P8 AH2
VTT47 VCCD_HMPLL1
N8
VTT48 close pin A38
M8
VTT49
P7 A28
VTT50 VCCD_LVDS0 (20mA)
N7 B28
VTT51 VCCD_LVDS1
M7 C28
R6
P6
VTT52
VTT53
VCCD_LVDS2
D21 (24mA)
+3VS_TVBG R559
0_0603_5%
+3VS PCI-E/MEM/PSB PLL decoupling
VTT54 VCCD_TVDAC +1.5VS_TVDAC
M6 H19 2 1
VTT55 VCCDQ_TVDAC

0.022U_0402_16V7K
MCH_A6 A6
VTT56 +1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
0.47U_0603_16V4Z

0.1U_0402_16V4Z
R5 A23 +3VS R561 R560
VTT57 VCCHV0 (40mA) 0_0603_5% 0_0603_5%
P5 B23 1 1
B VTT58 VCCHV1 B
10U_0805_10V4Z
0.1U_0402_16V4Z

1 N5 VTT59 VCCHV2 B25 2 1 2 1


C737

C739

C741

0.022U_0402_16V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
M5 VTT60 1 1
C740

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P4 AK31
VTT61 VCCAUX0 2 2
C738

N4 VTT62 VCCAUX1 AF31 1 1 1 1 1 1


2

C742

C744

C745

C747
M4 AE31
VTT63 VCCAUX2 2 2

C743

C746
R3 AC31
VTT64 VCCAUX3 @ @
P3 AL30
VTT65 VCCAUX4 2 2 2 2 2 2
N3 AK30
VTT66 VCCAUX5
M3 AJ30
VTT67 VCCAUX6 +1.5VS
0.22U_0603_16V7K

R2 VTT68 VCCAUX7 AH30


P2 VTT69 VCCAUX8 AG30
1 M2 AF30
VTT70 VCCAUX9
C748

MCH_D2
0.1U_0402_16V4Z

D2 VTT71 VCCAUX10 AE30


0.22U_0603_16V7K

AB1 AD30 1
VTT72 VCCAUX11
R1 AC30
MCH_AB1

2 VTT73 VCCAUX12
C749

1 P1 AG29
VTT74 VCCAUX13 +1.5VS_MPLL +1.5VS_HPLL
C750

N1 AF29 R562 R563


VTT75 VCCAUX14 2 0_0603_5% 0_0603_5%
M1 AE29
VTT76 VCCAUX15
0.47U_0603_16V4Z

2 VCCAUX16
AD29 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS
1 AC29
VCCAUX17

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AG28
VCCAUX18
C751

10U_0805_10V4Z

10U_0805_10V4Z
VCCAUX19 AF28
AE28 1 1 1 1
2 VCCAUX20

C752

C754
VCCAUX21 AH22

C753

C755
AJ21
VCCAUX22
AG14 AH21
VCCAUX32 VCCAUX23 2 2 2 2
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 AH20
VCCAUX34 VCCAUX25
Y14 AH19
VCCAUX35 VCCAUX26
AF13 P19
VCCAUX36 VCCAUX27
AE13 P16
+1.5VS VCCAUX37 VCCAUX28
AF12 VCCAUX38 VCCAUX29 AH15
A A
AE12 P15
VCCAUX39 VCCAUX30
AD12 VCCAUX40 VCCAUX31 AH14

CALISTOGA_FCBGA1466~D
PM@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/10/4 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 9 of 44
5 4 3 2 1
5 4 3 2 1

Strap Pin Table


CFG[3:17] have internal pull up
CFG[19:18] have internal pull down
+1.05VS U41F +1.5VS +1.05VS U41G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
(3500mA) AC27 AF27 W33 AT41 MCH_AT41 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 MCH_AM41
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27
VCC_NCTF3 VCCAUX_NCTF3
AF26 N33
VCC3 VCC_SM3
AU40 0 = DMI x 2

0.47U_0603_16V4Z

0.47U_0603_16V4Z
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 AF25 J33 AY34
VCC_NCTF5 VCCAUX_NCTF5 VCC5 VCC_SM5
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved

C758

C759
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU *(Default)
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_16V7K

0.22U_0603_16V7K

0.22U_0603_16V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34


2 2
0 = Lane Reversal Enable
AD26
VCC_NCTF10 VCCAUX_NCTF10
AG22 P32
VCC10 VCC_SM10
AR34 CFG9 1 = Normal Operation *(Default)
1 1 1 AC26 AF22 N32 BA30
VCC_NCTF11 VCCAUX_NCTF11 VCC11 VCC_SM11
C756

C760

C757

AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30


AA26
VCC_NCTF13 VCCAUX_NCTF13
AF21 L32
VCC13 VCC_SM13
AW30 CFG11 0 = Reserved
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30
2 2 2 W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 PSB 4X CLK Enable 1 = Calistoga *
V26 AG19 W31 AT30
VCC_NCTF16 VCCAUX_NCTF16 VCC16 VCC_SM16
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26
VCC_NCTF18 VCCAUX_NCTF18
R19 T31
VCC18 VCC_SM18
AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25
VCC_NCTF20 VCCAUX_NCTF20
AF18 P31
VCC20 VCC_SM20
AM30 10 = All Z Mode Enabled
AC25
VCC_NCTF21 VCCAUX_NCTF21
R18 N31
VCC21 VCC_SM21
AM29 11 = Normal Operation *(Default)
AB25 AG17 M31 AL29
VCC_NCTF22 VCCAUX_NCTF22 VCC22 VCC_SM22
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25
VCC_NCTF24 VCCAUX_NCTF24
AE17 Y30
VCC24 VCC_SM24
AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29
V25
VCC_NCTF26 VCCAUX_NCTF26
AB17 V30
VCC26 VCC_SM26
AJ28 0 = 1.05V *(Default)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U25
VCC_NCTF27 VCCAUX_NCTF27
AA17 U30
VCC27 VCC_SM27
AH28 CFG18 1 = 1.5V
1U_0603_10V4Z

T25 W17 T30 AJ27 1 1 1 1


P O W E R

VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28


10U_0805_10V4Z

10U_0805_10V4Z

R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)

C761

C762

C763

C764
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
AC24 R17 N30 AY26
VCC_NCTF31 VCCAUX_NCTF31 VCC31 VCC_SM31 2 2 2 2
C765

C766

C767

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24
VCC_NCTF33 VCCAUX_NCTF33
AF16 L30
VCC33 VCC_SM33
AV26 (Default)
Y24
VCC_NCTF34 VCCAUX_NCTF34
AE16 AA29
VCC34 VCC_SM34
AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
U24 AB16 V29 AJ26
VCC_NCTF37 VCCAUX_NCTF37 VCC37 VCC_SM37
C
T24
VCC_NCTF38 VCCAUX_NCTF38
AA16 U29
VCC38 VCC_SM38
AH26 0 = Only PCIE or SDVO is C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
AD23 W16 P29 AH25
VCC_NCTF40 VCCAUX_NCTF40 VCC40 VCC_SM40
V23
VCC_NCTF41 VCCAUX_NCTF41
V16 M29
VCC41 VCC_SM41
AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23
simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 R16 AA28 AJ23
VCC_NCTF44 VCCAUX_NCTF44 VCC44 VCC_SM44

0.47U_0603_16V4Z
1 AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22
V22 AF15 V28 AY22
C768 + VCC_NCTF46 VCCAUX_NCTF46 VCC46 VCC_SM46
U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 U28 VCC47 VCC_SM47 AW22 1

C769
T22 AD15 T28 AV22
220U_D2_2VMR15 VCC_NCTF48 VCCAUX_NCTF48 VCC48 VCC_SM48
R22 VCC_NCTF49 VCCAUX_NCTF49 AC15 R28 VCC49 VCC_SM49 AU22
2
AD21 AB15 P28 AT22
VCC_NCTF50 VCCAUX_NCTF50 VCC50 VCC_SM50 2 R564
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 6 CFG5 1 2 @ 2.2K_0402_5%
U21 Y15 M28 AP22
VCC_NCTF52 VCCAUX_NCTF52 VCC52 VCC_SM52 R565
T21 W15 L28 AK22 6 CFG7 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53
R21 V15 P27 AJ22
VCC_NCTF54 VCCAUX_NCTF54 VCC54 VCC_SM54 R566
AD20 U15 N27 AK21 6 CFG9 1 2 @ 2.2K_0402_5%
VCC_NCTF55 VCCAUX_NCTF55 VCC55 VCC_SM55
V20
VCC_NCTF56 VCCAUX_NCTF56
T15 M27
VCC56 VCC_SM56
AK20 Place near pin BA23
U20 R15 L27 BA19 R567 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 6 CFG11
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19
R20 N26 AW19 R568 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 6 CFG12

10U_0805_10V4Z

10U_0805_10V4Z
AD19 AE27 L26 AV19 1
VCC_NCTF60 VSS_NCTF0 VCC60 VCC_SM60 R569
1 V19 AE26 N25 AU19 1 1 6 CFG13 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 + C773
U19 AE25 M25 AT19
VCC_NCTF62 VSS_NCTF2 VCC62 VCC_SM62

C771

C772
C770 + T19 AE24 L25 AR19 R570 1 2 @ 2.2K_0402_5%
VCC_NCTF63 VSS_NCTF3 VCC63 VCC_SM63 6 CFG16
@ AD18 AE23 P24 AP19 330U_D2E_2.5VM_R9
220U_D2_2VMR15 VCC_NCTF64 VSS_NCTF4 VCC64 VCC_SM64 2 2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
2 AB18 AE21 M24 AJ19
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66
AA18 AE20 AB23 AJ18
VCC_NCTF67 VSS_NCTF7 VCC67 VCC_SM67
Y18 AE19 AA23 AJ17
VCC_NCTF68 VSS_NCTF8 VCC68 VCC_SM68
W18 AE18 Y23 AH17
VCC_NCTF69 VSS_NCTF9 VCC69 VCC_SM69
V18 AC17 P23 AJ16
B VCC_NCTF70 VSS_NCTF10 VCC70 VCC_SM70 +3VS B
U18 VCC_NCTF71 VSS_NCTF11 Y17 N23 VCC71 VCC_SM71 AH16
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
+1.05VS L23 AY15 R571 1 2 @ 1K_0402_5%
VCC73 VCC_SM73 6 CFG18

0.47U_0603_16V4Z
AC22 VCC74 VCC_SM74 AW15
M19 +1.8V AB22 AV15 R572 1 2 @ 1K_0402_5%
VCC100 VCC75 VCC_SM75 6 CFG19
L19 AR6 Y22 AU15 1
VCC101 VCC_SM100 VCC76 VCC_SM76

C774
N18 AP6 W22 AT15 R573 1 2 @ 1K_0402_5%
VCC102 VCC_SM101 VCC77 VCC_SM77 6 CFG20
M18 AN6 P22 AR15
VCC103 VCC_SM102 VCC78 VCC_SM78
L18 AL6 N22 AJ15
VCC104 VCC_SM103 VCC79 VCC_SM79 2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 AV1 MCH_AV1 AC21 AH13
VCC107 VCC_SM106 VCC82 VCC_SM82
N16 VCC108 VCC_SM107 AJ1 MCH_AJ1 AA21 VCC83 VCC_SM83 AK12
M16 W21 AJ12
VCC109 VCC84 VCC_SM84
0.47U_0603_16V4Z

0.47U_0603_16V4Z

L16 VCC110 N21 VCC85 VCC_SM85 AH12


M21
VCC86 VCC_SM86
AG12 Place near pin BA15
1 1 L21 AK11
VCC87 VCC_SM87
C775

C776

CALISTOGA_FCBGA1466~D AC20 BA8


VCC88 VCC_SM88
PM@ AB20 AY8
VCC89 VCC_SM89
Y20 AW8
2 2 VCC90 VCC_SM90
W20 AV8
VCC91 VCC_SM91
P20 VCC92 VCC_SM92 AT8
N20 AR8
VCC93 VCC_SM93
M20 VCC94 VCC_SM94 AP8
L20 BA6
VCC95 VCC_SM95
AB19 AY6
VCC96 VCC_SM96
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 AV6
VCC98 VCC_SM98
N19 AT6
VCC99 VCC_SM99

CALISTOGA_FCBGA1466~D
A A
PM@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/10/4 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 10 of 44
5 4 3 2 1
5 4 3 2 1

U41I U41J
AC41 AE34 AN21 AG10
VSS0 VSS100 VSS200 VSS280
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 C34 AB21 W10
VSS2 VSS102 VSS202 VSS282
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 AV33 P21 BA9
VSS4 VSS104 VSS204 VSS284
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 V33 AW20 Y9
VSS9 VSS109 VSS209 VSS289
AN40 T33 AR20 R9
VSS10 VSS110 VSS210 VSS290
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 M33 AA20 E9
VSS12 VSS112 VSS212 VSS291
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 F33 A20 AD8
VSS15 VSS115 VSS215 VSS295
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 B33 AC19 U8
VSS17 VSS117 VSS217 VSS297
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 AG32 K19 C8
VSS19 VSS119 VSS219 VSS299
AV39 AF32 G19 BA7
VSS20 VSS120 VSS220 VSS300
AR39 AE32 C19 AV7
VSS21 VSS121 VSS221 VSS301
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 AB32 P18 AL7
VSS23 VSS123 VSS223 VSS303
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 B32 D18 AH7
VSS25 VSS125 VSS225 VSS305
AA39 AY31 A18 AF7
VSS26 VSS126 VSS226 VSS306
Y39 AV31 AY17 AC7
VSS27 VSS127 VSS227 VSS307
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39
T39
VSS29
VSS30
VSS129
VSS130
AJ31
AG31
AP17
AM17
VSS229
VSS230
P O W E R VSS309
VSS310
G7
D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 Y31 AV16 AD6
VSS32 VSS132 VSS232 VSS312
N39 AB30 AN16 AB6
VSS33 VSS133 VSS233 VSS313
M39
L39
VSS34
VSS35
P O W E R VSS134
VSS135
E30
AT29
AL16
J16
VSS234
VSS235
VSS314
VSS315
Y6
U6
J39 AN29 F16 N6
VSS36 VSS136 VSS236 VSS316
H39 AB29 C16 K6
C VSS37 VSS137 VSS237 VSS317 C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 N29 AM15 B6
VSS39 VSS139 VSS239 VSS319
D39 K29 AK15 AV5
VSS40 VSS140 VSS240 VSS320
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 C29 L15 AY4
VSS43 VSS143 VSS243 VSS323
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 A29 A15 AP4
VSS45 VSS145 VSS245 VSS325
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 AW28 AT14 AJ4
VSS47 VSS147 VSS247 VSS327
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 AP28 AD14 U4
VSS49 VSS149 VSS249 VSS329
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 AD28 U14 J4
VSS51 VSS151 VSS251 VSS331
Y37 AC28 K14 F4
VSS52 VSS152 VSS252 VSS332
W37 W28 H14 C4
VSS53 VSS153 VSS253 VSS333
V37 J28 E14 AY3
VSS54 VSS154 VSS254 VSS334
T37 E28 AV13 AW3
VSS55 VSS155 VSS255 VSS335
R37 AP27 AR13 AV3
VSS56 VSS156 VSS256 VSS336
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 AK27 AM13 AH3
VSS58 VSS158 VSS258 VSS338
M37 J27 AL13 AG3
VSS59 VSS159 VSS259 VSS339
L37 G27 AG13 AF3
VSS60 VSS160 VSS260 VSS340
J37 F27 P13 AD3
VSS61 VSS161 VSS261 VSS341
H37 C27 F13 AC3
VSS62 VSS162 VSS262 VSS342
G37 B27 D13 AA3
VSS63 VSS163 VSS265 VSS343
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 M26 AY12 AT2
VSS65 VSS165 VSS263 VSS345
AY36 K26 AC12 AR2
VSS66 VSS166 VSS266 VSS346
AW36 F26 K12 AP2
VSS67 VSS167 VSS267 VSS347
AN36 D26 H12 AK2
VSS68 VSS168 VSS268 VSS348
AH36 AK25 E12 AJ2
B VSS69 VSS169 VSS269 VSS349 B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 H25 Y11 Y2
VSS72 VSS172 VSS272 VSS352
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 D25 D11 T2
VSS74 VSS174 VSS274 VSS354
B36 A25 B11 N2
VSS75 VSS175 VSS275 VSS355
BA35 BA24 AV10 J2
VSS76 VSS176 VSS276 VSS356
AV35 AU24 AP10 H2
VSS77 VSS177 VSS277 VSS357
AR35 AL24 AL10 F2
VSS78 VSS178 VSS278 VSS358
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 AN23
VSS81 VSS181 CALISTOGA_FCBGA1466~D
Y35 VSS82 VSS182 AM23
W35 AH23 PM@
VSS83 VSS183
V35 VSS84 VSS184 AC23
T35 W23
VSS85 VSS185
R35 K23
VSS86 VSS186
P35 J23
VSS87 VSS187
N35 F23
VSS88 VSS188
M35 C23
VSS89 VSS189
L35 AA22
VSS90 VSS190
J35 VSS91 VSS191 K22
H35 G22
VSS92 VSS192
G35 VSS93 VSS193 F22
F35 E22
VSS94 VSS194
D35 D22
VSS95 VSS195
AN34 VSS96 VSS196 A22
AK34 BA21
VSS97 VSS197
AG34 AV21
VSS98 VSS198
AF34 AR21
VSS99 VSS199
CALISTOGA_FCBGA1466~D
A A
PM@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/10/4 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 11 of 44
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V +1.8V

JP28

1
+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ6 R345
DDRA_SDQ4 VSS DQ4 DDRA_SDQ0 +DIMM_VREF
5 DQ0 DQ5 6
DDRA_SDQ1 7 8 1K_0402_1%
DQ1 VSS DDRA_SDM0
9 10

2
DDRA_SDQS0# VSS DM0 +DIMM_VREF
7 DDRA_SDQS0# DDRA_SDQS0
11 DQS0# VSS 12
DDRA_SDQ5
20mils
13 14
7 DDRA_SDQS0 DQS0 DQ6

1
15 16 DDRA_SDQ7 1 C376 1
DDRA_SDQ2 VSS DQ7 R344 C410
17 18
DDRA_SDQ3 DQ2 VSS DDRA_SDQ13
19 DQ3 DQ12 20
D DDRA_SDQ12 1K_0402_1% 2.2U_0805_10V6K 0.1U_0402_16V4Z D
21 VSS DQ13 22
DDRA_SDQ8 23 24 2 2

2
DDRA_SDQ14 DQ8 VSS DDRA_SDM1
25 DQ9 DM1 26
27 28
DDRA_SDQS1# VSS VSS
29 30 DDRA_CLK0 6
7 DDRA_SDQS1# DDRA_SDQS1 DQS1# CK0
7 DDRA_SDQS1 31 DQS1 CK0# 32 DDRA_CLK0# 6
33 34
DDRA_SDQ9 VSS VSS DDRA_SDQ11
35 DQ10 DQ14 36
DDRA_SDQ15 37 38 DDRA_SDQ10
DQ11 DQ15 DDRA_SMA[0..13]
39 40 7 DDRA_SMA[0..13]
VSS VSS
DDRA_SDQ[0..63]
7 DDRA_SDQ[0..63]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDM[0..7]
DQ16 DQ20 7 DDRA_SDM[0..7] +1.8V
DDRA_SDQ17 45 46 DDRA_SDQ21
DQ17 DQ21
47 48
DDRA_SDQS2# VSS VSS R1191 0_0402_5%
49 DQS2# NC 50 2 PM_EXTTS#0 6,13
7 DDRA_SDQS2# DDRA_SDQS2 DDRA_SDM2
51 52
7 DDRA_SDQS2 DQS2 DM2
53 VSS VSS 54 1 1 1 1 1 1 1
DDRA_SDQ18 55 56 DDRA_SDQ23 C611 C605 C608 C606 C389 C400 C388
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ22
57 58
DQ19 DQ23 2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z
59 60
DDRA_SDQ29 VSS VSS DDRA_SDQ28 2 2 2 2 2 2 2
61 DQ24 DQ28 62
DDRA_SDQ24 63 64 DDRA_SDQ25 2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z
DQ25 DQ29
65 66
DDRA_SDM3 VSS VSS DDRA_SDQS3#
67 DM3 DQS3# 68 DDRA_SDQS3# 7
69 70 DDRA_SDQS3
NC DQS3 DDRA_SDQS3 7
71 72
DDRA_SDQ26 VSS VSS DDRA_SDQ31 +1.8V
73 DQ26 DQ30 74
DDRA_SDQ27 75 76 DDRA_SDQ30 +0.9VS
DQ27 DQ31
77 78
DDRA_CKE0 VSS VSS DDRA_CKE1 DDRA_CKE0
6 DDRA_CKE0 79 80 DDRA_CKE1 6 1 4
C CKE0 NC/CKE1 DDRA_SBS2# C
81 VDD VDD 82 2 3 1 1 1 1
83 84 RP19 56_0404_4P2R_5% C411 C414 C417 C413
DDRA_SBS2# NC NC/A15
7 DDRA_SBS2# 85 86
BA2 NC/A14 DDRA_SMA12 0.1U_0402_16V4Z 0.1U_0402_16V4Z
87 VDD VDD 88 1 4
DDRA_SMA12 89 90 DDRA_SMA11 DDRA_SMA9 2 3 2 2 2 2
DDRA_SMA9 A12 A11 DDRA_SMA7 RP20 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
91 92
DDRA_SMA8 A9 A7 DDRA_SMA6
93 A8 A6 94
95 96 DDRA_SMA5 1 4
DDRA_SMA5 VDD VDD DDRA_SMA4 DDRA_SMA8
97 A5 A4 98 2 3
DDRA_SMA3 99 100 DDRA_SMA2 RP21 56_0404_4P2R_5%
DDRA_SMA1 A3 A2 DDRA_SMA0
101 A1 A0 102
103 104 DDRA_SMA1 1 4
DDRA_SMA10 VDD VDD DDRA_SBS1# DDRA_SMA3 +0.9VS
105 A10/AP BA1 106 DDRA_SBS1# 7 2 3
DDRA_SBS0# 107 108 DDRA_SRAS# RP22 56_0404_4P2R_5%
7 DDRA_SBS0# DDRA_SWE# BA0 RAS# DDRA_SCS#0 DDRA_SRAS# 7
7 DDRA_SWE# 109 110 DDRA_SCS#0 6
WE# S0# DDRA_SMA10
111 112 1 4
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_SBS0#
7 DDRA_SCAS# 113 114 DDRA_ODT0 6 2 3 1 1 1 1
DDRA_SCS#1 CAS# ODT0 DDRA_SMA13 RP23 56_0404_4P2R_5% C427 C404 C407 C425
6 DDRA_SCS#1 115 116 1
NC/S1# NC/A13 C403
117 118
DDRA_ODT1 VDD VDD DDRA_SWE# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
6 DDRA_ODT1 119 NC/ODT1 NC 120 1 4
121 122 DDRA_SCS#1 2 3 2 2 2 2 0.1U_0402_16V4Z
DDRA_SDQ37 VSS VSS DDRA_SDQ39 RP24 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
123 124
DDRA_SDQ36 DQ32 DQ36 DDRA_SDQ38
125 126
DQ33 DQ37 DDRA_SCAS#
127 128 1 4
DDRA_SDQS4# VSS VSS DDRA_SDM4 DDRA_ODT1
129 130 2 3
7 DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4 RP25 56_0404_4P2R_5% +0.9VS
131 132
7 DDRA_SDQS4 DQS4 VSS DDRA_SDQ34
133 VSS DQ38 134
DDRA_SDQ35 135 136 DDRA_SDQ33
DDRA_SDQ32 DQ34 DQ39
137 138
DQ35 VSS DDRA_SDQ45 DDRA_SMA11
139 140 1 4 1 1 1 1 1
DDRA_SDQ40 VSS DQ44 DDRA_SDQ43 DDRA_CKE1 C422 C405 C409 C408 C406
141 142 2 3
DDRA_SDQ44 DQ40 DQ45 RP26 56_0404_4P2R_5%
143 144
B DQ41 VSS DDRA_SDQS5# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
145 VSS DQS5# 146
DDRA_SDM5 DDRA_SDQS5 DDRA_SDQS5# 7 DDRA_SMA6 2 2 2 2 2
147 DM5 DQS5 148 DDRA_SDQS5 7 1 4
149 150 DDRA_SMA7 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ41 VSS VSS DDRA_SDQ47 RP27 56_0404_4P2R_5%
151 DQ42 DQ46 152
DDRA_SDQ46 153 154 DDRA_SDQ42
DQ43 DQ47 DDRA_SMA2
155 156 1 4
DDRA_SDQ49 VSS VSS DDRA_SDQ52 DDRA_SMA4 +0.9VS
157 158 2 3
DDRA_SDQ48 DQ48 DQ52 DDRA_SDQ53 RP28 56_0404_4P2R_5%
159 160
DQ49 DQ53
161 162
VSS VSS DDRA_SBS1#
163 NC,TEST CK1 164 DDRA_CLK1 6 1 4
165 166 DDRA_SMA0 2 3 1 1 1
VSS CK1# DDRA_CLK1# 6
DDRA_SDQS6# 167 168 RP29 56_0404_4P2R_5% C424 C423 C426
7 DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6
169 DQS6 DM6 170
7 DDRA_SDQS6 DDRA_SCS#0 0.1U_0402_16V4Z 0.1U_0402_16V4Z
171 172 1 4
DDRA_SDQ54 VSS VSS DDRA_SDQ51 DDRA_SRAS# 2 2 2
173 DQ50 DQ54 174 2 3
DDRA_SDQ50 175 176 DDRA_SDQ55 RP30 56_0404_4P2R_5% 0.1U_0402_16V4Z
DQ51 DQ55
177 178
DDRA_SDQ60 VSS VSS DDRA_SDQ57 DDRA_SMA13
179 180 1 4
DDRA_SDQ61 DQ56 DQ60 DDRA_SDQ56 DDRA_ODT0
181 182 2 3
DQ57 DQ61 RP31 56_0404_4P2R_5%
183 184
DDRA_SDM7 VSS VSS DDRA_SDQS7#
185 186
DM7 DQS7# DDRA_SDQS7 DDRA_SDQS7# 7
187 VSS DQS7 188 DDRA_SDQS7 7
DDRA_SDQ59 189 190
DDRA_SDQ58 DQ58 VSS DDRA_SDQ62
191 DQ59 DQ62 192
193 194 DDRA_SDQ63
D_CK_SDATA VSS DQ63
13,14 D_CK_SDATA 195 196
D_CK_SCLK SDA VSS R3531
13,14 D_CK_SCLK 197 SCL SAO 198 2 10K_0402_5%
+3VS 199 200 R3541 2 10K_0402_5%
VDDSPD SA1
203 204
GND GND
FOX_AS0A426-M2RN-7F
CONN@
A +3VS A

1 1
DIMM0 REV H:5.2mm (BOT)
C607 C402

0.1U_0402_16V4Z
2
2.2U_0805_10V6K 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 12 of 44
5 4 3 2 1
A B C D E

+DIMM_VREF +1.8V

+1.8V +1.8V
1 1
1 1 1 1 1 1
JP29 C373 C386 C519 + C556+ C420 C429 C385 C374
+DIMM_VREF 1 2
VREF VSS DDRB_SDQ5 2.2U_0805_10V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
3 VSS DQ4 4
DDRB_SDQ0 5 6 DDRB_SDQ4 2 2
0.1U_0402_16V4Z 2 2 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
DDRB_SDQ1 DQ0 DQ5
7 DQ1 VSS 8
9 10 DDRB_SDM0 330U_D2E_2.5VM_R9 150U_D2_6.3VM
DDRB_SDQS0# VSS DM0 @
11 DQS0# VSS 12
1 7 DDRB_SDQS0# DDRB_SDQS0 DDRB_SDQ6 1
7 DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
21
DQ3 DQ12
22 DDRB_SDQ13 For EMI
DDRB_SDQ8 VSS DQ13
23 DQ8 VSS 24
DDRB_SDQ9 25 26 DDRB_SDM1
DQ9 DM1 +1.8V +1.8V +1.8V +1.8V
27 VSS VSS 28
DDRB_SDQS1# 29 30
7 DDRB_SDQS1# DQS1# CK0 DDRB_CLK1 6
DDRB_SDQS1 31 32
7 DDRB_SDQS1 DQS1 CK0# DDRB_CLK1# 6
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14 DDRB_SMA[0..13] 1 1 1 1 1 1 1 1
DQ10 DQ14 7 DDRB_SMA[0..13]
DDRB_SDQ11 37 38 DDRB_SDQ15 C615 C616 C617 C618 C619 C620 C622 C621
DQ11 DQ15 DDRB_SDQ[0..63]
39 40
VSS VSS 7 DDRB_SDQ[0..63] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDM[0..7] 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
7 DDRB_SDM[0..7]
41 VSS VSS 42
DDRB_SDQ17 43 44 DDRB_SDQ21
DDRB_SDQ20 DQ16 DQ20 DDRB_SDQ16
45 DQ17 DQ21 46
47 48 0_0402_5%
DDRB_SDQS2# VSS VSS R356 1 +1.05VS +5VALW +1.5VS
49 50 2 PM_EXTTS#0 6,12
7 DDRB_SDQS2# DDRB_SDQS2 DQS2# NC DDRB_SDM2
51 52
7 DDRB_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 58
DQ19 DQ23
59 VSS VSS 60
DDRB_SDQ28 61 62 DDRB_SDQ26
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ24
63 64
DQ25 DQ29
65 VSS VSS 66
DDRB_SDM3 67 68 DDRB_SDQS3# +1.8V
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# 7 +0.9VS
69 70
NC DQS3 DDRB_SDQS3 7
71 72
2 DDRB_SDQ30 VSS VSS DDRB_SDQ29 2
73 DQ26 DQ30 74
DDRB_SDQ31 75 76 DDRB_SDQ27 DDRB_CKE0 1 4 1 1 1 1 1 1 1
DQ27 DQ31 DDRB_SBS2# C372 C369 C370 C371 C421 C419 C428
77 78 2 3
DDRB_CKE0 VSS VSS DDRB_CKE1 RP32 56_0404_4P2R_5%
6 DDRB_CKE0 79 CKE0 NC/CKE1 80 DDRB_CKE1 6
81 82 2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z
VDD VDD DDRB_SMA12 2 2
2.2U_0805_10V6K 2 2
2.2U_0805_10V6K 2 2
1U_0402_6.3V4Z 2
83 84 1 4
DDRB_SBS2# NC NC/A15 DDRB_SMA9
7 DDRB_SBS2# 85 BA2 NC/A14 86 2 3
87 88 RP33 56_0404_4P2R_5%
DDRB_SMA12 VDD VDD DDRB_SMA11
89 A12 A11 90
DDRB_SMA9 91 92 DDRB_SMA7 DDRB_SMA8 1 4
DDRB_SMA8 A9 A7 DDRB_SMA6 DDRB_SMA5 +1.8V
93 A8 A6 94 2 3
95 96 RP34 56_0404_4P2R_5%
DDRB_SMA5 VDD VDD DDRB_SMA4
97 A5 A4 98
DDRB_SMA3 99 100 DDRB_SMA2 DDRB_SMA3 1 4
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SMA1
101 102 2 3 1 1 1 1
A1 A0 RP35 56_0404_4P2R_5% C384 C398 C375 C399
103 104
DDRB_SMA10 VDD VDD DDRB_SBS1#
105 106 DDRB_SBS1# 7
DDRB_SBS0# A10/AP BA1 DDRB_SRAS# DDRB_SMA10 0.1U_0402_16V4Z 0.1U_0402_16V4Z
7 DDRB_SBS0# 107 108 DDRB_SRAS# 7 1 4
DDRB_SWE# BA0 RAS# DDRB_SCS#0 DDRB_SBS0# 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
7 DDRB_SWE# 109 110 DDRB_SCS#0 6 2 3
WE# S0# RP36 56_0404_4P2R_5%
111 VDD VDD 112
DDRB_SCAS# 113 114 DDRB_ODT0
7 DDRB_SCAS# CAS# ODT0 DDRB_ODT0 6
DDRB_SCS#1 115 116 DDRB_SMA13 DDRB_SWE# 1 4
6 DDRB_SCS#1 NC/S1# NC/A13 DDRB_SCAS#
117 118 2 3
DDRB_ODT1 VDD VDD RP37 56_0404_4P2R_5%
6 DDRB_ODT1 119 120
NC/ODT1 NC
121 122
DDRB_SDQ32 VSS VSS DDRB_SDQ36 DDRB_SCS#1
123 124 1 4
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37 DDRB_ODT1 +0.9VS
125 DQ33 DQ37 126 2 3
127 128 RP38 56_0404_4P2R_5%
DDRB_SDQS4# VSS VSS DDRB_SDM4
129 130
7 DDRB_SDQS4# DDRB_SDQS4 DQS4# DM4
131 132
7 DDRB_SDQS4 DQS4 VSS DDRB_SDQ39
133 134 1 1 1 1 1
DDRB_SDQ34 VSS DQ38 DDRB_SDQ38 DDRB_SMA11 C382 C391 C392 C378 C393
135 136 1 4
3 DDRB_SDQ35 DQ34 DQ39 DDRB_CKE1 3
137 DQ35 VSS 138 2 3
139 140 DDRB_SDQ44 RP39 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
141 142
DDRB_SDQ41 DQ40 DQ45 DDRB_SMA6
143 DQ41 VSS 144 1 4
145 146 DDRB_SDQS5# DDRB_SMA7 2 3
DDRB_SDM5 VSS DQS5# DDRB_SDQS5 DDRB_SDQS5# 7 RP40 56_0404_4P2R_5%
147 148
DM5 DQS5 DDRB_SDQS5 7
149 150
DDRB_SDQ42 VSS VSS DDRB_SDQ46 DDRB_SMA2 +0.9VS
151 152 1 4
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA4
153 154 2 3
DQ43 DQ47 RP41 56_0404_4P2R_5%
155 VSS VSS 156
DDRB_SDQ48 157 158 DDRB_SDQ52
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53 DDRB_SBS1#
159 160 1 4 1 1 1 1 1
DQ49 DQ53 DDRB_SMA0 C397 C396 C383 C379 C394
161 VSS VSS 162 2 3
163 164 RP42 56_0404_4P2R_5%
NC,TEST CK1 DDRB_CLK0 6
165 166 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQS6# VSS CK1# DDRB_CLK0# 6 DDRB_SCS#0 2 2 2 2 2
167 168 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
7 DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SRAS#
169 170 2 3
7 DDRB_SDQS6 DQS6 DM6 RP43 56_0404_4P2R_5%
171 172
DDRB_SDQ51 VSS VSS DDRB_SDQ54
173 174
DDRB_SDQ50 DQ50 DQ54 DDRB_SDQ55 DDRB_SMA13 +0.9VS
175 176 1 4
DQ51 DQ55 DDRB_ODT0
177 178 2 3
DDRB_SDQ56 VSS VSS DDRB_SDQ60 RP44 56_0404_4P2R_5%
179 DQ56 DQ60 180
DDRB_SDQ61 181 182 DDRB_SDQ57
DQ57 DQ61
183 VSS VSS 184 1 1 1
DDRB_SDM7 185 186 DDRB_SDQS7# C381 C395 C380
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# 7
187 188
DDRB_SDQ59 VSS DQS7 DDRB_SDQS7 7 0.1U_0402_16V4Z 0.1U_0402_16V4Z
189 DQ58 VSS 190
DDRB_SDQ58 191 192 DDRB_SDQ62 2 2
0.1U_0402_16V4Z 2
DQ59 DQ62 DDRB_SDQ63
193 194
D_CK_SDATA VSS DQ63
12,14 D_CK_SDATA 195 196
D_CK_SCLK SDA VSS
12,14 D_CK_SCLK 197 198 1 2
SCL SAO R3481
+3VS 199 VDDSPD SA1 200 2 10K_0402_5% +3VS
4 R349 10K_0402_5% 4
201 202
GND GND
FOX_AS0A426-MARG-7F
CONN@

DIMM1 REV H:9.2mm (BOT)


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 13 of 44
A B C D E
A B C D E F G H

R574
0_0805_5% 40mil
+CLK_VDD1
Clock Generator
FSLC FSLB FSLA CPU SRC PCI +CLK_VDD48 +CLK_VDDREF
+3VS 1 2
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz 1 1 1 1 1 1 1 1
C777 C778 C779
C780 C781 C782 C783 C784
0 0 1 133 100 33.3 10U_0805_10V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K 10U_0805_10V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
2 2 2 2 2 2 2 2

0 1 1 166 100 33.3


+CLK_VDD2 R576
Table : ICS9LPR325 20mil
+CLK_VCCA
U1 1 2 +CLK_VDD1 40mil 0_0805_5%
1
0 1 +CLK_VDD1 R575 1 2 1
1 1 +3VS
2.2_0603_5%
**SEL_PCI5/REF1 CLKREQ3# 33.3MHz PCICLK5 1 VDDSRC VDDA 7 C785 C786 1 1 1
49 10U_0805_10V4Z 0.047U_0402_16V7K C787 C788 C789
VDDSRC 2 2
**SEL_PCI6/PCICLK1 CLKREQ5# 33.3MHz PCICLK6 54
VDDSRC GNDA
8
65 0.047U_0402_16V7K 0.047U_0402_16V7K 10U_0805_10V4Z
+CLK_VDD2 VDDSRC 2 2 2
**SEL_24M/PCICLK2 TESTMODE 24MHz Output
25 PM_STP_PCI#
PCI_SRC_STOP# PM_STP_PCI# 20
**SEL_48M/PCICLK3 CLKREQ7# 48MHz_1 Output 30 VDDPCI
36 24 PM_STP_CPU#
VDDPCI CPU_STOP# PM_STP_CPU# 20
ITP_EN/PCICLK_F0 SRC pair CPU_ITP pair
+CLK_VDD1 12
VDDCPU CLK_CPU1 R577 1 CLK_MCH_BCLK
CPUCLKT1LP 11 2 0_0402_5% CLK_MCH_BCLK 6
**SEL_24M/PCICLK2=0=TESTMODE C790 1 2 +CLK_VDDREF 18
33P_0402_50V8J R578 1_0603_5% VDDREF CLK_CPU1# R579 1 CLK_MCH_BCLK#
**SEL_PCI6/PCICLK1=0=CLKREQ5# 15mil 10 2 0_0402_5% CLK_MCH_BCLK# 6
CPUCLKC1LP
1 2 1 2 +CLK_VDD48 40
R580 2.2_0603_5% VDD48
15mil

1
14 CLK_CPU0 R581 1 2 0_0402_5% CLK_CPU_BCLK
+3VS CPUCLKT0LP CLK_CPU_BCLK 4
Y1 CLK_XTALIN 20
C791 X1 CLK_CPU0# R582 1 CLK_CPU_BCLK#
**SEL_PCI5=1=PCICLK5 13 2 0_0402_5% CLK_CPU_BCLK# 4
33P_0402_50V8J 14.31818MHz_20P_1BX14318BE1A CPUCLKC0LP

2
1 2 CLK_REF 1 2 CLK_XTALOUT 19
R583 10K_0402_5% X2
CPUCLKT2_ITP/SRCCLKT10LP 6
CLK_48M_SD R693 1 2 12_0402_5%
23 CLK_48M_SD CLK_ICH_48M R694 1 CLKSEL0 CLK_MCH_BCLK
20 CLK_ICH_48M 2 12_0402_5% 41 5 1 2
CLK_PCI0 USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP R585 @ 49.9_0402_1%
1 2
R586 10K_0402_5% CLKSEL1 45 CLK_MCH_BCLK# 1 2
FSLB/TEST_MODE/24Mhz CLK_SRC9 R588 1 CLK_PCIE_CARD
ITP_EN/PCICLK_F0=0=SRC pair 3 2 0_0402_5% CLK_PCIE_CARD 27
R587 @ 49.9_0402_1%
R687 1 Dbg@ CLKSEL2 SRCCLKT9LP CLK_CPU_BCLK
26 CLK_14M_Dbg 2 33_0402_5% 23 REF0/FSLC/TEST_SEL 1 2
2 CLK_SRC9# R590 1 2 0_0402_5% CLK_PCIE_CARD# R589 @ 49.9_0402_1%
SRCCLKC9LP CLK_PCIE_CARD# 27 CLK_CPU_BCLK# 1 2
1 2 CLK_PCI4 26 CLK_PCI_Dbg
R688 1 Dbg@ 2 33_0402_5% CLK_PCI4 34 72 EXP_CLKREQ# 27
R591 @ 49.9_0402_1%
2 R592 10K_0402_5% PCICLK4/FCTSEL1 CLKREQ9# R593 1 2
2 10K_0402_5% +3VS
33 70
SEL_48M/PCICLK3 SRCCLKT8LP
CLK_PCI_card R594 1 2 33_0402_5% CLK_PCI2 32 69
23 CLK_PCI_card SEL_24M/PCICLK2 SRCCLKC8LP CLK_PCIE_VGA 1 2
CLK_PCI_LPC R596 1 2 33_0402_5% CLK_PCI1 27 71 R595 @ 49.9_0402_1%
28 CLK_PCI_LPC SEL_PCI6/PCICLK1 CLKREQ8# CLK_PCIE_VGA# 1 2
66 R597 @ 49.9_0402_1%
CLK_ICH_14M R598 1 CLK_REF SRCCLKT7LP
20 CLK_ICH_14M 2 33_0402_5% 22 SEL_PCI5/REF1
67
SRCCLKC7LP
CLK_DREF_96M R599 1 GM@ 2 0_0402_5% CLK_DOT 43 38
6 CLK_DREF_96M DOTT_96MHz/27MHz_NonspreadCLKREQ7#/48Mhz_1 CLK_PCIE_ICH 1 2
CLK_DREF_96M# R601 1 GM@ 2 0_0402_5% CLK_DOT# 44 63 CLK_SRC6 R602 1 2 0_0402_5% CLK_PCIE_SATA R600 @ 49.9_0402_1%
6 CLK_DREF_96M# DOTC_96MHz/27MHz_spread SRCCLKT6LP CLK_PCIE_SATA 19 CLK_PCIE_ICH# 1 2
64 CLK_SRC6# R604 1 2 0_0402_5% CLK_PCIE_SATA# R603 @ 49.9_0402_1%
SRCCLKC6LP CLK_PCIE_SATA# 19
CLK_PCI_ICH R605 1 2 33_0402_5% CLK_PCI0 37 CLK_PCIE_MINI1 1 2
18 CLK_PCI_ICH ITP_EN/PCICLK_F0
62 R606 @ 49.9_0402_1%
CLKREQ6# SATA_CLKREQ# 20
R607 1 2 10K_0402_5% CLK_PCIE_MINI1# 1 2
+3VS
CLK_ENABLE# 1 R743 2 0_0402_5% CLK_ENABLE#_R 39 60 CLK_SRC5 R609 1 2 0_0402_5% CLK_PCIE_ICH R608 @ 49.9_0402_1%
42 CLK_ENABLE# VTT_PWRGD#/PD SRCCLKT5LP CLK_PCIE_ICH 20 CLK_PCIE_SATA 1 2
@ 61 CLK_SRC5# R611 1 2 0_0402_5% CLK_PCIE_ICH# R610 @ 49.9_0402_1%
CLKIREF SRCCLKC5LP CLK_PCIE_ICH# 20 CLK_PCIE_SATA# 1
R612 1 2 0_0402_5% 9 2
+3VS GND R614 1
15mil 29 2 10K_0402_5% +3VS R613 @ 49.9_0402_1%
CLKREQ5#/PCICLK6 CLK_DREF_SSC 1 2
58 CLK_SRC4 R616 1 2 0_0402_5% CLK_PCIE_LAN R615 @ 49.9_0402_1%
SRCCLKT4LP CLK_PCIE_LAN 24
1 2 CLK_ENABLE#_R D_CK_SCLK 16 CLK_DREF_SSC# 1 2
12,13 D_CK_SCLK SMBCLK
R617 10K_0402_5% 59 CLK_SRC4# R619 1 2 0_0402_5% CLK_PCIE_LAN# R618 @ 49.9_0402_1%
SRCCLKC4LP CLK_PCIE_LAN# 24 CLK_DREF_96M 1 2
57 R621 1 2 @ 10K_0402_5% +3VS R620 @ 49.9_0402_1%
D_CK_SDATA CLKREQ4# CLK_DREF_96M# 1
12,13 D_CK_SDATA 17 2
SMBDAT CLK_SRC3 R623 1 PM@ CLK_PCIE_VGA
55 2 0_0402_5% CLK_PCIE_VGA 15
R622 @ 49.9_0402_1%
3 SRCCLKT3LP CLK_PCIE_CARD 1 3
2
4 56 CLK_SRC3# R625 1 PM@ 2 0_0402_5% CLK_PCIE_VGA# R624 @ 49.9_0402_1%
+3VS GNDSRC SRCCLKC3LP CLK_PCIE_VGA# 15 CLK_PCIE_CARD# 1 2
R629 15 28 CLK_PCI5 R627 1 2 @ 10K_0402_5% R626 @ 49.9_0402_1%
GNDCPU CLKREQ3#/PCICLK5 +3VS
4.7K_0402_5% CLK_MCH_3GPLL 1 2
2

Q48 1 CLK_SRC2 R630 1 2 0_0402_5% CLK_MCH_3GPLL R628 @ 49.9_0402_1%


G

2 +3VS 21 52 CLK_MCH_3GPLL 6
GNDREF SRCCLKT2LP CLK_MCH_3GPLL# 1
VGATE 6,20,42 2
1 3 D_CK_SDATA 31 53 CLK_SRC2# R632 1 2 0_0402_5% CLK_MCH_3GPLL# R631 @ 49.9_0402_1%
20,24,26,27 ICH_SMBDATA GNDPCI SRCCLKC2LP CLK_MCH_3GPLL# 6 CLK_PCIE_LAN 1 2
D

2N7002_SOT23 R633 @ 49.9_0402_1%


G

35 GNDPCI CLKREQ2# 26 MCH_CLKREQ# 6


R634 1 2 10K_0402_5% CLK_PCIE_LAN# 1 2
+3VS
CLK_ENABLE#_R 1 3 42 50 CLK_SRC1 R636 1 2 0_0402_5% CLK_PCIE_MINI1 R635 @ 49.9_0402_1%
+3VS GND48 SRCCLKT1LP CLK_PCIE_MINI1 26
D

R638 68 51 CLK_SRC1# R637 1 2 0_0402_5% CLK_PCIE_MINI1#


GNDSRC SRCCLKC1LP CLK_PCIE_MINI1# 26
4.7K_0402_5%
Q49
2
G

1 2 +3VS 46 MINI1_CLKREQ# 26
2N7002_SOT23 CLKREQ1# R639 1
73 2 10K_0402_5% +3VS
D_CK_SCLK THRM_PAD CLK_SRC0 R640 1 GM@ CLK_DREF_SSC
20,24,26,27 ICH_SMBCLK 1 3 74 47 2 0_0402_5% CLK_DREF_SSC 6
THRM_PAD LCD100/96/SRC0_TLP
75
D

THRM_PAD CLK_SRC0# R641 1 GM@ CLK_DREF_SSC#


76 48 2 0_0402_5% CLK_DREF_SSC# 6
2N7002_SOT23 THRM_PAD LCD100/96/SRC0_CLP
Q50

ICS9LPR325AKLFT_MLF72
+1.05VS +1.05VS +1.05VS
2

R642 R643 R644


@ 56_0402_5% @ 1K_0402_5% @ 1K_0402_5%

R645 R646 R647 R648 R649


8.2K_0402_5% 1K_0402_5% 1K_0402_5% 8.2K_0402_5% 1K_0402_5%
1

4 CLKSEL0 1 CLKSEL1 CLKSEL2 1 4


2 1 2 MCH_CLKSEL0 6 1 2 MCH_CLKSEL1 6 2 1 2 MCH_CLKSEL2 6
1 2 1 2 CPU_BSEL1 5 1 2 1 2 CPU_BSEL2 5
1 2 1 2 CPU_BSEL0 5 R650 R652 R653 R654
R655 R651 @ 0_0402_5% 0_0402_5% @ 0_0402_5% 0_0402_5%
@ 1K_0402_5% 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/10/4 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 14 of 44
A B C D E F G H
5 4 3 2 1

PCIE_MTX_C_GRX_N[0..15]
8 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
8 PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
8 PCIE_GTX_C_MRX_N[0..15]
D PCIE_GTX_C_MRX_P[0..15] D
8 PCIE_GTX_C_MRX_P[0..15]

JP19A JP19B

+MXM_B+ 1 2 +1.8VS PCIE_GTX_C_MRX_N1 109 110


PWR_SRC 1V8RUN PCIE_GTX_C_MRX_P1 PEX_RX1# GND PCIE_MTX_C_GRX_N1
3 PWR_SRC 1V8RUN 4 111 PEX_RX1 PEX_TX1# 112
5 6 140mil(3.5A) 113 114 PCIE_MTX_C_GRX_P1
PWR_SRC 1V8RUN PCIE_GTX_C_MRX_N0 GND PEX_TX1
7 PWR_SRC 1V8RUN 8 115 PEX_RX0# GND 116
9 10 PCIE_GTX_C_MRX_P0 117 118 PCIE_MTX_C_GRX_N0
PWR_SRC 1V8RUN PEX_RX0 PEX_TX0# PCIE_MTX_C_GRX_P0
11 PWR_SRC 1V8RUN 12 119 GND PEX_TX0 120
13 14 CLK_PCIE_VGA# 121 122
PWR_SRC 1V8RUN 14 CLK_PCIE_VGA# PEX_REFCLK# PRSNT1#
15 16 CLK_PCIE_VGA 123 124 VGA_TV_CRMA
PWR_SRC RUNPWROK VGA_ON 30 14 CLK_PCIE_VGA PEX_REFCLK TV_C/HDTV_Pr VGA_TV_CRMA 17
17 GND 5VRUN 18 +5VS 125 CLK_REQ# GND 126
19 20 127 128 VGA_TV_LUMA
GND GND 18 PLTRST_VGA# PEX_RST# TV_Y/HDTV_Y VGA_TV_LUMA 17
21 GND GND 22 129 RSVD GND 130
23 24 131 132 VGA_TV_COMPS
GND GND RSVD TV_CVBS/HDTV_Pb VGA_TV_COMPS 17
D_EC_SMB_DA1 133 134
D_EC_SMB_CK1 SMB_DAT GND VGA_CRT_R
135 SMB_CLK VGA_RED 136 VGA_CRT_R 17
137 THERM# GND 138
17 VGA_CRT_HSYNC VGA_CRT_HSYNC 139 140 VGA_CRT_G VGA_CRT_G 17
VGA_CRT_VSYNC VGA_HSYNC VGA_GRN
17 VGA_CRT_VSYNC 141 VGA_VSYNC GND 142
17 VGA_DDC_CLK VGA_DDC_CLK 143 144 VGA_CRT_B VGA_CRT_B 17
PCIE_GTX_C_MRX_N15 VGA_DDC_DATA DDCA_CLK VGA_BLU
25 PEX_RX15# PRSNT2# 26 17 VGA_DDC_DATA 145 DDCA_DAT GND 146
PCIE_GTX_C_MRX_P15 27 28 PCIE_MTX_C_GRX_N15 147 148 VGA_TZCLK- VGA_TZCLK- 16
PEX_RX15 PEX_TX15# PCIE_MTX_C_GRX_P15 IGP_UCLK# LVDS_UCLK# VGA_TZCLK+
29 GND PEX_TX15 30 149 IGP_UCLK LVDS_UCLK 150 VGA_TZCLK+ 16
C PCIE_GTX_C_MRX_N14 31 32 151 152 C
PCIE_GTX_C_MRX_P14 PEX_RX14# GND PCIE_MTX_C_GRX_N14 GND GND
33 PEX_RX14 PEX_TX14# 34 153 RSVD LVDS_UTX3# 154
35 36 PCIE_MTX_C_GRX_P14 155 156
PCIE_GTX_C_MRX_N13 GND PEX_TX14 RSVD LVDS_UTX3
37 PEX_RX13# GND 38 157 RSVD GND 158
PCIE_GTX_C_MRX_P13 39 40 PCIE_MTX_C_GRX_N13 159 160 VGA_TZOUT2- VGA_TZOUT2- 16
PEX_RX13 PEX_TX13# PCIE_MTX_C_GRX_P13 IGP_UTX2# LVDS_UTX2# VGA_TZOUT2+
41 GND PEX_TX13 42 161 IGP_UTX2 LVDS_UTX2 162 VGA_TZOUT2+ 16
PCIE_GTX_C_MRX_N12 43 44 163 164
PCIE_GTX_C_MRX_P12 PEX_RX12# GND PCIE_MTX_C_GRX_N12 GND GND VGA_TZOUT1-
45 PEX_RX12 PEX_TX12# 46 165 IGP_UTX1# LVDS_UTX1# 166 VGA_TZOUT1- 16
47 48 PCIE_MTX_C_GRX_P12 167 168 VGA_TZOUT1+ VGA_TZOUT1+ 16
PCIE_GTX_C_MRX_N11 GND PEX_TX12 IGP_UTX1 LVDS_UTX1
49 PEX_RX11# GND 50 169 GND GND 170
PCIE_GTX_C_MRX_P11 51 52 PCIE_MTX_C_GRX_N11 171 172 VGA_TZOUT0- VGA_TZOUT0- 16
PEX_RX11 PEX_TX11# PCIE_MTX_C_GRX_P11 IGP_UTX0# LVDS_UTX0# VGA_TZOUT0+
53 GND PEX_TX11 54 173 IGP_UTX0 LVDS_UTX0 174 VGA_TZOUT0+ 16
PCIE_GTX_C_MRX_N10 55 56 175 176
PCIE_GTX_C_MRX_P10 PEX_RX10# GND PCIE_MTX_C_GRX_N10 GND GND VGA_TXCLK-
57 PEX_RX10 PEX_TX10# 58 177 IGP_LCLK#/DVI_B_CLK# LVDS_LCLK# 178 VGA_TXCLK- 16
59 60 PCIE_MTX_C_GRX_P10 179 180 VGA_TXCLK+ VGA_TXCLK+ 16
PCIE_GTX_C_MRX_N9 GND PEX_TX10 IGP_LCLK/DVI_B_CLK LVDS_LCLK
61 PEX_RX9# GND 62 181 DVI_B_HPD/GND GND 182
PCIE_GTX_C_MRX_P9 63 64 PCIE_MTX_C_GRX_N9 183 184
PEX_RX9 PEX_TX9# PCIE_MTX_C_GRX_P9 RSVD LVDS_LTX3#
65 GND PEX_TX9 66 185 RSVD LVDS_LTX3 186
PCIE_GTX_C_MRX_N8 67 68 187 188
PCIE_GTX_C_MRX_P8 PEX_RX8# GND PCIE_MTX_C_GRX_N8 GND GND VGA_TXOUT2-
69 PEX_RX8 PEX_TX8# 70 189 IGP_LTX2#/DVI_B_TX2# LVDS_LTX2# 190 VGA_TXOUT2- 16
71 72 PCIE_MTX_C_GRX_P8 191 192 VGA_TXOUT2+ VGA_TXOUT2+ 16
PCIE_GTX_C_MRX_N7 GND PEX_TX8 IGP_LTX2/DVI_B_TX2 LVDS_LTX2
73 PEX_RX7# GND 74 193 GND GND 194
PCIE_GTX_C_MRX_P7 75 76 PCIE_MTX_C_GRX_N7 195 196 VGA_TXOUT1- VGA_TXOUT1- 16
PEX_RX7 PEX_TX7# PCIE_MTX_C_GRX_P7 IGP_LTX1#/DVI_B_TX1# LVDS_LTX1# VGA_TXOUT1+
77 GND PEX_TX7 78 197 IGP_LTX1/DVI_B_TX1 LVDS_LTX1 198 VGA_TXOUT1+ 16
PCIE_GTX_C_MRX_N6 79 80 199 200
PCIE_GTX_C_MRX_P6 PEX_RX6# GND PCIE_MTX_C_GRX_N6 GND GND VGA_TXOUT0-
81 PEX_RX6 PEX_TX6# 82 201 IGP_LTX0#/DVI_B_TX0# LVDS_LTX0# 202 VGA_TXOUT0- 16
83 84 PCIE_MTX_C_GRX_P6 203 204 VGA_TXOUT0+ VGA_TXOUT0+ 16
PCIE_GTX_C_MRX_N5 GND PEX_TX6 DVI_DET IGP_LTX0/DVI_B_TX0 LVDS_LTX0
85 PEX_RX5# GND 86 16 DVI_DET 205 DVI_A_HPD GND 206
PCIE_GTX_C_MRX_P5 87 88 PCIE_MTX_C_GRX_N5 16 VGA_DVI_TXC- VGA_DVI_TXC- 207 208 I2CC_SDA I2CC_SDA 16
B PEX_RX5 PEX_TX5# PCIE_MTX_C_GRX_P5 VGA_DVI_TXC+ DVI_A_CLK# DDCC_DAT I2CC_SCL B
89 GND PEX_TX5 90 16 VGA_DVI_TXC+ 209 DVI_A_CLK DDCC_CLK 210 I2CC_SCL 16
PCIE_GTX_C_MRX_N4 91 92 211 212 ENVDD
PEX_RX4# GND GND LVDS_PPEN ENVDD 16
PCIE_GTX_C_MRX_P4 93 94 PCIE_MTX_C_GRX_N4 16 VGA_DVI_TXD2- VGA_DVI_TXD2- 213 214
PEX_RX4 PEX_TX4# PCIE_MTX_C_GRX_P4 VGA_DVI_TXD2+ DVI_A_TX2# LVDS_BL_BRGHT ENBKL
95 GND PEX_TX4 96 16 VGA_DVI_TXD2+ 215 DVI_A_TX2 LVDS_BLEN 216 ENBKL 8,28
PCIE_GTX_C_MRX_N3 97 98 217 218 VGA_DVI_SDATA VGA_DVI_SDATA 16
PCIE_GTX_C_MRX_P3 PEX_RX3# GND PCIE_MTX_C_GRX_N3 VGA_DVI_TXD1- GND DDCB_DAT VGA_DVI_SCLK
99 PEX_RX3 PEX_TX3# 100 16 VGA_DVI_TXD1- 219 DVI_A_TX1# DDCB_CLK 220 VGA_DVI_SCLK 16
101 102 PCIE_MTX_C_GRX_P3 16 VGA_DVI_TXD1+ VGA_DVI_TXD1+ 221 222 +2.5VS
PCIE_GTX_C_MRX_N2 GND PEX_TX3 DVI_A_TX1 2V5RUN
103 PEX_RX2# GND 104 223 GND GND 224
PCIE_GTX_C_MRX_P2 105 106 PCIE_MTX_C_GRX_N2 16 VGA_DVI_TXD0- VGA_DVI_TXD0- 225 226 +3VS
PEX_RX2 PEX_TX2# PCIE_MTX_C_GRX_P2 VGA_DVI_TXD0+ DVI_A_TX0# 3V3RUN
107 GND PEX_TX2 108 16 VGA_DVI_TXD0+ 227 DVI_A_TX0 3V3RUN 228
229 GND 3V3RUN 230
231 GND GND 232
ACES_88990-2D08
CONN@ ACES_88990-2D08
CONN@ +3VS

2
+MXM_B+ +2.5VS +5VS

G
160mil(4A) L44 2 1 1 3 D_EC_SMB_DA1
B+ 28,29,38 EC_SMB_DA1
KC FBM-L11-201209-221LMAT_0805

S
PM@ 2 160mil(4A) 1 1 Q46
L43 2 1 C525 C471 C520 PM@ 2N7002_SOT23
KC FBM-L11-201209-221LMAT_0805

2
PM@ 0.1U_0402_16V4Z

G
1 1 1
C526 C527 0.1U_0603_25V7K PM@ 2 2
PM@ 0.1U_0402_16V4Z 1 3 D_EC_SMB_CK1
28,29,38 EC_SMB_CK1
680P_0603_50V7K 68P_0402_50V8J PM@

S
A 2 2 A
PM@ Q47

2N7002_SOT23

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MXM Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 15 of 44
5 4 3 2 1
5 4 3 2 1

TXOUT0- 1 4 VGA_TXOUT0-
VGA_TXOUT0- 15
TXOUT0+ 2 3 VGA_TXOUT0+
LCD POWER CIRCUIT TXOUT1-
RP4
1 4
PM@ 0_0404_4P2R_5%
VGA_TXOUT1-
VGA_TXOUT0+ 15

TXOUT1+ VGA_TXOUT1+ VGA_TXOUT1- 15


2 3 VGA_TXOUT1+ 15
RP6 PM@ 0_0404_4P2R_5%
+3V +3VS TXOUT2- 1 4 VGA_TXOUT2-
+LCDVDD VGA_TXOUT2- 15
W=60mils TXOUT2+ 2 3 VGA_TXOUT2+
VGA_TXOUT2+ 15
RP8 PM@ 0_0404_4P2R_5%
TXCLK- 1 4 VGA_TXCLK-
VGA_TXCLK- 15

1
1 TXCLK+ 2 3 VGA_TXCLK+
VGA_TXCLK+ 15
R11 R10 C19 RP10 PM@ 0_0404_4P2R_5%
300_0603_5% 100K_0402_5% TZOUT0- 1 4 VGA_TZOUT0-
D TZOUT0+ VGA_TZOUT0+ VGA_TZOUT0- 15 D
4.7U_0805_10V4Z 2 3
2 VGA_TZOUT0+ 15
RP12 PM@ 0_0404_4P2R_5%

1 2

2
TZOUT1- 1 4 VGA_TZOUT1-
VGA_TZOUT1- 15

3
D S
TZOUT1+ VGA_TZOUT1+
G 2 3 VGA_TZOUT1+ 15
Q2 2 2 1 2 Q1 RP14 PM@ 0_0404_4P2R_5%
2N7002_SOT23 G R9 1K_0402_5% AO3413_SOT23-3 TZOUT2- 1 4 VGA_TZOUT2-
TZOUT2+ VGA_TZOUT2+ VGA_TZOUT2- 15
S 1
D 2 3 VGA_TZOUT2+ 15

1
C16 +LCDVDD RP16 PM@ 0_0404_4P2R_5%
W=60mils TZCLK- 1 4 VGA_TZCLK-
VGA_TZCLK- 15

1
GM@ D 0.047U_0402_16V7K TZCLK+ VGA_TZCLK+
2 3 VGA_TZCLK+ 15
R14 2
8 GMCH_ENVDD 1 2 0_0402_5% 2 Q3 RP18 PM@ 0_0404_4P2R_5%
PM@ G 2N7002_SOT23 1 1
R13 1 2 0_0402_5% S C17 C10
15 ENVDD

3
1
4.7U_0805_10V4Z 0.1U_0402_16V4Z I2CC_SCL 1 4 GMCH_LCD_CLK
2 2 GMCH_LCD_CLK 8
R12 I2CC_SDA 2 3 GMCH_LCD_DATA GMCH_LCD_DATA 8
100K_0402_5% RP2 GM@ 0_0404_4P2R_5%
2

TXOUT0- 2 3 GMCH_TXOUT0-
+3VS TXOUT0+ GMCH_TXOUT0+ GMCH_TXOUT0- 8
1 4 GMCH_TXOUT0+ 8
RP3 GM@ 0_0404_4P2R_5%
TXOUT1- 2 3 GMCH_TXOUT1-
GMCH_TXOUT1- 8
1
TXOUT1+ 1 4 GMCH_TXOUT1+
GMCH_TXOUT1+ 8
R8 DAC_BRIG 1 2 RP5 GM@ 0_0404_4P2R_5%
C9 220P_0402_50V7K TXOUT2- 2 3 GMCH_TXOUT2-
INVTPWM TXOUT2+ GMCH_TXOUT2+ GMCH_TXOUT2- 8
4.7K_0402_5% 1 2 1 4 GMCH_TXOUT2+ 8
D4 C15 220P_0402_50V7K RP7 GM@ 0_0404_4P2R_5%
2

BKOFF# 1 2 RB751V_SOD323 DISPOFF# DISPOFF# 1 2 TXCLK- 2 3 GMCH_TXCLK-


28 BKOFF# TXCLK+ GMCH_TXCLK+ GMCH_TXCLK- 8
C11 220P_0402_50V7K 1 4 GMCH_TXCLK+ 8
RP9 GM@ 0_0404_4P2R_5%
C TZOUT0- GMCH_TZOUT0- C
2 3 GMCH_TZOUT0- 8
TZOUT0+ 1 4 GMCH_TZOUT0+
GMCH_TZOUT0+ 8
RP11 GM@ 0_0404_4P2R_5%
TZOUT1- 2 3 GMCH_TZOUT1-
TZOUT1+ GMCH_TZOUT1+ GMCH_TZOUT1- 8
1 4
LCD/PANEL BD. Conn. TZOUT2-
RP13
2 3
GM@ 0_0404_4P2R_5%
GMCH_TZOUT2-
GMCH_TZOUT1+ 8

GMCH_TZOUT2- 8
TZOUT2+ 1 4 GMCH_TZOUT2+
GMCH_TZOUT2+ 8
JP1 RP15 GM@ 0_0404_4P2R_5%
42 41 DAC_BRIG TZCLK- 2 3 GMCH_TZCLK-
GND GND DAC_BRIG 28 TZCLK+ GMCH_TZCLK+ GMCH_TZCLK- 8
+INVPWR_B+ 40 40 39 39 1 4 GMCH_TZCLK+ 8
38 37 INVTPWM R7 1 2 0_0402_5% RP17 GM@ 0_0404_4P2R_5%
38 37 INVT_PWM 28
36 35 DISPOFF#
+3VS 36 35
I2CC_SCL 34 33
15 I2CC_SCL 34 33 +LCDVDD
I2CC_SDA 32 31
15 I2CC_SDA 32 31
TZOUT0-
30
30 29
29 W=60mils W=40mils
28 27
TZOUT0+ 28 27 TXOUT0- +DVI_VCC
26 25
26 25 TXOUT0+ F2 D7
24 23
TZOUT1+ 24 23
22 22 21 21 1 2 1 2 +5VS
TZOUT1- 20 19 TXOUT1- 1
20 19 TXOUT1+ 1.1A_6VDC_FUSE RB411DT146_SOT23-3
18 17
TZOUT2+ 18 17 C23
16 15 DVI@ DVI@
TZOUT2- 16 15 TXOUT2+ 0.1U_0402_16V4Z
14 13
14 13 TXOUT2- 2 DVI@
12 11
TZCLK-
TZCLK+
10
8
12
10
11
9
9
7 TXCLK- R501 1 2 180_0402_1%
DVI-D Connector
0_0603_5% 8 7 TXCLK+ @ DVI_TXD0- +3VS
6 5 15 VGA_DVI_TXD0- 1 4 +DVI_VCC
R3 USB20_N3_R 6 5 DVI_TXD0+ JP15
20 USB20_N3 1 2 4 3 15 VGA_DVI_TXD0+ 2 3
4 3

1
R4 1 2 USB20_P3_R 2 1 RP45 0_0404_4P2R_5% 17 14
20 USB20_P3 2 1 +3VS TMDS_DATA0- +5V
0_0603_5% DVI@ 18 R17 R18
ACES_88242-4001 R502 1 TMDS_DATA0+
2 180_0402_1% 4.7K_0402_5% 4.7K_0402_5%

2
B CONN@ @ DVI_TXD1- DVI@ DVI@ B

G
15 VGA_DVI_TXD1- 2 3 9 TMDS_DATA1-
1 4 DVI_TXD1+ 10
15 VGA_DVI_TXD1+

2
RP1 0_0404_4P2R_5% TMDS_DATA1+
1 3 VGA_DVI_SCLK 15
DVI@ 1

S
DVI_TXD2- TMDS_DATA2- Q35
15 VGA_DVI_TXD2- 2 3 2 6
TMDS_DATA2+ DDC_CLOCK

2
DVI_TXD2+ 2N7002_SOT23

G
15 VGA_DVI_TXD2+ 1 4
RP46 0_0404_4P2R_5% 12 DVI@
DVI@ TMDS_DATA3-
1 2 13 7 1 3 VGA_DVI_SDATA 15
R503 180_0402_1% TMDS_DATA3+ DDC_DATA

S
+3VS @ 4 Q36
TMDS_DATA4- 2N7002_SOT23
5 TMDS_DATA4+ DVI@
1

U48 20 R360
TMDS_DATA5- DVI_DET
21 16 1 2
P
NC

TMDS_DATA5+ Hot Plug Detect DVI_DET 15


INVTPWM 4 2 R504 1 2 180_0402_1% 20K_0402_5%
Y A DPST_PWM 8

1
@ DVI@
G

1 4 DVI_TXC+ 23 R361
15 VGA_DVI_TXC+ DVI_TXC- TMDS_Clock+
NC7SZ14P5X_NL_SC70-5 2 3 24 D20
15 VGA_DVI_TXC-
3

RP47 0_0404_4P2R_5% TMDS_Clock- 100K_0402_5% SKS10-04AT_TSMA


@
DVI@ 3 DVI@ @

2
TMDS_DATA2/4 shield
11
TMDS_DATA1/3 shield
Optional for ATI M66M/M7x 25 Shield TMDS_DATA0/5 shield 19
2
G

R746 26 22
Shield TMDS_Clock shield
27 Shield
+3VS 1 2 INVTPWM 1 3 28
Shield
31
D

10K_0402_5% Shield
32 Shield
@
@ Q56
2N7002_SOT23 For GMCH DPST 8
Analog VSYNC GND
15

SUYIN_070939FR024S531PL
A CONN@ A
+INVPWR_B+ +LCDVDD
+3VS
L31 2 1 B+
W=40mils KC FBM-L11-201209-221LMAT_0805
1 1 1
L29 2 1 C18 C14 C8
KC FBM-L11-201209-221LMAT_0805
1 1 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
C432 C433 2 2 2
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

680P_0603_50V7K 68P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & DVI Connector
2 2 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 16 of 44
5 4 3 2 1
A B C D E

CRT Connector D3 D2 D1
W=40mils
@ @ @ +5VS +R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D19 F1 W=40mils

1
2 1 1 2

RB411DT146_SOT23-3 1.1A_6VDC_FUSE
1
+2.5VS @ 2 1 R685
0_0603_5% C430

3
+3VS @ 2 1 R686 0.1U_0402_16V4Z
0_0603_5% 2
1 1

CRT_R 1 2 CRT_R_2 JP14


L5 FCM2012C-800_0805 6
11
CRT_G 1 2 CRT_G_2 1
L3 FCM2012C-800_0805 7
12
CRT_B 1 2 CRT_B_2 2
L1 FCM2012C-800_0805 8

1
13

1
R6 R2 1 1 1 1 1 1 3
R1 9
C12 C6 C2 C7 C5 C3 14
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 4

2
2 2 2 2 2 2 10 16

2
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 15 17
150_0402_1% 1 5
C436
SUYIN_070549FR015S208CR
1 2 CRT_HSYNC_2 CONN@
L32 FCM1608C-121T_0603 2
change to 47pf for ATI M66/M7x CRT_DET 20
100P_0402_50V8J
1 2 CRT_VSYNC_2

2
L30 FCM1608C-121T_0603 DSUB_12
+CRT_VCC R763
1 1 1 100K_0402_5%
1 2 2 1 C434
C439 0.1U_0402_16V4Z R359 10K_0402_5% C435

1
10P_0402_50V8J 10P_0402_50V8J DSUB_15
+CRT_VCC

1
2 U18 2 2 C437 2 2
68P_0402_50V8J 1

OE#
P
4 1 CRT_VSYNC CRT_HSYNC 2 4 CRT_HSYNC_1
8 GMCH_CRT_VSYNC A Y
3 2 CRT_HSYNC C431
8 GMCH_CRT_HSYNC

G
RP48 GM@ 33_0404_4P2R_5% 68P_0402_50V8J
4 1 CRT_B SN74AHCT1G125DCKR_SC70-5 2
8 GMCH_CRT_B

3
3 2 CRT_G
8 GMCH_CRT_G +CRT_VCC
RP49 GM@ 0_0404_4P2R_5%
4 1 CRT_R
8 GMCH_CRT_R TV_COMPS
8 GMCH_TV_COMPS 3 2 1 2
RP50 GM@ 0_0404_4P2R_5% C438 0.1U_0402_16V4Z

1
4 1 TV_LUMA U19 +CRT_VCC
8 GMCH_TV_LUMA
3 2 TV_CRMA

OE#
P
8 GMCH_TV_CRMA CRT_VSYNC CRT_VSYNC_1
RP51 GM@ 0_0404_4P2R_5% 2 4 Place closed to chipset
A Y

G
SN74AHCT1G125DCKR_SC70-5 +3VS

1
1 4 CRT_VSYNC pull-up 2.2k on GPU side
15 VGA_CRT_VSYNC
2 3 CRT_HSYNC
15 VGA_CRT_HSYNC
RP52 PM@ 0_0404_4P2R_5% R381 1 2 R391
1 4 CRT_B 4.7K_0402_5% R384 PM@ 0_0402_5% VGA_DDC_DATA 15
15 VGA_CRT_B
2 3 CRT_G
15 VGA_CRT_G

2
RP53 PM@ 0_0404_4P2R_5%

G
1 4 CRT_R 4.7K_0402_5% R398 GM@ 0_0402_5%
15 VGA_CRT_R TV_COMPS DSUB_12
15 VGA_TV_COMPS 2 3 1 3 2 1
RP54 PM@ 0_0404_4P2R_5% GMCH_CRT_DATA 8

S
1 4 TV_LUMA Q20
15 VGA_TV_LUMA

2
TV_CRMA D14 D24 D25 2N7002_SOT23

G
15 VGA_TV_CRMA 2 3
RP55 PM@ 0_0404_4P2R_5% @ @ @
DAN217_SC59 DAN217_SC59 DAN217_SC59 DSUB_15 1 3 2 1
TV-OUT Conn. R399 GMCH_CRT_CLK 8

S
1

1
Place closed to chipset Q21 GM@ 0_0402_5%
3 2N7002_SOT23 3
1 2 R392 VGA_DDC_CLK 15
PM@ 0_0402_5%

pull-up 2.2k on GPU side

3
+3VS

TV_LUMA 1 2
L42 FCM1608C-121T_0603 JP24
3
TV_CRMA 1 2 TV_CRMA_1 6
L40 FCM1608C-121T_0603 TV_COMPS_1 7
5
TV_COMPS 1 2 2
L18 FCM1608C-121T_0603 TV_LUMA_1 4
1
8
1

R205 R413 R416 1 1 1 1 1 1 9


C211 C510 C514 C216 C508 C515
GM@ GM@
150_0402_1% GM@ 6P_0402_50V8K GM@ 6P_0402_50V8K SUYIN_030107FR007SX08FU
150_0402_1% 2 2
6P_0402_50V8K 2 2 2
6P_0402_50V8K 2
CONN@
2

GM@ GM@
150_0402_1% 6P_0402_50V8K 6P_0402_50V8K

4 4
change to 47pf for ATI M66/M7x
P/N: SE071470J80 ( S CER CAP 47P 50V J NPO 0402 )

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 17 of 44
A B C D E
5 4 3 2 1

+3VS
23 PCI_AD[0..31] U42B
PCI_AD0 E18 D7 PCI_REQ#0
AD0 REQ0# PCI_REQ#0 23
PCI_AD1 C18 E7 PCI_GNT#0
AD1 GNT0# PCI_GNT#0 23
R143 1 2 8.2K_0402_5% PCI_DEVSEL# PCI_AD2 PCI_REQ#1
PCI_AD3
A16
F18
AD2 PCI REQ1# C16
D16
R144 1 AD3 GNT1#
D 2 8.2K_0402_5% PCI_STOP# PCI_AD4 E16 AD4 REQ2# C17 PCI_REQ#2 D
PCI_AD5 A18 D17
R139 1 AD5 GNT2#
2 8.2K_0402_5% PCI_TRDY# PCI_AD6 E17 AD6 REQ3# E13 PCI_REQ#3
PCI_AD7 A17 F13
R145 1 AD7 GNT3#
2 8.2K_0402_5% PCI_FRAME# PCI_AD8 A15 AD8 REQ4# / GPIO22 A13 PCI_REQ#4
PCI_AD9 C14 A14 PCI_GNT#4
R137 1 AD9 GNT4# / GPIO48
2 8.2K_0402_5% PCI_PLOCK# PCI_AD10 E14 AD10 GPIO1 / REQ5# C8 PCI_REQ#5
PCI_AD11 D14 D8 PCI_GNT#5
R122 1 AD11 GPIO17 / GNT5#
2 8.2K_0402_5% PCI_IRDY# PCI_AD12 B12 AD12
PCI_AD13 C13 B15 PCI_CBE#0
AD13 C/BE0# PCI_CBE#0 23
R124 1 2 8.2K_0402_5% PCI_SERR# PCI_AD14 G15 C12 PCI_CBE#1
AD14 C/BE1# PCI_CBE#1 23
PCI_AD15 G13 D12 PCI_CBE#2
AD15 C/BE2# PCI_CBE#2 23
R138 1 2 8.2K_0402_5% PCI_PERR# PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 23
PCI_AD17 C11
PCI_AD18 AD17 PCI_IRDY#
D11 AD18 IRDY# A7 PCI_IRDY# 23
PCI_AD19 A11 E10 PCI_PAR
+3VS AD19 PAR PCI_PAR 23
PCI_AD20 A10 B18 PCI_RST#
AD20 PCIRST# PCI_RST# 23,26,27
PCI_AD21 F11 A12 PCI_DEVSEL#
AD21 DEVSEL# PCI_DEVSEL# 23
PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# 23
R109 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10 PCI_SERR# 23
R120 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD25 B9 F15 PCI_STOP# Place closely pin B10
AD25 STOP# PCI_STOP# 23
PCI_AD26 A8 F14 PCI_TRDY#
AD26 TRDY# PCI_TRDY# 23
R136 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD27 A6 F16 PCI_FRAME#
AD27 FRAME# PCI_FRAME# 23
PCI_AD28 C7 CLK_PCI_ICH
R140 1 AD28
2 8.2K_0402_5% PCI_PIRQD# PCI_AD29 B6 AD29 PLTRST# C26 PLT_RST#
PLT_RST# 6,20,22,24,28

2
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH 14
R108 1 2 8.2K_0402_5% PCI_PIRQE# PCI_AD31 D6 B19 PCI_PME#
AD31 PME# PCI_PME#
R123
C R111 1 2 8.2K_0402_5% PCI_PIRQF# 10_0402_5% C

Interrupt I/F @

1
R112 1 2 8.2K_0402_5% PCI_PIRQG# PCI_PIRQA# A3 G8 PCI_PIRQE#
PIRQA# GPIO2 / PIRQE# PCI_PIRQE# 23
PCI_PIRQB# B4 F7 PCI_PIRQF# 1
R134 1 PIRQB# GPIO3 / PIRQF#
2 8.2K_0402_5% PCI_PIRQH# PCI_PIRQC# C5 PIRQC# GPIO4 / PIRQG# F8 PCI_PIRQG# C126
PCI_PIRQD# B5 G7 PCI_PIRQH# 10P_0402_50V8J
R135 1 PIRQD# GPIO5 / PIRQH#
2 8.2K_0402_5% PCI_REQ#0 @
2
R125 1
MISC
2 8.2K_0402_5% PCI_REQ#1 AE5 RSVD[1] RSVD[6] AE9
AD5 RSVD[2] RSVD[7] AG8
R146 1 2 8.2K_0402_5% PCI_REQ#2 AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R142 1 2 8.2K_0402_5% PCI_REQ#3 AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# 6
R666 1 2 8.2K_0402_5% PCI_REQ#4
ICH7_BGA652~D
R667 1 2 8.2K_0402_5% PCI_REQ#5

R121 1 2 1K_0402_5% PCI_GNT#5


@
B R126 B
1 2 1K_0402_5% PCI_GNT#4
@

+3VS

Boot BIOS Strap

5
U8
PLT_RST#
PCI_GNT#5 PCI_GNT#4 Boot BIOS Loaction 2 B

P
Y 4 PLT_RST_BUF# 26
1 A

G
0 1 SPI

1
NC7SZ08P5X_NL_SC70-5

3
R316
100K_0402_5%
1 0 PCI

2
+3VS
1 1 LPC*

5
U9
2 B

P
Y 4 2 1 PLTRST_VGA# 15
1 R321 100_0402_5%
A
G
PM@

1
NC7SZ08P5X_NL_SC70-5
3

PM@ R317
100K_0402_5%
PM@

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7M(1/4)-PCI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 18 of 44
5 4 3 2 1
5 4 3 2 1

+RTCVCC
C287
18P_0402_50V8J
2 1 ICH_RTCX1

1
R265 X1

10M_0402_5%
1
3 NC OUT 4

R263
1M_0402_5%
32.768KHZ_12.5P_MC-306 2 1 +1.05VS
2

SM_INTRUDER# NC IN U42A
C286

RTC
D 18P_0402_50V8J AB1 AA6 LPC_AD0 D
RTXC1 LAD0 LPC_AD0 26,28
2 1 ICH_RTCX2 AB2 AB5 LPC_AD1
+RTCVCC RTCX2 LAD1 LPC_AD1 26,28
AC4 LPC_AD2
LAD2 LPC_AD2 26,28
+RTCVCC 1 2 ICH_RTCRST# AA3 Y6 LPC_AD3 H_FERR# 2 1
RTCRST# LAD3 LPC_AD3 26,28

LPC
R264 R250 56_0402_5%
20K_0402_5% ICH_INTVRMEN W4 AC3
INTVRMEN LDRQ0#
1

SM_INTRUDER# Y5 AA5
R281 R754 INTRUDER# LDRQ1# / GPIO23 LPC_DRQ#1 26
332K_0402_1% 1 2 AB3 LPC_FRAME#
LFRAME# LPC_FRAME# 26,28
close to RAM door @ 10K_0603_5% W1 EE_CS
Y1 2 1 R271 10K_0402_5% +3VS
2

EE_SHCLK EC_GA20
Y2 EE_DOUT A20GATE AE22 EC_GA20 28

LAN
ICH_INTVRMEN C292 W3 AH28 H_A20M#
EE_DIN A20M# H_A20M# 4

CPU
High = Internal VR Enable 1U_0603_10V4Z
1 2 V3 LAN_CLK CPUSLP# AG27

U3 AF24 DPRSTP# R260 1 2 0_0402_5% H_DPRSTP#


LAN_RSTSYNC TP1 / DPRSTP# H_DPRSTP# 4,42
AH25 DPSLP# R261 1 2 0_0402_5% H_DPSLP#
TP2 / DPSLP# H_DPSLP# 4
U5 LAN_RXD0
V4 AG26 H_FERR#
LAN_RXD1 FERR# H_FERR# 4
T5 LAN_RXD2
+3VS AG24 H_PW RGOOD
GPIO49 / CPUPWRGD H_PW RGOOD 4
U7 LAN_TXD0
V6 AG22 H_IGNNE#
LAN_TXD1 IGNNE# H_IGNNE# 4
1

V7 LAN_TXD2 INIT3_3V# AG21


R298 AF22 H_INIT#
INIT# H_INIT# 4
AF25 H_INTR
INTR H_INTR 4
10K_0402_5%

AC-97/AZALIA
1 2 HDA_BITCLK_ICH U1 R272 2 1 10K_0402_5%
30 HDA_BITCLK_MDC +3VS
2

C R293 39_0402_5%HDA_SYNC_ICH ACZ_BCLK EC_KBRST# C


30 HDA_SYNC_MDC 1 2 R6 ACZ_SYNC RCIN# AG23 EC_KBRST# 28
R292 39_0402_5%
SATA_LED# 1 2 HDA_RST_ICH# R5 AF23 H_SMI#
30 HDA_RST_MDC# ACZ_RST# SMI# H_SMI# 4
R301 39_0402_5% AH24 H_NMI
NMI H_NMI 4
31 HDA_SDIN0 T2 ACZ_SDIN0
30 HDA_SDIN1 T3 AH22 H_STPCLK#
ACZ_SDIN1 STPCLK# H_STPCLK# 4
T1 ACZ_SDIN2
AF26 THRMTRIP_ICH# R258 1 2 24.9_0402_1% H_THERMTRIP#
THERMTRIP# H_THERMTRIP# 4,6
1 2 HDA_SDOUT_ICH T4
30 HDA_SDOUT_MDC ACZ_SDOUT
R310 39_0402_5% IDE_DA[0..2] 22 2 1 +1.05VS
AH17 IDE_DA0 R257 56_0402_5%
SATA_LED# DA0 IDE_DA1
28 SATA_LED# AF18 SATALED# DA1 AE17
AF17 IDE_DA2
DA2
22 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AF3 AE16 IDE_DCS1# IDE_DCS1# 22
SATA_DTX_C_IRX_P0 SATA0RXN DCS1# IDE_DCS3#
22 SATA_DTX_C_IRX_P0 AE3 SATA0RXP DCS3# AD16 IDE_DCS3# 22
SATA_ITX_DRX_N0 AG2 SATA0TXN

SATA
31 HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_ICH SATA_ITX_DRX_P0 AH2 SATA0TXP IDE_DD[0..15] 22
R279 39_0402_5% AB15 IDE_DD0
SATA_DTX_C_IRX_N1 DD0 IDE_DD1
22 SATA_DTX_C_IRX_N1 AF7 SATA2RXN DD1 AE14
31 HDA_SYNC_AUDIO 1 2 HDA_SYNC_ICH 22 SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 AE7 AG13 IDE_DD2
R273 39_0402_5% SATA_ITX_DRX_N1 SATA2RXP DD2 IDE_DD3
AG6 SATA2TXN DD3 AF13
SATA_ITX_DRX_P1 AH6 AD14 IDE_DD4
HDA_RST_ICH# SATA2TXP DD4 IDE_DD5
31 HDA_RST_AUDIO# 1 2 DD5 AC13
R300 39_0402_5% CLK_PCIE_SATA# AF1 AD12 IDE_DD6
14 CLK_PCIE_SATA# SATA_CLKN DD6
CLK_PCIE_SATA AE1 AC12 IDE_DD7
14 CLK_PCIE_SATA SATA_CLKP DD7
31 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT_ICH AE12 IDE_DD8
R299 39_0402_5% DD8 IDE_DD9
AH10 SATARBIASN DD9 AF12 MAINPW ON 35,36,38
R242 1 2 24.9_0402_1% SATARBIAS AG10 AB13 IDE_DD10
B SATARBIASP DD10 IDE_DD11 B
10mils width less than 500mils DD11 AC14
IDE_DD12 R189
DD12 AF14

1
AH13 IDE_DD13 @ 330_0402_5% C
DD13 IDE_DD14 Q10
IDE_DIORDY AG16
IDE DD14 AH14
AC15 IDE_DD15
+1.05VS 1 2 2
B
22 IDE_DIORDY IORDY DD15 E
4.7K_0402_5% 2 1 R203 IDE_DIORDY IDE_IRQ AH16 2SC2411K_SOT23
+3VS 22 IDE_IRQ

3
IDE_DDACK# IDEIRQ @
22 IDE_DDACK# AF16 DDACK#
IDE_DIOW # AH15 AE15 IDE_DDREQ
22 IDE_DIOW # DIOW# DDREQ IDE_DDREQ 22
8.2K_0402_5% 2 1 R199 IDE_IRQ IDE_DIOR# AF15 H_THERMTRIP#
22 IDE_DIOR# DIOR#

ICH7_BGA652~D

SATA_ITX_DRX_N0 1 2 SATA_ITX_C_DRX_N0 SATAX1@


C290 3900P_0402_50V7K SATA_ITX_C_DRX_N0 22 SATA_DTX_C_IRX_N1
1 2
SATA_ITX_DRX_P0 1 2 SATA_ITX_C_DRX_P0 R656 1K_0402_5%
C291 3900P_0402_50V7K SATA_ITX_C_DRX_P0 22
1 SATAX1@2 SATA_DTX_C_IRX_P1
R657 1K_0402_5%
SATA_ITX_DRX_N1 1 2 SATA_ITX_C_DRX_N1
SATAX2@ C281 3900P_0402_50V7K SATA_ITX_C_DRX_N1 22
SATA_ITX_DRX_P1 1 2 SATA_ITX_C_DRX_P1
SATAX2@ C280 3900P_0402_50V7K SATA_ITX_C_DRX_P1 22

A SATA_RXn/p need tie to ground when SATA port no used A


close ICH8

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7M(2/4)-LAN,IDELPC,RTC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 19 of 44
5 4 3 2 1
5 4 3 2 1

+3V
+3VS
Place closely pin B2 Place closely pin AC1

1
10K_0402_5%
R308 1 2 SERIRQ R157 R155
2.2K_0402_5% 2.2K_0402_5% +3VS CLK_ICH_48M CLK_ICH_14M
8.2K_0402_5% U42C
R270 1 2 PM_CLKRUN# @ R284

1
ICH_SMBCLK C22 AF19 2 1
14,24,26,27 ICH_SMBCLK SMBCLK GPIO21 / SATA0GP
ICH_SMBDATA B22 AH18 10K_0402_5% R168 R283
14,24,26,27 ICH_SMBDATA SMBDATA GPIO19 / SATA1GP

SMB
SATA
GPIO
10K_0402_5% LINKALERT# A26 AH19 10_0402_5% 10_0402_5%
R658 1 ICH_VGATE ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP @ @
2 B25 SMLINK0 GPIO37 / SATA3GP AE19 2 1
ICH_SMLINK1 A25 R65910K_0402_5%

2
SMLINK1
8.2K_0402_5% 1 1
R309 1 2 EC_THERM# AC1 CLK_ICH_14M C165 C298
CLK14 CLK_ICH_14M 14

Clocks
D @ EC_SWI# CLK_ICH_48M 10P_0402_50V8J 10P_0402_50V8J D
28 EC_SWI# A28 RI# CLK48 B2 CLK_ICH_48M 14
@ @
SB_SPKR A19 2 2
31 SB_SPKR SPKR
High: CRT Plugged PAD SUS_STAT# A27 C20 SUS_CLK
T6
XDP_DBRESET# SUS_STAT# SUSCLK
4 XDP_DBRESET# A22
SYS_RST#

SYS
B24 PM_SLP_S3#
PM_BMBUSY# SLP_S3# PM_SLP_S4# PM_SLP_S3# 28
AB18 D23 PM_SLP_S4# 28
6 PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# PM_SLP_S5#
SLP_S5# F22 PM_SLP_S5# 28
SMBALERT# B23
+3V GPIO11 / SMBALERT#
AA4 SYS_PWROK SYS_PWROK 6,30
10K_0402_5% PM_STP_PCI# PWROK
AC20 1 2

POWER MGT
14 PM_STP_PCI# GPIO18 / STPPCI#

GPIO
R313 1 2 EC_SWI# PM_STP_CPU# AF21 AC22 DPRSLPVRR2621 210K_0402_5%
14 PM_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR PM_DPRSLPVR 6,42
R286 100_0402_5%
10K_0402_5% CP_PE# A21 C21 PM_BATLOW#
R312 1 ICH_SMLINK0 27 CP_PE# GPIO26 TP0 / BATLOW#
2
PROJECT_ID0 B21 C23 PBTN_OUT#
PROJECT_ID1 GPIO27 PWRBTN# PBTN_OUT# 28
10K_0402_5% E23
R303 1 ICH_SMLINK1 GPIO28
2 C19 PLT_RST# 6,18,22,24,28
PM_CLKRUN# LAN_RST#
28 PM_CLKRUN#
AG18 GPIO32 / CLKRUN# SB_RSMRST#
No used Integrated LAN,
10K_0402_5% Y4
R276 1 2 LINKALERT# AC19
RSMRST# connecting to PLT_RST#
IDE_HRESET# GPIO33 / AZ_DOCK_EN#
22 IDE_HRESET# U2
150_0402_1% GPIO34 / AZ_DOCK_RST#
R311 1 2 XDP_DBRESET# ICH_PCIE_WAKE# F20 E20 EC_SCI# 100K_0402_5%
24,26,27 ICH_PCIE_WAKE# WAKE# GPIO9 EC_SCI# 28 +3VS
SERIRQ AH21 A20 2 1 R278 @
26,28 SERIRQ SERIRQ GPIO10
1K_0402_5% EC_THERM# AF20 F19 R453 2 1 0_0402_5%
ICH_PCIE_WAKE# 28 EC_THERM# THRM# GPIO12
R302 1 2 E19 2 1 Q14
GPIO13 EC_LID_OUT# 28 ACIN 28,38
6,14,42 VGATE 2 1 ICH_VGATE AD22 R4 D15 MMBT3906_NL_SOT23-3
8.2K_0402_5% R267 0_0402_5% VRMPWRGD GPIO14 SB_RSMRST#
E22

C
GPIO15 EC_RSMRST# 28
R287 2 1 PM_BATLOW# R3 RB751V_SOD323

E
CRT_DET# GPIO24
AC21
GPIO6 GPIO GPIO25
D20

1
10K_0402_5% AC18 AD21

B
C SPI_CS#1 EC_SMI# GPIO7 GPIO35 / SATAREQ# SATA_CLKREQ# 14 C
R660 1 2 E21 AD20 R259 1 2
28 EC_SMI# GPIO8 GPIO38 +3V
10K_0402_5% AE20 10K_0402_5% R325 4.7K_0402_5%
R661 1 SPI_MOSI GPIO39
2
10K_0402_5% ICH7_BGA652~D

2
R662 1 2 SPI_MISO D17A
1
6
2
10K_0402_5%
R277 1 2 SMBALERT# BAV99DW-7_SOT363

@ 10K_0402_5% D17B
R269 1 2 4
3
10K_0402_5% U42D 5
R268 1 2 PROJECT_ID0 PCIE_PTX_C_IRX_N1 F26 V26 DMI_MTX_IRX_N0
27 PCIE_PTX_C_IRX_N1 PERn1 DMI0RXN DMI_MTX_IRX_N0 6

1
PCIE_PTX_C_IRX_P1 F25 V25 DMI_MTX_IRX_P0 BAV99DW-7_SOT363
27 PCIE_PTX_C_IRX_P1 PERp1 DMI0RXP DMI_MTX_IRX_P0 6
10K_0402_5% For Express Card C175 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N1 E28 U28 DMI_ITX_MRX_N0 R329
27 PCIE_ITX_C_PRX_N1 PETn1 DMI0TXN DMI_ITX_MRX_N0 6

DIRECT MEDIA INTERFACE


R290 1 2 PROJECT_ID1 C174 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P1 E27 U27 DMI_ITX_MRX_P0 2.2K_0402_5%
27 PCIE_ITX_C_PRX_P1 PETp1 DMI0TXP DMI_ITX_MRX_P0 6
100K_0402_5% H26 Y26 DMI_MTX_IRX_N1
DMI_MTX_IRX_N1 6

2
R285 1 PM_DPRSLPVR PERn2 DMI1RXN DMI_MTX_IRX_P1
2 H25 Y25 DMI_MTX_IRX_P1 6
PERp2 DMI1RXP DMI_ITX_MRX_N1
G28 W28 DMI_ITX_MRX_N1 6
PETn2 DMI1TXN DMI_ITX_MRX_P1
G27 W27 DMI_ITX_MRX_P1 6
PETp2 DMI1TXP

PCI-EXPRESS
PCIE_PTX_C_IRX_N3 K26 AB26 DMI_MTX_IRX_N2
24 PCIE_PTX_C_IRX_N3 PERn3 DMI2RXN DMI_MTX_IRX_N2 6
@ 10K_0402_5% PCIE_PTX_C_IRX_P3 K25 AB25 DMI_MTX_IRX_P2
24 PCIE_PTX_C_IRX_P3 PERp3 DMI2RXP DMI_MTX_IRX_P2 6
R663 1 2 SUS_CLK For PCIE LAN C166 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N3 J28 AA28 DMI_ITX_MRX_N2
24 PCIE_ITX_C_PRX_N3 PETn3 DMI2TXN DMI_ITX_MRX_N2 6
C168 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P3 J27 AA27 DMI_ITX_MRX_P2
24 PCIE_ITX_C_PRX_P3 PETp3 DMI2TXP DMI_ITX_MRX_P2 6
PCIE_PTX_C_IRX_N4 M26 AD25 DMI_MTX_IRX_N3
26 PCIE_PTX_C_IRX_N4 PCIE_PTX_C_IRX_P4 PERn4 DMI3RXN DMI_MTX_IRX_P3 DMI_MTX_IRX_N3 6
26 PCIE_PTX_C_IRX_P4 M25 AD24 DMI_MTX_IRX_P3 6
B C162 2 0.1U_0402_16V7K PCIE_ITX_PRX_N4 PERp4 DMI3RXP DMI_ITX_MRX_N3 B
For Wireless LAN 26 PCIE_ITX_C_PRX_N4 1
PCIE_ITX_PRX_P4
L28 PETn4 DMI3TXN AC28
DMI_ITX_MRX_P3
DMI_ITX_MRX_N3 6
26 PCIE_ITX_C_PRX_P4 C158 2 1 0.1U_0402_16V7K L27 AC27
PETp4 DMI3TXP DMI_ITX_MRX_P3 6
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH# 14
P25 AE27 CLK_PCIE_ICH
PERp5 DMI_CLKP CLK_PCIE_ICH 14
N28
PETn5 R213 24.9_0402_1%
N27
PETp5 DMI_ZCOMP
C25
DMI_IRCOMP
Within 500 mils
D25 1 2 +1.5VS
DMI_IRCOMP
T25
PERn6
+3V 1 2 USB_OC#1 T24 PERp6 USBP0N F1 USB20_N0
USB20_N0 27
R294 10K_0402_5% R28 F2 USB20_P0 USB Conn.
PETn6 USBP0P USB20_P0 27
1 2 USB_OC#3 R27 G4 USB20_N1
USB20_N1 27
R320 10K_0402_5% PETp6 USBP1N USB20_P1
USBP1P G3 USB20_P1 27 New Card
1 2 USB_OC#5 R2 H1 USB20_N2
USB20_N2 27
R296 10K_0402_5% SPI_CS#1 SPI_CLK USBP2N USB20_P2
P6 SPI_CS# USBP2P H2 USB20_P2 27 USB Conn.

SPI
1 2 USB_OC#7 P1 J4 USB20_N3
USB20_N3 16
R668 10K_0402_5% SPI_ARB USBP3N USB20_P3
SPI_MOSI USBP3P
J3
USB20_N4 USB20_P3 16 CMOS Camera
P5 K1 USB20_N4 26
SPI_MISO SPI_MOSI USBP4N USB20_P4
P2
SPI_MISO USBP4P
K2
USB20_N5 USB20_P4 26 USB/B
L4 USB20_N5 27
USBP5N USB20_P5
USBP5P
L5 USB20_P5 27 Bluetooth
1 2 USB_OC#4 27 USB_OC#0
USB_OC#0 D3 OC0# USBP6N M1 USB20_N6
USB20_N6 26
R512 10K_0402_5% USB_OC#1 USB20_P6
+3VS 1 2 USB_OC#6 USB_OC#2
C4
D5
OC1# USB USBP6P
M2
N4 USB20_N7 USB20_P6 26 USB/B
27 USB_OC#2 USB_OC#3 OC2# USBP7N USB20_P7 USB20_N7 26
R513 10K_0402_5% D4 N3 Mini Card(WLAN)
OC3# USBP7P USB20_P7 26
USB_OC#4 E5
USB_OC#5 OC4#
C3 OC5# / GPIO29
2

USB_OC#6 A2 D2 USBRBIAS 1 2
R670 USB_OC#7 OC6# / GPIO30 USBRBIAS# R160
B3 D1
OC7# / GPIO31 USBRBIAS 22.6_0402_1%
D33 100K_0402_5%

1 2 CRT_DET# ICH7_BGA652~D Within 500 mils


17 CRT_DET
1

A A

1SS355_SOD323-2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7M(3/4)-USB,GPIO,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 20 of 44
5 4 3 2 1
5 4 3 2 1

+1.05VS U42E
+5VALW U42F A4 P28
VSS[0] VSS[98]
A23 R1
+ICH_V5REF 0.1U_0402_16V4Z VSS[1] VSS[99]
G10 V5REF[1] Vcc1_05[1] L11 B1 VSS[2] VSS[100] R11
L12 B8 R12
Vcc1_05[2] VSS[3] VSS[101]

3
S
AD17 L14 1 B11 R13
G V5REF[2] Vcc1_05[3] VSS[4] VSS[102]
34 SBPWR_EN# 2 L16 1 1 B14 R14
+1.5VS +ICH_V5REF_SUS Vcc1_05[4] C792 C794 + C795 VSS[5] VSS[103]
F6 V5REF_Sus Vcc1_05[5] L17 B17 VSS[6] VSS[104] R15
1 Q44 D L18 B20 R16

1
C630 AO3413_SOT23-3 0.1U_0402_16V4Z Vcc1_05[6] 220U_D2_2VMR15 VSS[7] VSS[105]
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B26 VSS[8] VSS[106] R17
2 2 2
1 AA23 M18 B28 R18
0.1U_0603_25V7K Vcc1_5_B[2] Vcc1_05[8] VSS[9] VSS[107]
1 1 1 AB22 Vcc1_5_B[3] Vcc1_05[9] P11 C2 VSS[10] VSS[108] T6
D 2 C793 + C796 C797 C798 D
AB23 P18 C6 T12
Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z VSS[11] VSS[109]
AC23 T11 C27 T13
220U_D2_2VMR15 Vcc1_5_B[5] Vcc1_05[11] VSS[12] VSS[110]
+5V AC24 T18 D10 T14
2 2 2 2 Vcc1_5_B[6] Vcc1_05[12] VSS[13] VSS[111]
AC25 U11 D13 T15
Vcc1_5_B[7] Vcc1_05[13] VSS[14] VSS[112]
AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D18 VSS[15] VSS[113] T16
0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D21 T17
+5VS +3VS Vcc1_5_B[9] Vcc1_05[15] VSS[16] VSS[114]
AD27 Vcc1_5_B[10] Vcc1_05[16] V12 D24 VSS[17] VSS[115] U4
AD28 V14 E1 U12
Vcc1_5_B[11] Vcc1_05[17] VSS[18] VSS[116]
Place closely pin D26 Vcc1_5_B[12] Vcc1_05[18] V16 E2 VSS[19] VSS[117] U13
2

D27 V17 E4 U14


R149 D8 D28,T28,AD28. Vcc1_5_B[13] Vcc1_05[19] VSS[21] VSS[118]
D28 Vcc1_5_B[14] Vcc1_05[20] V18 E8 VSS[22] VSS[119] U15
E24 Vcc1_5_B[15] E15 VSS[23] VSS[120] U16
100_0402_5% RB751V_SOD323 E25 U6 +3VS F3 U17
Vcc1_5_B[16] Vcc3_3 / VccHDA VSS[24] VSS[121]
E26 1 F4 U24
1

+ICH_V5REF Vcc1_5_B[17] +1.05VS C799 VSS[25] VSS[122]


F23 R7 +3V F5 U25
Vcc1_5_B[18] VccSus3_3/VccSusHDA VSS[26] VSS[123]
2 F24 F12 U26
C150 Vcc1_5_B[19] C800 0.1U_0402_16V4Z VSS[27] VSS[124]
G22 Vcc1_5_B[20] V_CPU_IO[1] AE23 F27 VSS[28] VSS[125] V2
2
G23 AE26 1 2 F28 V13
0.1U_0402_16V4Z Vcc1_5_B[21] V_CPU_IO[2] VSS[29] VSS[126]
H22 AH26 G1 V15
1 Vcc1_5_B[22] V_CPU_IO[3] 0.1U_0402_16V4Z VSS[30] VSS[127]
H23 Vcc1_5_B[23] G2 VSS[31] VSS[128] V24
J22 AA7 +3VS 1 2 G5 V27
Vcc1_5_B[24] Vcc3_3[3] VSS[32] VSS[129]
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G6 VSS[33] VSS[130] V28
K22 AB20 1 C801 G9 W6
Vcc1_5_B[26] Vcc3_3[5] C802 0.1U_0402_16V4Z VSS[34] VSS[131]
K23 AC16 G14 W24
+5VALW +5V +3V Vcc1_5_B[27] Vcc3_3[6] VSS[35] VSS[132]
L22 AD13 1 2 G18 W25
Vcc1_5_B[28] Vcc3_3[7] 0.1U_0402_16V4Z VSS[36] VSS[133]
L23 AD18 G21 W26
Vcc1_5_B[29] Vcc3_3[8] 2 C803 VSS[37] VSS[134]
M22 AG12 G24 Y3
Vcc1_5_B[30] Vcc3_3[9] VSS[38] VSS[135]
2

M23 AG15 4.7U_0805_10V4Z G25 Y24


R165 R158 D10 Vcc1_5_B[31] Vcc3_3[10] VSS[39] VSS[136]
N22 AG19 G26 Y27
Vcc1_5_B[32] Vcc3_3[11] VSS[40] VSS[137]
N23 H3 Y28
C 10_0402_5% 10_0402_5% RB751V_SOD323 Vcc1_5_B[33] VSS[41] VSS[138] C
P22 Vcc1_5_B[34] Vcc3_3[12] A5 +3VS H4 VSS[42] VSS[139] AA1
@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P23 B13 H5 AA24
1

+ICH_V5REF_SUS Vcc1_5_B[35] Vcc3_3[13] VSS[43] VSS[140]


R22 Vcc1_5_B[36] Vcc3_3[14] B16 1 1 1 H24 VSS[44] VSS[141] AA25
2 R23 Vcc1_5_B[37] Vcc3_3[15] B7 H27 VSS[45] VSS[142] AA26

C804

C805

C806
C159 R24 C10 H28 AB4
Vcc1_5_B[38] Vcc3_3[16] VSS[46] VSS[143]
R25 Vcc1_5_B[39] Vcc3_3[17] D15 J1 VSS[47] VSS[144] AB6
0.1U_0402_16V4Z R26 F9 2 2 2 J2 AB11
1 +3VS Vcc1_5_B[40] Vcc3_3[18] VSS[48] VSS[145]
T22 G11 J5 AB14
Vcc1_5_B[41] Vcc3_3[19] VSS[49] VSS[146]
T23
Vcc1_5_B[42] Vcc3_3[20]
G12 2005/09/12 J24
VSS[50] VSS[147]
AB16
T26 G16 J25 AB19
Vcc1_5_B[43] Vcc3_3[21] VSS[51] VSS[148]
T27 J26 AB21
Vcc1_5_B[44] VSS[52] VSS[149]
1 T28 W5 +RTCVCC K24 AB24
C807 Vcc1_5_B[45] VccRTC VSS[53] VSS[150]
U22 K27 AB27
Vcc1_5_B[46] VSS[54] VSS[151]

0.1U_0402_16V4Z

1U_0402_6.3V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3V K28 VSS[55] VSS[152] AB28
0.1U_0402_16V4Z V22 1 1 1 1 L13 AC2
2 Vcc1_5_B[48] VSS[56] VSS[153]

C810

C811
V23 A24 C808 C809 L15 AC5
Vcc1_5_B[49] VccSus3_3[2] VSS[57] VSS[154]
W22 C24 L24 AC9
Vcc1_5_B[50] VccSus3_3[3] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[58] VSS[155]
W23 D19 L25 AC11
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[59] VSS[156]
Y22 D22 L26 AD1
Vcc1_5_B[52] VccSus3_3[5] VSS[60] VSS[157]
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 M3 VSS[61] VSS[158] AD3
M4 VSS[62] VSS[159] AD4
+1.5VS R664 +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 K3 M5 AD7
0.5_0603_1% R665 Vcc3_3[1] VccSus3_3[7] +3V VSS[63] VSS[160]
K4 1 1 M12 AD8
VccSus3_3[8] VSS[64] VSS[161]
0.01U_0402_16V7K

1 2 1 2 +1.5VS_DMIPLL AG28 K5 C812 C813 M13 AD11


VccDMIPLL VccSus3_3[9] VSS[65] VSS[162]
10U_0805_10V4Z

VccSus3_3[10] K6 M14 VSS[66] VSS[163] AD15


0_0603_5% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M15 AD19
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[67] VSS[164]
C814

AC6 L2 M16 AD23


Vcc1_5_A[2] VccSus3_3[12] VSS[68] VSS[165]
C815

AC7 L3 M17 AE2


Vcc1_5_A[3] VccSus3_3[13] VSS[69] VSS[166]
1 AD6 L6 M24 AE4
2 2 C816 Vcc1_5_A[4] VccSus3_3[14] VSS[70] VSS[167]
AE6 L7 M27 AE8
B Vcc1_5_A[5] VccSus3_3[15] VSS[71] VSS[168] B
AF5 M6 M28 AE11
0.1U_0402_16V4Z Vcc1_5_A[6] VccSus3_3[16] VSS[72] VSS[169]
AF6 M7 N1 AE13
2 Vcc1_5_A[7] VccSus3_3[17] VSS[73] VSS[170]
AG5 N7 N2 AE18
Vcc1_5_A[8] VccSus3_3[18] VSS[74] VSS[171]
AH5 N5 AE21
Vcc1_5_A[9] VSS[75] VSS[172]
Vcc1_5_A[19] AB17 +1.5VS N6 VSS[76] VSS[173] AE24
+1.5VS Place closely pin AG5. AD2
VccSATAPLL Vcc1_5_A[20]
AC17 N11
VSS[77] VSS[174]
AE25
0.1U_0402_16V4Z

N12 AF2
VSS[78] VSS[175]
+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N13 VSS[79] VSS[176] AF4
<BOM Structure>
0.1U_0402_16V4Z

1 F17 N14 AF8


Vcc1_5_A[22] VSS[80] VSS[177]
C817

1 AB10 G17 N15 AF11


+1.5VS Vcc1_5_A[10] Vcc1_5_A[23] VSS[81] VSS[178]
C818

AB9 N16 AF27


Vcc1_5_A[11] VSS[82] VSS[179]
1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N17 VSS[83] VSS[180] AF28
2 C820 AD10 Vcc1_5_A[13] Vcc1_5_A[25] AC8 N18 VSS[84] VSS[181] AG1
2 C819 0.1U_0402_16V4Z
AE10 N24 AG3
1U_0603_10V4Z Vcc1_5_A[14] ICH_K7 VSS[85] VSS[182]
AF10 K7 PAD T32 N25 AG7
2 Vcc1_5_A[15] VccSus1_05[1] VSS[86] VSS[183]
AF9 Vcc1_5_A[16] N26 VSS[87] VSS[184] AG11
AG9 C28 ICH_C28 PAD P3 AG14
Vcc1_5_A[17] VccSus1_05[2] T33 VSS[88] VSS[185]
AH9 G20 ICH_G20 PAD P4 AG17
Vcc1_5_A[18] VccSus1_05[3] T34 VSS[89] VSS[186]
P12 VSS[90] VSS[187] AG20
+3V Place closely pin AG9. E3
VccSus3_3[19] Vcc1_5_A[26]
A1 +1.5VS P13
VSS[91] VSS[188]
AG25
1 Vcc1_5_A[27] H6 P14 VSS[92] VSS[189] AH1
C821 C1 H7 1 P15 AH3
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[93] VSS[190]
1 J6 C823 P16 AH7
0.1U_0402_16V4Z C822 ICH_AA2 Vcc1_5_A[29] VSS[94] VSS[191]
T35 PAD AA2 J7 P17 AH12
2 ICH_Y7 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] 0.1U_0402_16V4Z VSS[95] VSS[192]
T36 PAD Y7 P24 AH23
0.1U_0402_16V4Z VccSus1_05/VccLAN1_05[2] 2 VSS[96] VSS[193]
P27 AH27
2 VSS[97] VSS[194]
V5
VccSus3_3/VccLAN3_3[1] ICH7_BGA652~D
V1 VccSus3_3/VccLAN3_3[2]
W2
VccSus3_3/VccLAN3_3[3]
+3V W7 VccSus3_3/VccLAN3_3[4]
A A

1 ICH7_BGA652~D
C824

0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7M(4/4)-POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 21 of 44
5 4 3 2 1
A B C D E F G H

+5VS
Placea caps. near ODD CONN.

0.1U_0402_16V4Z 10U_0805_10V4Z

1 1 1 1 1
C197 C184 C194
+3VS
C183 C192
2 2 2 2 2 IDE_DD[0..15] C239
1 19 IDE_DD[0..15] 1
1 2 0.1U_0402_16V4Z
1000P_0402_50V7K 1U_0402_6.3V4Z 10U_0805_10V4Z IDE_DA[0..2]
19 IDE_DA[0..2]

5
U7
IDE_HRESET# 2

P
20 IDE_HRESET# B
4 IDE_RST#
PLT_RST# Y
6,18,20,24,28 PLT_RST# 1
A

G
NC7SZ08P5X_NL_SC70-5

3
JP25
1 2
3 4
IDE_RST# 5 6 IDE_DD8
IDE_DD7 7 8 IDE_DD9
IDE_DD6 9 10 IDE_DD10
IDE_DD5 11 12 IDE_DD11
IDE_DD4 13 14 IDE_DD12
IDE_DD3 15 16 IDE_DD13
IDE_DD2 17 18 IDE_DD14
IDE_DD1 19 20 IDE_DD15
IDE_DD0 21 22 IDE_DDREQ
IDE_DIOR# IDE_DDREQ 19
23 24 IDE_DIOR# 19
IDE_DIOW# 25 26
19 IDE_DIOW#
IDE_DIORDY 27 28 IDE_DDACK#
19 IDE_DIORDY IDE_IRQ IDE_DDACK# 19
19 IDE_IRQ 29 30
IDE_DA1 31 32 IDE_PDIAG# 1 2 R200 +5VS
IDE_DA0 33 34 IDE_DA2 100K_0402_5%
IDE_DCS1# 35 36 IDE_DCS3#
19 IDE_DCS1# IDE_DCS3# 19
IDE_LED# 37 38
28 IDE_LED#
+5VS 39 40 +5VS
2 2
41 42
43 44
45 46
1 2 IDE_CSEL 47 48
R169 475_0402_1% 49 50
51 52 +5VS

OCTEK_CDR-50JD1 0.1U_0402_16V4Z
CONN@
+3VS
IDE_CSEL 1
C196
1
C182
1
C193
Grounding for Master (When use SATA HDD) 1
Open or High for Slaver (Normal) C245
2 1 IDE_LED# 2 2 2
+5VS
R185 100K_0402_5% 0.1U_0402_16V4Z
1000P_0402_50V7K 1U_0402_6.3V4Z 2

SATA HDD Conn.(SAS Connector)


JP27
1 GND
SATA_ITX_C_DRX_P0 2
19 SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 HTX0+
3
19 SATA_ITX_C_DRX_N0 HTX0-
SATA_DTX_IRX_N0
4
GND First HDD for 15.4"
5
SATA_DTX_IRX_P0 HRX0-
6
3 HRX0+ 3
7 GND
SATA_DTX_C_IRX_N0 1 2 SATA_DTX_IRX_N0
19 SATA_DTX_C_IRX_N0
C566 3900P_0402_50V7K
23 GND
19 SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 1 2 SATA_DTX_IRX_P0 SATA_ITX_C_DRX_P1 24
C562 3900P_0402_50V7K 19 SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1 HTX1+
25
19 SATA_ITX_C_DRX_N1 HTX1-
SATA_DTX_IRX_N1
26
GND 2nd HDD for 17"
27
SATA_DTX_IRX_P1 HRX1-
28
SATA_DTX_C_IRX_P1 SATA_DTX_IRX_P1 HRX1+
19 SATA_DTX_C_IRX_P1 1 2 29 GND
SATAX2@ C541 3900P_0402_50V7K

SATA_DTX_C_IRX_N1 1 2 SATA_DTX_IRX_N1
19 SATA_DTX_C_IRX_N1
SATAX2@ C539 3900P_0402_50V7K 8
+3VS VCC3.3
9 VCC3.3
10
VCC3.3
11
GND
12
GND
13
GND
+5VS 14
VCC5
15
VCC5
16 VCC5
17
GND
18 RESERVED
19
GND
20
VCC12
21 VCC12
22
VCC12

30 GND1
4 4
31
GND2

OCTEK_SAS-22CA1G
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 22 of 44
A B C D E F G H
A B C D E

PS: only below need to pull high


others have internal Pull high
+3VS
40mil pin 118 XD SMRE#
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z pin 7 XD SMWE#
1
U46 1 1 1 1 1 1 1 1
pin 111 XD BSY# 1

C874 C875 C876 C877 C878 C879 C880 C881 pin 21 XD CE#
PCI_AD31 18 125
PCI_AD30 AD31 PMPWR_VCC 2 2 2 2 2 2 2 2
19 120
PCI_AD29
PCI_AD28
20
22
AD30
AD29
MR510 VCC8
VCC7 101
81 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCI_AD[0..31] PCI_AD27 AD28 VCC6
18 PCI_AD[0..31] 23 AD27 VCC5 69
PCI_AD26 24 52
PCI_CBE#[0..3] PCI_AD25 AD26 VCC4
18 PCI_CBE#[0..3] 25 AD25 VCC3 42
PCI_AD24 26 29
PCI_AD23 AD24 VCC2
33 AD23 NC24 11
PCI_AD22 34 113 +3V_MCVCC
PCI_AD21 AD22 VCC_SD2
35 AD21 VCC_SD1 10 1 1
PCI_AD20 36 1 R722 43K_0402_5%
2 +3VS 0.1U_0402_16V4Z C873 C882
PCI_AD19 AD20 0.1U_0402_16V4Z
39 AD19
PCI_AD18 40 127 R696 1 @ 2 0_0402_5% SD_PW REN#
PCI_AD17 AD18 PMPWR_ENI# 2 2
46 AD17 PMPWR_OUT 126
CLK_PCI_card CLK_48M_SD PCI_AD16 47
PCI_AD15 AD16
65 AD15
1

PCI_AD14 66 104 PCI_RST# xD PU and PD. Close to Socket


R695 R698 PCI_AD13 AD14 GRST#
67 AD13
@ 10_0402_5% @ 10_0402_5% PCI_AD12 68
PCI_AD11 AD12 MS_INS# MS_INS#
70 AD11 MSINS# 90 1 R700 43K_0402_5%
2 +3VS
PCI_AD10 71 95 MSSMXD_PW REN#
2

PCI_AD9 AD10 MSPWREN#/SMPWREN# xDDATA1/MSBS


1 1 72 AD9 MSBS/SMDATA1 96
C883 C884 PCI_AD8 73 xDDATA1/MSBS 1 R703 43K_0402_5%
2 MS signal
PCI_AD7 AD8
82 AD7
2 @ 15P_0402_50V8J @ 15P_0402_50V8J PCI_AD6 83 115 xDDATA2/MSDATA0 xDDATA2/MSDATA0 1 R704 43K_0402_5%
2 2
2 2 PCI_AD5 AD6 MSDATA0/SMDATA2 xDDATA6/MSDATAT1 xDDATA6/MSDATAT1 R705 43K_0402_5% +3VS
84 AD5 MSDATA1/SMDATA6 114 1 2
PCI_AD4 85 116 xDDATA5/MSDADTA2 xDDATA5/MSDADTA2 1 R706 43K_0402_5%
2
PCI_AD3
PCI_AD2
86
87
AD4
AD3
MSDATA2/SMDATA5
MSDATA3/SMDATA3 117 xDDATA3/MSDADTA3 xDDATA3/MSDADTA3 1 R707 43K_0402_5%
2 Memory Card Power Switch
PCI_AD1 AD2 R708 2xDSMRE#/MSCLK xDSMRE#/MSCLK +3V_MCVCC
88 AD1 MSCLK/SMRE# 118 1 1 R709 43K_0402_5%
2 +3V_MCVCC

2
PCI_AD0 91 22_0402_1% U47 40mil

8.2K_0402_5%
AD0 XMDAT4B XMDAT4B R710 43K_0402_5%
MMDAT4 99 1 2 1
GND OUT 8
112 XMDAT5B/XDW PO# xDSMW E#/SDCLK 1 R711 43K_0402_5%
2 R702 2 7
MMDAT5/SMWP# IN OUT

1
PCI_CBE#0 74 111 XMDAT6B_XDBSY# XMDAT6B_XDBSY# 1 R712 43K_0402_5%
2 3 6 C885 1 C886 1 C887 1
PCI_CBE#1 C/BE0# MMDAT6/SMBAY# XMDAT7B_XDCe# XMDAT7B_XDCe# R713 43K_0402_5% MC_PW REN# IN OUT R714
60 98 1 2 4 5

1
PCI_CBE#2 C/BE1# MMDAT7/SMCE# EN# FLG 150K_0402_5%
48 C/BE2# xd signal 1

1
PCI_CBE#3 27 C890 TPS2061DRG4_SO8 4.7U_0805_10V4Z
0.1U_0402_16V4Z @
C/BE3# xDDATA4/SDDAT3 xDDATA4/SDDAT3 R715 43K_0402_5% @ R716 2 2 2
5 1 2

2
SDDAT3/SMDATA4 xDCLE/SDDAT2 xDCLE/SDDAT2 R717 43K_0402_5% 0.1U_0402_16V4Z SDOC# 300_0603_5% 0.1U_0402_16V4Z
18 PCI_GNT#0 17 PCIGNT# SDDAT2/SMCLE 4 1 2
xDDATA0/SDDAT1 xDDATA0/SDDAT1 R718 43K_0402_5% 2
18 PCI_REQ#0 16 PCIREQ# SDDAT1/SMDATA0 9 1 2
18 PCI_PAR 59 8 xDDATA7/SDDAT0 xDDATA7/SDDAT0 1 R719 43K_0402_5%
2

1 2
PAR SDDAT0/SMDATA7 xDALE/SDCMD xDALE/SDCMD R720 43K_0402_5%
18 PCI_SERR# 58 SERR# SDCMD/SMALE 6 1 2 D
18 PCI_PERR# 57 7 1 R721 2xDSMW E#/SDCLK
PERR# SDCLK/SMWE# 22_0402_1% MSSMXD_PW REN# R699 20_0402_5%
MC_PW REN#2 Q55
18 PCI_STOP# 56 STOP# SD signal 1
SD_PW REN# 1 G 2N7002_SOT23
18 PCI_DEVSEL# 55 DEVSEL# SDCLKI 41 CLK_48M_SD 14 2
18 PCI_TRDY# 54 R701 0_0402_5% S

3
TRDY#
18 PCI_IRDY# 53 IRDY#
18 PCI_FRAME# 49 1 SD_PW REN#
FRAME# SDPWREN33# SMW PD#/SDW P
18,26,27 PCI_RST# 37 PCIRST# SDWP/SMWPD# 121 1 R723 43K_0402_5%
2 +3VS
38 122 SDCD# 1 R724 43K_0402_5%
2
14 CLK_PCI_Card PCICLK SDCD#
89 xDSMCD# R725 1 2 8.2K_0402_5%

PCI_AD16
R726 100_0402_5%
1 2 28
SMCD#
4 IN 1 Socket Push Type(New)
3 IDSEL 3
+3VS 2 R727 1 10K_0402_5%
GND_SD1 3
109 xD PU and PD. Close to Socket JP30
GND_SD2
27,28,30,34,40 SUSP# 2 @ R728 1 0_0402_5% 108 SUSPEND# NC23 12 +3V_MCVCC 33 XD-VCC SD-VCC 23 +3V_MCVCC
+3VS 1 2 93 RIOUT#_PME# GND7 119 MS-VCC 14
R73143K_0402_5% 97 xDDATA0/SDDAT1 8
R732 1 GND6 xDDATA1/MSBS XD-D0 xDSMW E#/SDCLK
+3VS 2 GND5 92 9 XD-D1 4 IN 1 CONN SD_CLK 24
10K_0402_5% 110 80 xDDATA2/MSDATA0 26 25 xDDATA7/SDDAT0
SDOC# MFUNC7 GND4 xDDATA3/MSDADTA3 XD-D2 SD-DAT0 xDDATA0/SDDAT1
107 MFUNC6 GND3 61 27 XD-D3 SD-DAT1 29
5IN1_LED# 106 43 xDDATA4/SDDAT3 28 10 xDCLE/SDDAT2
28 5IN1_LED# MFUNC5 GND2 XD-D4 SD-DAT2
R729 1 10K_0402_5%
2 105 21 xDDATA5/MSDADTA2 30 11 xDDATA4/SDDAT3
MFUNC4 GND1 xDDATA6/MSDATAT1 XD-D5 SD-DAT3 xDALE/SDCMD
103 MFUNC3 31 XD-D6 SD-CMD 12
102 xDDATA7/SDDAT0 32 36 SDCD#
R730 1 10K_0402_5% MFUNC2 XD-D7 SD-CD-SW
2 100 MFUNC1
94 xDSMW E#/SDCLK 6 35 SMW PD#/SDW P
18 PCI_PIRQE# MFUNC0 XD-WE SD-WP-SW
128 XMDAT5B/XDW PO# 7
NC22 xDALE/SDCMD XD-WP
NC21 124 5 XD-ALE
2 123 xDSMCD# 34 15 xDSMRE#/MSCLK
NC1 NC20 XMDAT6B_XDBSY# XD-CD MS-SCLK xDDATA2/MSDATA0
13 NC2 NC19 79 1 XD-R/B MS-DATA0 19
14 78 xDSMRE#/MSCLK 2 20 xDDATA6/MSDATAT1
NC3 NC18 XMDAT7B_XDCe# XD-RE MS-DATA1 xDDATA5/MSDADTA2
MFUN0 15 NC4 NC17 77 3 XD-CE MS-DATA2 18
30 76 xDCLE/SDDAT2 4 16 xDDATA3/MSDADTA3
NC5 NC16 XD-CLE MS-DATA3
MFUN1 w/o eerom pull low 31 NC6 NC15 75 MS-INS 17 MS_INS#
32 64 Reserve for SD,MS CLK. 13 21 xDDATA1/MSBS
NC7 NC14 4IN1 GND MS-BS
MFUN2 44 NC8 NC13 63 22 4IN1 GND
45 62 Close to Socket
NC9 NC12
MFUN3 50 NC10 NC11 51
xDSMW E#/SDCLK 1 2
MFUN4 w/o eerom pull low C888 10P_0402_50V8K 37 4IN1 GND
4 38 4IN1 GND 4
MFUN5 xDSMRE#/MSCLK 1 2
MR510QFA1_LQFP128_14X14 C889 10P_0402_50V8K TAITW _R015-312-LM
MFUN6 CONN@

MFUN7
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R5C833 5IN1 & IEEE1394
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 23 of 44
A B C D E
5 4 3 2 1

+3VALW
U35 60mil
+3V_LAN +3V_LAN
+3V_LAN R23 1 2 1_1206_1%

+3V_LAN_R
60mil LAN BCM5787M
8 1 R24 1 2 1_1206_1%
D S
1 7 D S 2 1 1 1 1
C24 6 3 1 1 1 1 C28 C30 C25 C26
D S

3
5 4 C29 C58 C89 C111
4.7U_0805_10V4Z D G 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 AO4468_SO8 4.7U_0805_10V4Z 0.1U_0402_16V4Z LAN_REGCTL25 1 2 2 LAN_REGCTL12 1 2 2
@ 2 2 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z Q18 +2.5V_LAN Q6 +1.2V_LAN
+VSB 2 13VLAN_GATE MMJT9435T1G_SOT223 20mil MMJT9435T1G_SOT223 60mil

2
4

2
4
@ R508
200K_0402_5% 1
D C634 D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1
D @ C447 C52 C449 C110 C31 C448 C80 C42 C91 C112 C39 C457 C450 C41 C464
2 0.1U_0603_25V7K
26,27,34 SYSON# 2
G 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
Q40 S @ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3
2N7002_SOT23 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+3V_LAN

+3VALW 1 2 +3V_LAN
R19 0_1206_5% U3
SPROM_DOUT 1 8 SPROM_DIN
SPROM_CLK SI SO
2 SCK GND 7
3 6 +3V_LAN
SPROM_CS RESET# VCC
4 CS# WP# 5 1
C114
AT45DB011B-SU_SO8 0.1U_0402_16V4Z
U2 @ @
41 LAN_MIDI0- 2
TRD0_N LAN_MIDI0+ LAN_MIDI0- 25
14 CLK_PCIE_LAN# 28 PCIE_REFCLK_N TRD0_P 40
LAN_MIDI1- LAN_MIDI0+ 25 Use Flash if support ASF2.0
42 LAN_MIDI1- 25
TRD1_N LAN_MIDI1+
14 CLK_PCIE_LAN 29 PCIE_REFCLK_P TRD1_P 43 LAN_MIDI1+ 25
48 LAN_MIDI2- +3V_LAN +3V_LAN
TRD2_N LAN_MIDI2+ LAN_MIDI2- 25
R741 0_0402_5% 11 47 +3V_LAN
CLKREQ TRD2_P LAN_MIDI2+ 25
28 LAN_LOWPWR 1 2 49 LAN_MIDI3- 1
TRD3_N LAN_MIDI3- 25
50 LAN_MIDI3+ C136
TRD3_P LAN_MIDI3+ 25

2
R71 1 2 10K_0402_5% 3 0.1U_0402_16V4Z R128 R102
C @ LOW PWR R748 0_0402_5% 2 C
4.7K_0402_5% 4.7K_0402_5%
+3VS R88 1 2 1K_0402_5% 53 2 1 2 U4
VMAIN_PRSNT LINKLED LAN_LINK# 25
1 1 8

1
R89 SPD100LED A0 VCC SPROM_WP
+3V_LAN 1 2 1K_0402_5% 54 VAUX_PRSNT SPD1000LED 67 R747 0_0402_5% 2 A1 WP 7
+3V_LAN 2 1 LAN_PME# TRAFFICLED 66 1 2 3 A2 SCL 6 SPROM_CLK
R514 LAN_ACTIVITY# 25 SPROM_DOUT
4 5
100K_0402_5% GND SDA
59 65 SPROM_CLK @ AT24C64AN-10SU-2.7_SO8
28 ENERGY_DET ENERGY_DET SCLK(EECLK)

2
63 SPROM_DIN R78 1 2 4.7K_0402_5%
+LAN_GPHYPLLVDD SI SPROM_DOUT R740
35 64
GPHY_PLLVDD SO(EEDATA) SPROM_CS R77
CS 62 1 2 4.7K_0402_5% 4.7K_0402_5%
PCIE_ITX_C_PRX_N3 32 Change to SA000003510(AT24C64) @
20 PCIE_ITX_C_PRX_N3 PCIE_RXD_N

1
PCIE_ITX_C_PRX_P3 31 Unpop if use Flash
20 PCIE_ITX_C_PRX_P3 PCIE_RXD_P LAN_REGCTL12
14
C38 PCIE_PTX_IRX_N3 REGCTL12 LAN_REGCTL25
20 PCIE_PTX_C_IRX_N3 1 2 0.1U_0402_16V7K 25 18
PCIE_TXD_N REGCTL25 LAN_RDAC
PCIE_PTX_IRX_P3 RDAC
37 1 2 Unpop if use Flash
20 PCIE_PTX_C_IRX_P3 C37 1 2 0.1U_0402_16V7K 26 R62 1K for BCM5906M
PCIE_TXD_P 1.24K_0402_1%
20mil L7 20mil
23 +LAN_XTALVDD 1 2 L33
XTALVDD +2.5V_LAN
R67 1 2 0_0402_5% LAN_RESET# 10 6 +3V_LAN BLM18AG601SN1D_0603 +LAN_PCIEPLLVDD 1 2 +1.2V_LAN
6,18,20,22,28 PLT_RST# PERST VDDIO
15 1 1 1 BLM18AG601SN1D_0603
R66 1 0_0402_5% LAN_PME# VDDIO
20,26,27 ICH_PCIE_WAKE# 2 @ 12 19 C43 C452 C451
R511 1 0_0402_5% WAKE VDDIO 0.1U_0402_16V4Z
28 EC_PME# 2 56
VDDIO 0.1U_0402_16V4Z
61
VDDIO 2 2 2
LAN_SMBCLK 58 17 4.7U_0805_10V4Z
SMB_CLK VDDP +2.5V_LAN
68
+3V_LAN LAN_SMBDATA VDDP
R130
57
SMB_DATA 20mil L34
5 +1.2V_LAN
4.7K_0402_5% VDDC +LAN_PCIEVDD
13 1 2 +1.2V_LAN
VDDC
2

B BLM18AG601SN1D_0603 B
G

1 2 +3V_LAN pull-up to +3V on South Bridge Side VDDC 20 1 1


4 34 C455 C454
LAN_SMBDATA GPIO_0(SERIAL_DO) VDDC
14,20,26,27 ICH_SMBDATA 1 3 55
SPROM_WP VDDC 0.1U_0402_16V4Z
7 60
D

Q41 GPIO_1(SERIAL_DI) VDDC L8 2 2


+LAN_BIASVDD
20mil
@ 2N7002_SOT23 8 36 1 2 +2.5V_LAN 4.7U_0805_10V4Z
GPIO_2 BIASVDD +LAN_PCIEPLLVDD BLM18AG601SN1D_0603
30
PCIE_PLLVDD +LAN_PCIEVDD
9
UART_MODE PCIE_VDD
27 1
C53
20mil L36
33
+3V_LAN PCIE_VDD 0.1U_0402_16V4Z +LAN_AVDD 1 2 +2.5V_LAN
R64 38 +LAN_AVDD 1 1 BLM18AG601SN1D_0603
4.7K_0402_5% LAN_XTALI AVDD 2 C107 C88
21 45
XTALI AVDD
2
G

1 2 +3V_LAN AVDD 52
XTALO 22 0.1U_0402_16V4Z
LAN_SMBCLK XTALO +LAN_AVDDL 2 2
14,20,26,27 ICH_SMBCLK 1 3 AVDDL 39
1

44 0.1U_0402_16V4Z
D

Q42 R48 AVDDL


16 46
@ 2N7002_SOT23 REG_GND AVDDL
200_0402_1% AVDDL
51 20mil L37
24 69
PCIE_GND EXPOSED PAD +LAN_AVDDL 1 2 +1.2V_LAN
2

Y2 BCM5787MKML_QFN68 1 1 BLM18AG601SN1D_0603
1 2 LAN_XTALO C95 C463

1 25MHZ_20P 1 0.1U_0402_16V4Z
2 2
C35 C34 4.7U_0805_10V4Z
27P_0402_50V8J 27P_0402_50V8J
2 2
20mil L35
+LAN_GPHYPLLVDD 1 2 +1.2V_LAN
1 1 BLM18AG601SN1D_0603
C453 C456
A A
0.1U_0402_16V4Z
2 2
4.7U_0805_10V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/12/25 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN BCM5787M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 24 of 44
5 4 3 2 1
5 4 3 2 1

LAN_LINK# LAN_ACTIVITY#

LAN BCM5787M

3
@ @
PSOT24C-LF-T7_SOT23-3 PSOT24C-LF-T7_SOT23-3
D30 D31

1
D D

1 2

C94
+2.5V_LAN 220P_0402_50V7K
JP18
+3V_LAN 2 1 12 Amber LED+

2
R70 1K_0402_5%
L12 LAN_ACTIVITY# 11
24 LAN_ACTIVITY# Amber LED-
BLM18AG601SN1D_0603 SHLD2 16
RJ45_MIDI3- 8 Guide Pin
PR4-
SHLD1 15
RJ45_MIDI3+ 7

1
T4 PR4+
1 24 RJ45_MIDI1- 6
LAN_MIDI0+ TCT1 MCT1 RJ45_MIDI0+ PR2-
24 LAN_MIDI0+ 2 TD1+ MX1+ 23
24 LAN_MIDI0- LAN_MIDI0- 3 22 RJ45_MIDI0- RJ45_MIDI2- 5
TD1- MX1- PR3-
4 TCT2 MCT2 21
24 LAN_MIDI1+ LAN_MIDI1+ 5 20 RJ45_MIDI1+ RJ45_MIDI2+ 4
LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1- PR3+
24 LAN_MIDI1- 6 TD2- MX2- 19
7 18 RJ45_MIDI1+ 3
LAN_MIDI2+ TCT3 MCT3 RJ45_MIDI2+ PR2+
24 LAN_MIDI2+ 8 TD3+ MX3+ 17
24 LAN_MIDI2- LAN_MIDI2- 9 16 RJ45_MIDI2- RJ45_MIDI0- 2
C TD3- MX3- PR1- C
10 TCT4 MCT4 15 SHLD2 14
24 LAN_MIDI3+ LAN_MIDI3+ 11 14 RJ45_MIDI3+ RJ45_MIDI0+ 1
LAN_MIDI3- TD4+ MX4+ RJ45_MIDI3- PR1+
24 LAN_MIDI3- 12 TD4- MX4- 13 SHLD1 13
LAN_LINK# 10
350uH_GSL5009LF 24 LAN_LINK# Green LED-

+3V_LAN 2 1 9 Green LED+


R154 1K_0402_5%
1

R129 R118 FOX_JM36113-L2R8-7F


49.9_0402_1% 49.9_0402_1% CONN@

1
R152 R148 @ @ 1 2
49.9_0402_1% 49.9_0402_1%
@ @ R101 R115 C151
2

75_0402_1% 75_0402_1% 220P_0402_50V7K


0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
1 1
C146 C134 1 1 1 1 R132 R153 RJ45_GND 1 2 LANGND 40mil
0.1U_0402_16V4Z 0.1U_0402_16V4Z C138 C121 C152 C106 75_0402_1% 75_0402_1% 1 1
@ 2 @ 2 C154

2
1000P_1206_2KV7K C108 C96
2 2 2 2 RJ45_GND 4.7U_0805_10V4Z
2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 40mil
Pop for BCM5906 0.1U_0402_16V4Z

B Place close to TCT pin B


LAN_ACTIVITY# 1 2
C186
220P_0402_50V7K
@

LAN_LINK# 1 2
C187
220P_0402_50V7K
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/12/25 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45/RJ11
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 25 of 44
5 4 3 2 1
A B C D E

For Wireless LAN


+3VS_WL +1.5VS +3VAux_WL

1 1 1 1 1 1 1 1
C906 C139 C480 C147 C140 C133 C137 C907

10U_0805_6.3V6M 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_6.3V6M


2 2 2 2 2 2 2 2

1 1

R755 @ 0_0402_5% JP21


ICH_PCIE_WAKE# 1 2 1 2 +3VS_WL
20,24,27 ICH_PCIE_WAKE# WLAN_BT_DATA 1 2
27 WLAN_BT_DATA 3 4
WLAN_BT_CLK 3 4
27 WLAN_BT_CLK 5 5 6 6 +1.5VS
14 MINI1_CLKREQ# 7 8
7 8
9 9 10 10
14 CLK_PCIE_MINI1# 11 11 12 12
13 14
14 CLK_PCIE_MINI1
15
13
15
14
16 16 LPC Debug Port
17 18 +5VS +3VS
17 18 WL_OFF#
19 20 WL_OFF# 28
19 20 PLT_RST_BUF#
21 22 PLT_RST_BUF# 18
21 22
20 PCIE_PTX_C_IRX_N4 23 23 24 24 +3VAux_WL
25 26 JP40
20 PCIE_PTX_C_IRX_P4 25 26
27 27 28 28 1 1
29 30 ICH_SMBCLK ICH_SMBCLK 14,20,24,27 2
29 30 ICH_SMBDATA 2
20 PCIE_ITX_C_PRX_N4 31 32 ICH_SMBDATA 14,20,24,27 3
31 32 3
20 PCIE_ITX_C_PRX_P4 33 34 4
33 34 4
35 35 36 36 USB20_N7 20 5 5
37 38 6 CLK_14M_SIO
37 38 USB20_P7 20 6 LPC_AD0 CLK_14M_Dbg 14
+3VS_WL 39 40 7 LPC_AD0 19,28
39 40 7 LPC_AD1
41 42 (MINI1_LED#) 8 LPC_AD1 19,28
41 42 8 LPC_AD2
43 44 MINI1_LED# 29 9 LPC_AD2 19,28
43 44 9 LPC_AD3
45 46 10 LPC_AD3 19,28
45 46 10 LPC_FRAME#
E51TXD_P80DATA
47
49
47 48 48
50
(9~16mA) 11 11
12 LPC_DRQ#1
LPC_FRAME# 19,28
28 E51TXD_P80DATA E51RXD_P80CLK 49 50 12 PCI_RST# LPC_DRQ#1 19
28 E51RXD_P80CLK 51 52 13 PCI_RST# 18,23,27
51 52 13
14 1 2
2 14 R690 @ 0_0402_5% CLK_PCI_Dbg 2
15
G1
G2
G3
G3

15 SIRQ CLK_PCI_Dbg 14
16
FOX_AS0B226-S99N-7F 16 SERIRQ 20,28
For MINICARD Port80 Debug 17
53
54
55
56

CONN@ 17
18 18
19
19
20
20 close to RAM Door
@ ACES_85201-2005
+3VS 1 @ 2 +3VAux_WL
Mini Card Power Rating R756 0_0805_5%
1 2 20 mil
+3V
Power Primary Power (mA) Auxiliary Power (mA) R757 0_0805_5%

Peak Normal Normal


+3VS 1000 750
+3VS 1 2 +3VS_WL
+3V 330 250 250 (wake enable) R758 0_1206_5%
1 2 40 mil
+3V
+1.5VS 500 375 5 (Not wake enable) R759 @ 0_1206_5%

To USB/B Connector

3 JP11 3

1 1 +5VALW
2 2
3 3 +5VALW
4 4
5
5 USB20_N4
6 6 USB20_P4 USB20_N4 20
7 7 USB20_P4 20
C368
1
8
8 USB20_N6
9 9 USB20_P6 USB20_N6 20
4.7U_0805_10V4Z
10 10 USB20_P6 20 2
11
11
12 12 SYSON# 24,27,34

13
GND1
14
GND2
ACES_87213-1200G
CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN & TV-Tuner)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 26 of 44
A B C D E
A B C D E

New Card Power Switch


New Card Socket (Left/TOP)
U16
+3VALW_CARD +3VS_CARD +1.5VS_CARD
60mils
+3VS 5 7 +3VS_CARD Imax = 0.275A Imax = 1.35A Imax = 0.75A JP9
3.3Vin1 3.3Vout1
6 8
3.3Vin2 3.3Vout2
1 GND
1 1 1 1 1 1 20 USB20_N1 2
C390 C387 C366 C367 C412 C401 USB_D-
1
40mil 20 USB20_P1 CP_USB#
3 USB_D+ 1
+3V 21 3.3Vaux_in Aux_out 20 +3VALW_CARD 4 CPUSB#
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 5
2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z RSV
40mil 6 RSV
+1.5VS 18 16 +1.5VS_CARD 14,20,24,26 ICH_SMBCLK 7
1.5Vin1 1.5Vout1 SMB_CLK
19 17 14,20,24,26 ICH_SMBDATA 8
1.5Vin2 1.5Vout2 SMB_DATA
+1.5VS_CARD 9 +1.5V
10
+1.5V
+3V R341 1 2 100K_0402_5% CP_USB# 14 CPUSB# 20,24,26 ICH_PCIE_WAKE# 11 WAKE#
R340 1 2 100K_0402_5% CP_PE# 15 CPPE# OC# 23 +3VALW_CARD 12 +3.3VAUX
SUSP# 4 PERST1# 13
23,28,30,34,40 SUSP# SYSON STBY# RCLKEN1 PERST#
28,34,40 SYSON 3 SHDN# RCLKEN 22 +3VS_CARD 14 +3.3V
PCI_RST# 2 9 PERST1# +3VS +3VS 15
18,23,26 PCI_RST# SYSRST# PERST# CLKREQ1# +3.3V
16 CLKREQ#
CP_PE# 17

GND
20 CP_PE#

NC1
NC2
NC3
NC4
NC5
CPPE#

1
+3VS 1 18
14 CLK_PCIE_CARD# REFCLK-
R336 C357 19
14 CLK_PCIE_CARD REFCLK+
TPS2231PWPR_PWP24 10K_0402_5% 20

11

1
10
12
13
24
GND

1
0.1U_0402_16V4Z 21
2 20 PCIE_PTX_C_IRX_N1 PERn0
R338 22
20 PCIE_PTX_C_IRX_P1

2
PERp0

5
10K_0402_5% U15 23
CLKREQ1# GND
2 24

G Vcc
B 20 PCIE_ITX_C_PRX_N1 PETn0
4 EXP_CLKREQ# 14 20 PCIE_ITX_C_PRX_P1 25

2
Y PETp0
1 A 26 GND

1
D NC7SZ32P5X_NL_SC70-5 27 29

3
RCLKEN1 2 Q15 GND GND
28 GND GND 30
G 2N7002_SOT23
+3VS +3V +1.5VS S FOX_1CH4110C_LT

3
CONN@

1 1 1
C363 C362 C365
2 2
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
2 2 2

USB CONN. (Stack-up Type)


Bluetooth Conn.
+USB_VCCA

+USB_VCCA
W=80mils
D12
+3VALW +3VS 1 4
1 GND VCC +USB_VCCA
1 1
C173 + C164 C167
USB20_P0_R 2 3 USB20_N0_R
150U_Y_6.3VM I/O I/O
1 <BOM Structure> 470P_0402_50V7K
C592 C600 2 2 2 @ PRTR5V0U2X_SOT143
470P_0402_50V7K
0.1U_0402_16V4Z 1U_0603_10V4Z JP23
3

2
S
R733 0_0402_5% 1
G
USB20_N2 1 VCC
28 BT_ON# 1 2 2 Q32
20 USB20_N2 2 USB20_N2_R 2 D11
3 USB20_P2 1 D0- 3
R482 10K_0402_5% AO3413_SOT23-3
20 USB20_P2 2 USB20_P2_R 3 D0+ 1 GND VCC 4 +USB_VCCA
D R734 0_0402_5% 4
1

GND
C597 W=40mils R736 0_0402_5% 5 USB20_P2_R 2 3 USB20_N2_R
USB20_N0 1 VCC I/O I/O
+BT_VCC 20 USB20_N0 2 USB20_N0_R 6
USB20_P0 1 D1-
0.1U_0402_16V4Z
20 USB20_P0 2 USB20_P0_R 7 @ PRTR5V0U2X_SOT143
D1+
1 8
GND
1

C590 C598 R735 0_0402_5%


R492 9
4.7U_0805_10V4Z 300_0603_5% GND1
10 GND2
2 0.1U_0402_16V4Z
SUYIN_020122MR008S505ZL
BT_LED# 28,29
2

+BT_VCC CONN@
+3V
1

D
2 Q34 80mil
1

G 2N7002_SOT23 R742 D
+5VALW

1
S 1 @ 22 @ Q51 +USB_VCCA
3

G 2N7002_SOT23 U6
10K_0402_5% S 1 8 R164
3

GND OUT 100K_0402_5%


2 7
IN OUT
3 6

2
+BT_VCC IN OUT R162 1
1 4 5 2 10K_0402_5% USB_OC#0 20
C171 EN# FLG
JP12 TPS2061DRG4_SO8
1 9 4.7U_0805_10V4Z R167 1 2 10K_0402_5%
1 GND 2 USB_OC#2 20
2 2 1
3 1 C161
20 USB20_P5 3
4 C169
20 USB20_N5 4
5 0.1U_0402_16V4Z
5 24,26,34 SYSON# 2
6 0.1U_0402_16V4Z
26 WLAN_BT_DATA 6 2
26 WLAN_BT_CLK 7 7
4 4
8 10
8 GND
ACES_87213-0800G
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD & USB Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 27 of 44
A B C D E
5 4 3 2 1

+3VALW For EC Tools


L46
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2+EC_VCCA +3VALW
1 1 C537 1 1 2 2 FBM-L11-160808-800LMT_0603 JP10
C560 1 KSI[0..7] 1
+3VALW KSI[0..7] 29 1
C552 C557 C536 C544 2 E51RXD_P80CLK
KSO[0..17] 2 E51RXD_P80CLK 26
1000P_0402_50V7K 1000P_0402_50V7K C559 3 E51TXD_P80DATA
2 2 2 2 1 1 KSO[0..17] 29 3 E51TXD_P80DATA 26
1 2 EC_PME# 4
R459 10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 4
@ ACES_85205-0400
@
D
+3VALW D
ECAGND JP35

111
125
22
33
96

67
1 1

9
U28 2 E51RXD_P80CLK
2 E51TXD_P80DATA
3

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
3
4 4

ACES_85205-0400
1 21 INVT_PW M @
19 EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PW M 16
2 23 BEEP#
19 EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 31
20,26 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 ENCODER_DIR 32
19,26 LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF 35,37
C555 LPC_AD3 5 2 1 ECAGND 3S/4S# 1 2
19,26 LPC_AD3 LAD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output C567 0.01U_0402_16V7K R521 4.7K_0402_5%
19,26 LPC_AD2 LAD2
2 1 R447 2 1 @ 33_0402_5% LPC_AD1 8 63 BATT_TEMP
19,26 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 38
LPC_AD0 BATT_OVP
19,26 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 37
ADP_I/AD2/GPIO3A 65 ADP_I 37
12 AD Input 66 AD_BID0
14 CLK_PCI_LPC PCICLK AD3/GPIO3B
6,18,20,22,24 PLT_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75 ENERGY_DET 24
37 ECRST# SELIO2#/AD5/GPIO43 76 POUT 42
EC_SCI# 20
20 EC_SCI# SCI#/GPIO0E +3VALW
+3VALW 2 1 20 PM_CLKRUN# 38 CLKRUN#/GPIO1D
R441 47K_0402_5% 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 16
2 1 70 EN_DFAN1 65W /90W # 2 1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 33
C548 0.1U_0402_16V4Z DA Output 71 IREF R449 100K_0402_5%
IREF/DA2/GPIO3E IREF 37
KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CHGSEL 37
+3VALW KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE 32
2

C KSI4 59 84 LAN_LOW PW R LAN_LOW PW R 24


C
R466 KSI5 KSI4/GPIO34 PSDAT1/GPIO4B W L_LED#
60 KSI5/GPIO35 PSCLK2/GPIO4C 85 W L_LED# 29
10K_0402_5% KSI6 61 PS2 Interface 86 BT_LED#
KSI6/GPIO36 PSDAT2/GPIO4D BT_LED# 27,29
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 29
KSO0 39 88 TP_DATA
TP_DATA 29
1

KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F


40 KSO1/GPIO21
KSO2 41
EC_RCIRRX KSO3 KSO2/GPIO22 3S/4S#
42 KSO3/GPIO23 SDICS#/GPXOA00 97 3S/4S# 37
KSO4 43 98 65W /90W #
KSO4/GPIO24 SDICLK/GPXOA01 65W /90W # 37
KSO5 SBPW R_EN
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 SBPW R_EN 34 Analog Board ID definition,
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109
KSO7 46 SPI Device Interface Please see page 3.
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119 EC_SI_SPI_SO
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 29
+5VS KSO10 49 120 EC_SO_SPI_SI +3VALW
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 29
KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK 29
KSO12 51 128 EC_SPICS#/FSEL#
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# 29

2
1 2 TP_CLK KSO13 52 KSO13/GPIO2D
R448 4.7K_0402_5% KSO14 53 R465
KSO14/GPIO2E
1 2 TP_DATA KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 EC_RCIRRX Ra @ 100K_0402_5%
R444 4.7K_0402_5% KSO16 81 74
KSO16/GPIO48 CIR_RLC_TX/GPIO41 ENCODER_PULSE 32
KSO17 82 89 FSTCHG
FSTCHG 37

1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_GRN_LED# AD_BID0
BATT_CHGI_LED#/GPIO52 90 BATT_GRN_LED# 29
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 29

2
EC_SMB_CK1 77 GPIO 92 BATT_AMB_LED# BATT_AMB_LED# 29 1
15,29,38 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54
EC_SMB_DA1 78 93 PW R_LED PW R_LED 29 R464 C565
15,29,38 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
+5VALW 4 EC_SMB_CK2
EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON
SYSON 27,34,40 Rb
EC_SMB_DA2 80 121 VR_ON 18K_0402_5%
4 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 42 2
127 0.1U_0402_16V4Z

1
B EC_SMB_CK1 AC_IN/GPIO59 ACIN 20,38 B
1 2
R460 4.7K_0402_5%
1 2 EC_SMB_DA1 PM_SLP_S3# 6 100
20 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 20
R458 4.7K_0402_5% PM_SLP_S5# 14 101 EC_LID_OUT#
20 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 20
1 2 EC_SMB_CK2 EC_SMI# 15 102 EC_ON EC_CRY1 EC_CRY2
20 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 30,37
R456 4.7K_0402_5% LID_SW # 16 103
29 LID_SW # LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SW I# 20
1 2 EC_SMB_DA2 SUSP# 17 104 EC_PW ROK 1 1
23,27,30,34,40 SUSP# SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PW ROK 30
R454 4.7K_0402_5% PBTN_OUT# 18 GPO 105 BKOFF# C538 C540
20 PBTN_OUT# PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 16

4
EC_PME# 19 GPIO 106 W L_OFF#
24 EC_PME# EC_PME#/GPIO0D WL_OFF#/GPXO09 W L_OFF# 26
25 107 MEDIA_LED# 10P_0402_50V8J 10P_0402_50V8J

IN

OUT
20 EC_THERM# EC_THERM#/GPIO11 GPXO10 MEDIA_LED# 29 2 2
FAN_SPEED1 28 108
33 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 CALIBRATE 37
BT_ON# 29
27 BT_ON# FANFB2/GPIO15
E51TXD_P80DATA 30
E51RXD_P80CLK EC_TX/GPIO16

NC

NC
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# 20
ON/OFF 32 112 ENBKL ENBKL 8,15
30 ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2
29 PW R_SUSP_LED PW R_SUSP_LED 34 114 EAPD
EAPD 31

3
NUM_LED# PWR_LED#/GPIO19 GPXID3 SATA_LED#
29 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 SATA_LED# 19
GPXID5 116 5IN1_LED# 23
117 IDE_LED# X2
GPXID6 IDE_LED# 22 32.768KHZ_12.5P_MC-306
GPXID7 118 ARCADE# 29
EC_CRY1 122
EC_CRY2 XCLK1
123 XCLK0 V18R 124
1
AGND

For KB926 C0 reversion C891


GND
GND
GND
GND
GND

@ C908 ACIN 1 2 100P_0402_50V8J

KB926QFA1_LQFP128_14X14 2 C892
11
24
35
94
113

69

20mil
<BOM Structure> 0.1U_0402_16V4Z BATT_TEMP 1 2 100P_0402_50V8J
A
L48 A
ECAGND 2 1 C893
FBM-L11-160808-800LMT_0603 BATT_OVP 1 2 100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB926
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 28 of 44
5 4 3 2 1
+3VALW

reserve for debug


EC_SPICS#/FSEL# 1
U45
8
To TP/B Conn.
+3VALW CE# VDD SPICLK
3 6
+5VALW +5VALW WP# SCK EC_SO_SPI_SI_R
1 2 7 HOLD# SI 5
4 2 EC_SI_SPI_SO_R
R738 @ 1K_0402_5% VSS SO JP6

1
C550 1 2 0.1U_0402_16V4Z
R442 @ MX25L8005M2C-15G_SOP8 +5VS 6
C551 1 TP_DATA 5
2 0.1U_0402_16V4Z 28 TP_DATA
100K_0402_5% TP_CLK 4
28 TP_CLK 3
U26

2
2
8 VCC A0 1 1
7 2 1 1
WP A1 U27 C130 ACES_85201-0605
15,28,38 EC_SMB_CK1 6 SCL A2 3
5 4 EC_SPICS#/FSEL# 1 8 C129 CONN@
15,28,38 EC_SMB_DA1 SDA GND 28 EC_SPICS#/FSEL# CE# VDD
3 6 SPICLK R443 1 2 0_0402_5% 100P_0402_50V8J 100P_0402_50V8J
WP# SCK EC_SO_SPI_SI_R R445 1 EC_SPICLK 28 2 2
AT24C16AN-10SI-2.7_SO8 2 1 7 5 2 0_0402_5%
HOLD# SI EC_SI_SPI_SO_R R438 1 EC_SO_SPI_SI 28
R739 4 2 2 0_0402_5%
VSS SO EC_SI_SPI_SO 28 TP_DATA
1K_0402_5%

1
MX25L8005M2C-15G_SOP8
R437 +5VS TP_CLK
ENE suggestion SPI Frequency over 66MHz

3
100K_0402_5%
SST: 50MHz C149

2
MXIC: 70MHz D9
0.1U_0402_16V4Z @
ST: 40MHz PSOT24C_SOT23

1
KSI[0..7]
INT_KBD Conn. KSO[0..17]
KSI[0..7] 28

KSO[0..17] 28

JP5
(Left) KSO0
KSO1
26
25
26 G2
28
27
To BTN/B Conn.
KSO2 25 G1
24 24
KSO3 23
KSO4 23 +3VS +5VS
22 22
KSO5 21 JP2 +5VS
KSO6 21 +5VALW
20 20 1 1
KSO7 19 2
KSO8 19 2 C21
18 3 1 2 +3VALW
KSO9 18 3 R16 100K_0402_5%
17 4
KSO10 17 4 PWR_LED# 0.1U_0402_16V4Z D6
16 16 5 5
KSO11 15 6 2
15 6 ON/OFFBTN# 30 ARCADE# 28
KSO12 14 7 WL_R_LED# ARCADE_BTN# 1
KSO13 14 7 BT_LED# 51ON#
13 8 BT_LED# 27,28 3 51ON# 30,35
KSO14 13 8 PWR_SUSP_LED#
12 9
KSO15 12 9 KSO0 DAN202UT106_SC70-3
11 10
KSO16 11 10 KSI1 +3VALW
10 10 11 11
KSO17 9 12 KSI2
KSI0 9 12 KSI3
8 8 13 13
KSI1 7 14 KSI4 C22
KSI2 7 14
6 17 15
KSI3 6 G17 15 0.1U_0402_16V4Z PWR_LED# PWR_SUSP_LED#
5 18 16
KSI4 5 G18 16
4
KSI5 4 ACES_85201-16051
3
KSI6 3
2 CONN@
KSI7 2
1 1
(Right)

1
JP36 D D
ACES_85201-26051 28 PWR_LED 2 28 PWR_SUSP_LED 2
1 G G
2
CONN@ +5VS S Q4 S Q37

3
3 2N7002_SOT23 2N7002_SOT23
4 +3VALW
5 LID_SW# 28
KSO15 C74 1 2 100P_0402_50V8J KSO7 C66 1 2 100P_0402_50V8J KSI5
6 KSO0
KSO14 C73 100P_0402_50V8J KSO6 C65 100P_0402_50V8J 7 ARCADE_BTN#
1 2 1 2
8
KSO13 KSO5 9 NUM_LED# 28
C72 1 2 100P_0402_50V8J C64 1 2 100P_0402_50V8J
10 CAPS_LED# 28
MEDIA_LED# 28 @ R584
KSO12 C71 100P_0402_50V8J KSO4 C63 100P_0402_50V8J 11 WL_R_LED#
1 2 1 2 1 2 WL_LED# 28
12 0_0402_5%
ACES_85201-1205 1 2 MINI1_LED# 26
KSI0 C75 1 2 100P_0402_50V8J KSO3 C62 1 2 100P_0402_50V8J CONN@ R669 0_0402_5%

KSO11 C70 1 2 100P_0402_50V8J KSI4 C54 1 2 100P_0402_50V8J

KSO10 C69 1 2 100P_0402_50V8J KSO2 C61 1 2 100P_0402_50V8J

KSI1 C76 1 2 100P_0402_50V8J KSO1 C60 1 2 100P_0402_50V8J

PWR_LED# C895 1 2 @ 100P_0402_50V8J


FOR EMI
KSI2 C77 1 2 100P_0402_50V8J KSO0 C59 1 2 100P_0402_50V8J
ON/OFFBTN# C896 1 2 @ 100P_0402_50V8J LID_SW# C897 1 2 @ 100P_0402_50V8J
KSO9 C68 1 2 100P_0402_50V8J KSI5 C55 1 2 100P_0402_50V8J KSO0 WL_R_LED# C898 1 2 @ 100P_0402_50V8J
KSI3 C78 1 2 100P_0402_50V8J KSI6 C56 1 2 100P_0402_50V8J KSI1 WL_BTN# BT_LED# C899 1 2 @ 100P_0402_50V8J
KSO8 C67 1 2 100P_0402_50V8J KSI7 C57 1 2 100P_0402_50V8J KSI2 BT_BTN# PWR_SUSP_LED#C900 1 2 @ 100P_0402_50V8J ARCADE_BTN# C901 1 2 @ 100P_0402_50V8J
KSI3 EMAIL_BTN# NUM_LED# C902 1 2 @ 100P_0402_50V8J
KSI4 IE_BTN# CAPS_LED# C903 1 2 @ 100P_0402_50V8J
KSI5 E-KEY_BTN# MEDIA_LED#
R358 LED1 C904 1 2 @ 100P_0402_50V8J
300_0402_5%
1 2 3 1 PWR_LED#
+5VS YG
PWR_LED#
R495
1 2 4 2 PWR_SUSP_LED#
+5VALW A
PWR_SUSP_LED#
453_0402_1%

HT-297DQ/GQ_AMB/YG_0603

R357 LED2
300_0402_5%
+5VALW 1 2 3 YG 1 BATT_GRN_LED# BATT_GRN_LED# 28
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title
R494
+5VALW 1 2 4 A 2 BATT_AMB_LED#
BATT_AMB_LED# 28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
453_0402_1% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
HT-297DQ/GQ_AMB/YG_0603
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 29 of 44
A B C D E

Power Button
ON/OFF switch TOP Side HDA MDC Conn.
1 2
R749 @ 10K_0603_5%
1 2
R750 @ 10K_0603_5% +3VALW
+3V
Bottom Side
1 1
1

2
20mil C127
R434 JP17
1U_0603_10V4Z
100K_0402_5% 2
1 2 1 2
GND1 RES0 R522 0_0402_5%
19 HDA_SDOUT_MDC 3 4

1
D27 IAC_SDATA_OUT RES1
5 6 +3V
GND2 3.3V
2 ON/OFF 28 19 HDA_SYNC_MDC 7 IAC_SYNC GND3 8
ON/OFFBTN# 1 1 2 HDA_SDIN1_MDC 9 10
29 ON/OFFBTN# 19 HDA_SDIN1 IAC_SDATA_IN GND4
3 51ON# R117 39_0402_5% 11 12
51ON# 29,35 19 HDA_RST_MDC# IAC_RESET# IAC_BITCLK HDA_BITCLK_MDC 19

1
DAN202UT106_SC70-3
R509

GND
GND
GND
GND
GND
GND
0_0402_5%
ACES_88018-124G

13
14
15
16
17
18

2
1
2 CONN@ 1
C545 D26 C128
Connector for MDC Rev1.5
1000P_0402_50V7K RLZ20A_LL34 22P_0402_50V8J
1 2

2
For EMI

1
D
EC_ON 2 Q27
28,37 EC_ON
G
2

S 2N7002_SOT23
R428 3

10K_0402_5%
2 2
1

Power ON Circuit
+3VS

+3VALW +3VALW
1

U14A U14B
R331 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14

180K_0402_5%
P

P
2

1 2 3 4 1 2 SYS_PWROK 6,20
I O I O R324 @ 0_0402_5%
G

G
1

D
2
+RTCBATT
34,39 SUSP 2 For South Bridge
7

G C300
Q13 S 1U_0805_25V4Z
3

2N7002_SOT23 1 1 2
28 EC_PWROK
R318 0_0402_5%

2
3 3
R15
+3VS 1K_0402_5%
+3VALW +3VALW

1 1
1

D5
R328
U14C U14D
14

14

10K_0402_1% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14


D18
+RTCVCC
P

P
2

SUSP# 1 2 5 6 9 8
23,27,28,34,40 SUSP# VS_ON 41

2
I O I O
2
G

RB751V_SOD323 C333
For +VCCP/+1.05VS BAS40-04_SOT23-3
+CHGRTC
7

0.1U_0402_16V4Z 1
1 C20

0.1U_0402_16V4Z
2

+3VALW
C319
+3VALW
1 2 0.1U_0402_16V4Z
Change BATT1 P/N : SP093PA0200 (Panasonic)
U14E U14F
14

14

SP093MX0000 (MAXELL)
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
R307 PM@ 200K_0402_5%
P

SUSP# 1 2 11 10 13 12 1 2
I O I O VGA_ON 15
R761 PM@ 0_0402_5%
G

+3VS 1 2
7

4 4
SUSP# 1 2
D16 RB751V_SOD323 R762 @ 0_0402_5%
2
PM@ C330
PM@
0.1U_0402_16V4Z
1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK, Reset and RTC Circuit, TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 30 of 44
A B C D E
A B C D E F G H

+VDDA
28.7K for Module Design (VDDA = 4.702)

1
R478 +5VAMP (output = 250 mA)
10K_0402_5% 60mil U32
+5VS L49 1 2 4 VIN VOUT 5 40mil +VDDA
KC FBM-L11-201209-221LMAT_0805

2
1 1 2
DELAY SENSE or ADJ
6 1 4.85V
1 2 L50 1 2 C581 C588 R467
C591 1U_0402_6.3V4Z KC FBM-L11-201209-221LMAT_0805 7 1 30K_0402_1% C576
ERROR CNOISE

1
10U_0805_10V4Z 10U_0805_10V4Z
R483 2 2
0.1U_0402_16V4Z 8 3 2
1

1
10K_0402_5% SD GND C587
1 SI9182DH-AD_MSOP8 <BOM Structure> 1

1
2
C599 2
1 2 MONO_IN R470
1U_0402_6.3V4Z 0.1U_0402_16V4Z 10K_0402_1%

2
1
C 1 2
C604 1 R490 Q33 R485 2.4K_0402_1%
28 BEEP# 2 1 2 2
1U_0402_6.3V4Z B
560_0402_5% E 2SC2411K_SOT23

3
C609 1 R491
2 1 2
20 SB_SPKR 1U_0402_6.3V4Z

1
560_0402_5%
D29
R493 RB751V_SOD323
10K_0402_5%

2
HD Audio Codec
L51
+AVDD_HDA MBK1608121YZF_0603
20mil 0.1U_0402_16V4Z +3VS_DVDD 1 2 +3VS
L47 1 2 0.1U_0402_16V4Z
40mil
+VDDA 1 1 1
FBM-L11-160808-800LMT_0603 1 1 1 C595 C594 C593
C573 C569
C572 10U_0805_10V4Z
2 10U_0805_10V4Z <BOM Structure> 2 2 2 2

25

38

9
2 2 2 U33
0.1U_0402_16V4Z 0.1U_0402_16V4Z

DVDD_IO
AVDD1

AVDD2

DVDD
<BOM Structure>

<BOM Structure>
14 35 HP_LEFT
NC LINE_OUT_L HP_LEFT 32
15 36 HP_RIGHT
NC LINE_OUT_R HP_RIGHT 32
1 2 MIC2_C_L 16 39 AMP_LEFT
MIC2_L HP_OUT_L AMP_LEFT 32
C589 4.7U_0805_10V4Z
32 INT_MIC_R
1 2 MIC2_C_R 17 41 AMP_RIGHT
MIC2_R HP_OUT_R AMP_RIGHT 32
C586 4.7U_0805_10V4Z
LINE_L 1 2 LINE_C_L 23 45
32 LINE_L LINE1_L NC
C580 4.7U_0805_10V4Z
LINE_R 1 2 LINE_C_R 24 46
32 LINE_R LINE1_R DMIC_CLK
C577 4.7U_0805_10V4Z For EMI
18 43
CD_L NC
20 44 1 2 1 2 C596
CD_R NC R507 0_0402_5% 22P_0402_50V8J
19
CD_GND
6 HDA_BITCLK_AUDIO 19
MIC1_L MIC1_C_L BIT_CLK
32 MIC1_L 1 2 21
C583 4.7U_0805_10V4Z MIC1_L
MIC1_R 1 2 MIC1_C_R 22 8 HDA_SDIN0_AUDIO 1 2
32 MIC1_R MIC1_R SDATA_IN HDA_SDIN0 19
C579 4.7U_0805_10V4Z R486 33_0402_5%
MONO_IN 12 37
PCBEEP MONO_OUT WOOFER_MONO
29
LINE1_VREFO
19 HDA_RST_AUDIO# 11
3 RESET# 3
GPIO1 31
19 HDA_SYNC_AUDIO 10 SYNC 10mil
28 MIC1_VREFO_L
MIC1_VREFO_L
19 HDA_SDOUT_AUDIO 5 SDATA_OUT
32 MIC1_VREFO_R
MIC1_VREFO_R
2
GPIO0
3 30 MIC2_VREFO
R481 2 SENSE_A GPIO3 MIC2_VREFO
32 HP_PLUG# 1 5.1K_0402_1% 13
SENSE A CODEC_VREF
34
SENSE B VREF
27 10mil
R484 1 2 10K_0402_1% 1
32 LINEIN_PLUG#
R479 2 1 20K_0402_1% 47 40
32 MIC_PLUG# 28 EAPD EAPD JDREF C571

1
1 2 SPDIF_R 48 SPDIFO NC 33 10U_0805_10V4Z
32 SPDIF R480 0_0402_5% R476 2
4 26 20K_0402_1%
<BOM Structure>
DVSS1 AVSS1
7 42
DVSS2 AVSS2

2
ALC268-GR_LQFP48_9X9
Sense Pin Impedance Codec Signals 1
R751
2
0_0805_5%
1
R489
2
0_0805_5%

39.2K PORT-A (PIN 39, 41) DGND AGND


1 2 1 2
R752 0_0805_5% R463 0_0805_5%
20K PORT-B (PIN 21, 22)
SENSE A
1 2 1 2
10K PORT-C (PIN 23, 24) R753 0_0805_5% R496 0_0805_5%

5.1K PORT-D (PIN 35, 36)


4
GND GNDA GND GNDA 4
39.2K PORT-E (PIN 14, 15)

20K PORT-F (PIN 16, 17)


SENSE B
10K PORT-G (PIN 43, 44)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-H (PIN 45, 46) Issued Date 2006/12/25 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC268
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 31 of 44
A B C D E F G H
A B C D E

+5VAMP +3VS +5VAMP


R50 FBMA-L11-160808-121LMT_0603 JP3
W=40mil SPKL+ 1 2 SPK_L+ 1
R744 1 SPKL- SPK_L- 1
2 0_0402_5% 1 2 2 2
R38 FBMA-L11-160808-121LMT_0603
R745 1 @ 2 0_0402_5%
1 1 Left
C568 C564 3
0.1U_0402_16V4Z G1
4
C578
0.47U_0603_16V4Z
2 2
4.7U_0805_10V4Z
Int. Speaker Conn. G2
ACES_88266-02001
AMP_RIGHT_C-1 AMP_RIGHT_C
20mil
1 2 1 2 CONN@
31 AMP_RIGHT C582 1U_0402_6.3V4Z

11

19

20
10

1
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C U31 R28 FBMA-L11-160808-121LMT_0603 JP34
31 AMP_LEFT C584 C585 1U_0402_6.3V4Z SPKR+ SPK_R+
1 2 1

CVDD

HVDD

PVDD
PVDD

VDD
1

1
0.47U_0603_16V4Z SPKR- 1 2 SPK_R- 2
1 R477 R475 R26 FBMA-L11-160808-121LMT_0603 2 1
Right
560_0402_5% 560_0402_5% 3 22 SPKR+ 3
INR_A ROUT+ SPKR- G1
5 21 4

2
INL_A ROUT- G2
HPF Fc = 604Hz SPKL+
R473 1 2 100K_0402_5% 27 8 ACES_88266-02001
/AMP EN LOUT+ SPKL- CONN@
9
R469 1 LOUT- +5VAMP +5VAMP
+5VAMP 2 100K_0402_5% 24 HP EN
17 HPOUT_R
+5VAMP HP_RIGHT HP_RIGHT_C 1 HP_RIGHT_R HP_R HPOUT_L
1 2 2 4 18
31 HP_RIGHT C574 2.2U_0805_10V6K R471 39K_0402_5% HP_LEFT_R INR_H HP_L HP_PLUG#
6 INL_H

2
HP_LEFT 1 2 HP_LEFT_C 1 2
31 HP_LEFT
1

2
C570 2.2U_0805_10V6K R468 39K_0402_5% VOL_AMP 26 R760
R472 /SD R350
15 100K_0402_5%
CVSS

1
30K_0402_5% D
28 100K_0402_5%
BEEP
16 2

1 1
VSS G
12
Gain= 14dB 1 1
2

1
CP+

3
C563
S D Q59
14 2 S

3
C561 CP- GND G
SPDIF_PLUG# SPDIF_PLUG# 2
PGND 23 1U_0603_10V4Z 2
VOL_AMP 1U_0603_10V4Z BIAS 25 7 G 2N7002_SOT23
BIAS PGND
1

D 2 2 Q17 Q60
1 13 D S

3
CGND
1

2 EC_MUTE 1 29 AO3413_SOT23-3 2N7002_SOT23


R474 C905 G C575 GND
+5VSPDIF
100K_0402_5% S Q58 APA2057A_TSSOP28
3

2
0.01U_0402_16V7K 2N7002_SOT23 2.2U_0805_10V6K
2
2

S/PDIF Out JACK


2 LINE Out/Headphone Out
C418 2
2 C415 R764 1 2
2 0_0402_5%
330P_0402_50V7K
To AUDIO/B Connector Int MIC Conn. 1
1
330P_0402_50V7K
JP31
20mil HP_PLUG#1 @ R765 2 0_0402_5%
R351 1
+5VSPDIF HPOUT_L 1 HPOUT_L_1 1 HPOUT_L_2 31 HP_PLUG#
2 2 2
47_0603_5% L27 FBM-11-160808-700T_0603 6
HPOUT_R 1 2 HPOUT_R_1 1 2 HPOUT_R_2 3
C543 47_0603_5% L28 FBM-11-160808-700T_0603
R352 SPDIF_PLUG# 5
0.1U_0402_16V4Z
MIC2_VREFO 4
SPDIF 7
31 SPDIF
+5VSPDIF 8
1 10

1
+5VAMP
R51 C416 9
2.2K_0402_5%
C612 2 SINGA_2SJ-E373-T01
15mil
JP4 R523 FBMA-L11-160808-121LMT_0603 100P_0402_50V8J CONN@

2
0.1U_0402_16V4Z 1 INT_MIC_R2
1 2 INT_MIC_R
1 INT_MIC_R 31
2 1 2
2 R524 FBMA-L11-160808-121LMT_0603

3
1
C36 LINE-IN JACK
+3VALW G1 220P_0402_50V7K JP33
4
G2 2
8
ACES_88266-02001 7
C614 CONN@

0.1U_0402_16V4Z LINEIN_PLUG# 5
31 LINEIN_PLUG#
3 INT_MIC_R2 3
4
L54 FBM-11-160808-700T_0603
LINE_R 1 2 LINE_R_R 3
31 LINE_R
2

3
6
@ LINE_L 1 2 LINE_L_R 2
31 LINE_L
L55 FBM-11-160808-700T_0603 1
Volume Control Circuit +3VS
PSOT24C-LF-T7_SOT23-3
D32
1 1
SINGA_2SJ-E351-S03
+3VS C613 C601 CONN@
1

220P_0402_50V7K 220P_0402_50V7K
(HDA Jack)
1

C347 2 2
+3VS 2 1 R330
1

100K_0402_5%
R450 R435 0.1U_0402_16V4Z FOR EMI
MIC JACK
4

U29 10K_0402_5% 10K_0402_5%


2

+3VS
GND

U12 1 JP32
2

C349 MIC1_VREFO_L MIC1_VREFO_R 8


P

NC

2 1 2 2 4 0.1U_0402_16V4Z 7
A R436 10K_0402_5% A Y
G

1
2
1 NC7SZ14P5X_NL_SC70-5 U13 MIC_PLUG# 5
31 MIC_PLUG#
3

COM R488 R487


1 14
CD1# VCC 2.2K_0402_5% 2.2K_0402_5%
2 D1 CD2# 13 4
3 1 2 3 12

2
B R446 10K_0402_5% CP1 D2 MIC1_R_1
4 11 31 MIC1_R 1 2 FBM-11-160808-700T_0603 3
SD1# CP2 L52
1 1 5 10 6
GND

Q1 SD2#
0.01U_0402_16V7K

0.01U_0402_16V7K

C341 C329 6 09 1 1 2 FBM-11-160808-700T_0603 MIC1_L_1 2


Q1# Q2 31 MIC1_L
7 08 L53 1
XRE094PHDINB1-2-12-E-7016_3P GND Q2# C345 1 1
5

2 2 TC74LCX74FT_TSSOP14 SINGA_2SJ-E351-S01
0.1U_0402_16V4Z
2 C603 C602 CONN@
4 220P_0402_50V7K 220P_0402_50V7K 4
2 2
(HDA Jack)
ENCODER_DIR 28
ENCODER_PULSE 28

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/12/25 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 32 of 44
A B C D E
H29 H20 H3 H18 H2 H11 H10 H30 H4
H_S354D138 H_S354D138 H_S354D138 H_S354D138 H_S354D138 H_S354D138 H_S354D138 H_S354D138 H_S354D138

FAN1 Conn @ @ @ @ @ @ @ @ @

1
+5VS
C443 10U_0805_10V4Z +5VS
1 2 H15 H19 H1 H24 H28
H_S354D138 H_C315BC236D138 H_C315BC236D138 H_S354BC140D138 H_C335BC140D138

1
U20 D22
1 8 1SS355_SOD323-2 @ @ @ @ @

1
VEN GND
2 VIN GND 7
+VCC_FAN1 3 6

2
EN_DFAN1 VO GND D21 H6 H16 H17 H7
28 EN_DFAN1 4 5
VSET GND H_C236BC168D165 H_C236BC168D165 H_C236BC168D165 H_C236BC168D165
G993P1UF_SOP8
1 2 Change to SC1BAS16000
BAS16_SOT23-3 For CPU Support Breket
C446 @ @ @ @

1
10U_0805_10V4Z
1 2
+3VS C445 H13 H14 H32 H33 H31
1000P_0402_50V7K H_C236BC131D128 H_C236BC131D128 H_C236BC131D128 H_C236BC131D128 H_C236BC131D128
1 2
For FAN and MXM
1
R365 @ @ @ @ @

1
10K_0402_5%
40mil
JP16
2

+VCC_FAN1 H21 H8
1 H_C236BC131D128 H_C236BC131D128 H5 H27
28 FAN_SPEED1 2 H_C158D158N H_O197X158D197X158N
3
1
C442 ACES_85205-03001 @ @ For MDC

1
1000P_0402_50V7K CONN@ @ @

1
2

H25 H26 H22 H23


H_C205D98 H_C205D98 H_O89X58D59X28 H_O89X58D59X28
For DDR Metal Cage
@ @ @ @

1
FD1 FD2 FD3 FD4 FD5 FD6

@ @ @ @ @ @

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

FD7 FD8 FD9 FD10 FD11

@ @ @ @ @

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

FD12 FD13 FD14 FD15 FD16

@ @ @ @ @

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 33 of 44
A B C D E

+5VALW TO +5VS +3VALW TO +3V_SB(ICH8M AUX Power) +5VALW

+5VALW +5VS +3VALW +3V

2
U22 U34 R455
8 1 8 1 100K_0402_5%
D S D S
7 2 7 2
D S D S

2
6 3 1 1 6 3 1 1

1
D S C503 C495 R411 D S C633 C629 R506 SYSON#
1 1 5 4 1 5 4 24,26,27 SYSON#
C498 C504 D G 470_0603_5% C631 D G 470_0603_5%
AO4468_SO8 10U_0805_10V4Z AO4468_SO8 10U_0805_10V4Z

1
10U_0805_10V4Z 2 2
1U_0603_10V4Z 2 2
1U_0603_10V4Z D

1
1 2 2
10U_0805_10V4Z 2
10U_0805_10V4Z SYSON 2 Q29 1
27,28,40 SYSON
G 2N7002_SOT23

1
D D
S

3
1
2 SUSP 2 SBPWR_EN#
G G R440
+VSB 2 1 5VS_GATE S Q23 +VSB 2 1 3V_GATE S Q38 100K_0402_5%

3
R412 2N7002_SOT23 R505 2N7002_SOT23
200K_0402_5% 1 200K_0402_5% 1

2
1
D C506 C632

1
SUSP D
2
Q24G 0.1U_0603_25V7K SBPWR_EN# 2 0.1U_0603_25V7K
2N7002_SOT23 S 2 Q39G 2 +5VALW
3

2N7002_SOT23 S

2
R462
100K_0402_5%

1
SUSP
+3VALW TO +3VS 30,39 SUSP

1
+3VALW +3VS D
2 Q31
23,27,28,30,40 SUSP#
U10 G 2N7002_SOT23
8 1 S

3
D S

1
7 2
D S

2
6 3 1 1 R457
D S C301 C299 R306 100K_0402_5%
1 1 5 D G 4
C344 C343 470_0603_5%
AO4468_SO8 10U_0805_10V4Z

2
10U_0805_10V4Z 2 2
1U_0603_10V4Z
2 2 2
10U_0805_10V4Z 1 1 2
D
2 SUSP
G
S Q12
3

5VS_GATE 2N7002_SOT23

+5VALW

2
+1.8V to +1.8VS R379
100K_0402_5%
+1.8V +1.8VS

1
U24
8 1
D S SBPWR_EN#
7 2 1 1 21 SBPWR_EN#
D S
2

6 3 C533 C531
D S R427
1 1 5 4
C553 C547 D G 10U_0805_10V4Z 470_0603_5%

1
SI4856ADY_SO8 PM@ 2 2
1U_0603_10V4Z PM@ D
10U_0805_10V4Z PM@ PM@ 28 SBPWR_EN 2
1

PM@ 2 2
10U_0805_10V4Z G
PM@ SI4856/AO4430 Q43 S

3
1

1
D 2N7002_SOT23
2 SUSP R510
G 100K_0402_5%
2 1 1.8VS_GATE S Q26
+VSB
3

R439 2N7002_SOT23

2
510K_0402_5% 1 PM@
3 PM@ C542 3
1

D
SUSP 2 0.1U_0603_25V7K
G 2 PM@
Q28 S
3

2N7002_SOT23
PM@

+1.5VS +2.5VS +1.05VS +0.9VS +1.8V


2

R204 R374 R403 R342 R424


470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
@ @
1

1
1

D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SYSON#
G G G G G
S Q11 S Q19 S Q22 S Q16 S Q25
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23


@ @
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 34 of 44
A B C D E
A B C D

PJP1 PL1
6 ADPIN VIN
G2 FBMA-L18-453215-900LMA90T_1812
G1 5 1 2

1
PR1

560P_0402_50V7K

12P_0402_50V8J
4 10_1206_5%

12P_0402_50V8J

560P_0402_50V7K
4

1
PC1

PC2

PC3

PC4
1 PR2 1

1 2
3 1K_1206_5%

2
3
1 2
PD1
2 RLZ24B_LL34 PQ1
2 PR3 TP0610K-T1-E3_SOT23-3
VIN PD2 1K_1206_5%
B+

2
1 1 2 1 1 2 3 1

RLS4148_LLDS2 PR4
E&T_4510-E04C-01R 1K_1206_5%
1 2

100K_0402_5%

100K_0402_5%
1

1
PR5
PR7

PR6
1K_1206_5%

2
1 2

2
VIN

1
PD3
RLS4148_LLDS2 PR8

1
PD4 100K_0402_5%
RB751V-40TE17_SOD323-2 PQ2

1 1
2 1 DTC115EUA_SC70-3

1 2
BATT+
2 PR9 28,37 ACOFF 2 2

33_1206_5% VS PQ3
PQ4 DTC115EUA_SC70-3
TP0610K-T1-E3_SOT23-3
2 2

3
CHGRTCP 3 1
0.22U_1206_25V7K
1

3
1

PR10
PC5

100K_0402_5% PC6
0.1U_0603_25V7K
2

PR11
B+
2

22K_0402_5% PR12
29,30 51ON# 1 2 VL 2.2M_0402_5%
2 1

1
VS PR13
499K_0402_1%

1
1

PR14

2
RTCVREF PR15 100K_0402_1%
200_0805_5% PU2A
3.3V PU1 LM393DT_SO8

8
G920AT24U_SOT89-3 19,36,38 MAINPWON PD5
2

PR16 PR17 2 3

P
3 3
+
1 2 1 2 3 OUT IN 2 1 1 O
+CHGRTC 37 ACON 3 2

0.01U_0402_25V7K
-

G
1

1
560_0603_5% 560_0603_5%
4.7U_0805_6.3V6K
1

1
GND
PC8

32.8

PC9
PC7 RB715F_SOT323-3 PR18

1000P_0402_50V7K
4
1

1
1U_0805_25V4Z 191K_0402_1%
2

1 PC10 PR19

PC11
2

2
0.1U_0603_25V7K 499K_0402_1%

PRG++ 2

2
ACIN
PR20 PQ5 PR21
Precharge detector D

1
34K_0402_1% RHU002N06_SOT323-3 47K_0402_5%
Min. typ. Max. RTCVREF 2 1
G
2 2 1
PACIN 37,38

1
H-->L 14.589V 14.84V 15.243V S

3
PQ6

1
DTC115EUA_SC70-3
L-->H 15.562V 15.97V 16.388V @ PR22
- PBJ1 + +RTCBATT 66.5K_0402_1% 2 +5VALW
2 1 +RTCBATT BATT ONLY

2
Precharge detector

3
ML1220T13RE Min. typ. Max.
4
45@
H-->L 6.138V 6.214V 6.359V 4

L-->H 7.196V 7.349V 7.505V

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/01/16 Deciphered Date 2008/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B JDW50/JDY70 LA3771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 35 of 44
A B C D
A B C D

MAX8744_B+
MAX8744_B+
B+
PL2

FBMA-L18-453215-900LMA90T_1812
1 2

2200P_0402_50V7K
2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
1
1

1
PC13

PC12

PC16
8
7
6
5

5
6
7
8
PC14

PC15
1 1

D
D
D
D

D
D
D
D
2

2
PQ8
PQ7 SI4800BDY-T1-E3_SO8
SI4800BDY-T1-E3_SO8

G
S
S
S

S
S
S
1
2
3
4

4
3
2
1
PL3 PU3
10UH_SIL104R-100PF_4.4A_30% MAX8744ETJ+_TQFN32_5X5
PC17
1 2 1U_1206_25V7K
+3VALWP 33 21 1 2
EP IN

2.2_1206_5%
SI4810BDY-T1-E3_SO8
2

5
6
7
D 8
DH3 DH5

2.2_1206_5%
25 16

2.61K_0402_1%
DH3 DH5

8
7
6
5
PR24 PR25

PR23

@ PR195

@ PR196
D
D
D
SI4810BDY-T1-E3_SO8

PQ9
2 1 BST3A 26 15 BST5A 2 1
6.81K_0402_1%

D
D
D
D
330U_D3L_6.3VM_R25M

BST3 BST5
2

1 0_0603_5%

1 2
2

2
PC19 0_0603_5% PC20 PR27
PR26

G
S
S
1 S

10UH_SIL104R-100PF_4.4A_30%
+

PQ10
0.1U_0603_25V7K 2.61K_0402_1%

G
S
S
S
PR28 0.1U_0603_25V7K
PC18

2 1

680P_0402_50V7K
1

4
3
2
1
6.49K_0402_1% LX3 LX5

PC162
24 17

680P_0402_50V7K
1

1
2
3
4

2
2 LX3 LX5

PC161
2 1

0.22U_0603_16V7K
2

2
DL3 23 18 DL5 @

6.49K_0402_1%
DL3 DL5

2
1 2 @

PL4
PR29
2

PC21

PC22
10K_0402_1%

PGND 19
0.22U_0603_16V7K CSH3
PR30

2 29 2

1
CSH3

1
CSL3 28 12 CSH5
CSL3 CSH5
1

13 CSL5
CSL5

1
PC23 FB3 30
1000P_0402_50V7K FB3 +5VALWP

15.4K_0402_1%
2VREF_8744

1
PC25

2
1 2 7 11 FB5 1000P_0402_50V7K
REF FB5 PC26

PR31
2
PC24 0.22U_0603_10V7K VL 4.7U_0805_6.3V6K
2 20 1 2

150U_D2_6.3VM
DRVA LDO5

1
@ PR32 0_0402_5% 1
SKIP 10 2 12VREF_8744

2
+

PC27
+3VALWP Ipeak = 5.5A; Imax = 4A 32 OUTA PR182 0_0402_5%

PR33
10K_0402_1%
PGOODA 22 1 2
PZD1 2
31 FBA
RLZ5.1B_LL34 PR34
DCR = 35m ohm(max) ; Rcs = 24.96m ohm

1
VS 100K_0402_5% 27
PGOOD3 SPOK 38
1 21 2 4 SHDN
DCR = 29m ohm(typical) ; Rcs = 20.68m ohm
2
200K_0402_5%

PGOOD5 14
2

PC28 PR36
PR35

6 ON5
0.22U_0603_25V7K 0_0402_5%
Ilimit = 185mV/24.96m ~ 215mV/20.68m 3 ILM 2 12VREF_8744
1

ILIM
= 7.41A ~ 10.39A

FSEL
5

GND
ONA
1

ON3

2
+5VALWP Ipeak = 5.5A ; Imax = 4A

499K_0402_1%
2

@ PR37
3
Iocp(mean) = Ilimit -Delta I/2 =6.956A~9.936A 3

2
@ PR38

0_0402_5%

8
0_0402_5%
DCR = 35m ohm(max) ; Rcs = 24.96m ohm

PR39

1
2
PR179
Delta I=((Vin-Vo)*D)/(F*L)

0_0402_5%

2VREF_8744
1

0_0402_5%

PR40
19,35,38 MAINPW ON 2VREF_8744 1
DCR = 29m ohm(typical) ; Rcs = 20.68m ohm
=((19-3.3)*(3.3/19))/(300K*10U) 2 1 1 2

PR41
=0.908A Ilimit = 185mV/24.96m ~ 215mV/20.68m

1
@ 47K_0402_5%
= 7.41A ~ 10.39A
0.047U_0402_16V7K
1

1
PC30

Notes : PC29
Iocp(mean) = Ilimit -Delta I/2
1U_0603_6.3V6M
=6.796A~9.776A
2

fESR<=fOSC/ ; fESR=1/(2**RESR*COUT)
ON3 = REF --->3.3V starts up delay 2ms after 5V starts up @
Delta I=((Vin-Vo)*D)/(F*L)
=((19-5)*(5/19))/(300K*10U)
1.228A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/01/16 Deciphered Date 2008/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JDW50/JDY70 LA3771P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 36 of 44
A B C D
A B C D

Iada=0~4.74A(90W)
ADP_I = 19.9*Iadapter*Rsense
CP = 85%*Iada ; CP = 4.07A
PQ29 P2 PQ30
AO4407_SO8 AO4407_SO8 P3
PR151
0.02_2512_1%
B+ PL15
CHG_B+
PQ31
AO4407_SO8
VIN 8 1 1 8 FBMA-L18-453215-900LMA90T_1812 1 8
7 2 2 7 1 4 1 2 2 7
6 3 3 6 3 6
5 5 2 3 CSIN 5
1 1
CSIP

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_25V7K
0.1U_0603_25V7K
4

4
PQ43

1
TP0610K-T1-E3_SOT23-3

PC123

PC124
1

PC125

PC126
PR154

5600P_0402_25V7K
PR152 DCIN 47K_0402_1%

0.1U_0603_25V7K
VIN 3 1

2
1

2
47K_0402_1% PR153 1 2
VIN

1
PC127

PC128
200K_0402_1% PC129

100K_0402_1%
0.1U_0603_25V7K PQ44
2

1
PR184
DTC115EUA_SC70-3 PD11

2
1SS355TE-17_SOD323-2
PD17 PR155 1 2 ACOFF

2
3

PQ32 PR185 2FSTCHG 10K_0402_1%

2
DTA144EUA_SC70-3 PD16 2 1 21
1SS355TE-17_SOD323-2 3 EC_ON

1
2 1 2 6251VDD 100K_0402_1% EC_ON 28,30 PR156
RB715F_SOT323-3 200K_0402_1%

2.2U_0603_6.3V6K
PC130
PR157 1 2 VIN

3
1
10K_0402_5%

1
2 1 PU10 PC131
28 FSTCHG
1

0.1U_0603_25V7K
1

2
1 2 1 24 DCIN 2 1 PD13
VDD DCIN

1
6251VDD 1 PC153 BATT+ PQ33 1SS355TE-17_SOD323-2

100K_0402_1%
2
0.1U_0402_16V7K DTC115EUA_SC70-3 2 1 2

PR159
2 PR158 2 23
PQ34 47K_0402_5% PQ35 ACSET ACPRN PR197 PQ36

1
DTC115EUA_SC70-3 DTC115EUA_SC70-3 20_0603_5% D RHU002N06_SOT323-3

1
6251_EN CSON 2 PACIN

0.1U_0603_25V7K
3 22 1 2

3
EN CSON
1

2
D

PC132
2 @ PC134 PC133 G
28 3S/4S#
3

5
6
7
8
2 PR160 680P_0402_50V7K 0.047U_0603_16V7K S

3
G 150K_0402_1% CSON 1 2 4 21 1 2 CSOP

D
D
D
D
1
CELLS CSOP
S PQ37 PR161
3

2
RHU002N06_SOT323-3 PC135 6800P_0402_25V7K 20_0603_5% PQ38 2
2

3
1 2 5 20 2 1 SI4800BDY-T1-E3_SO8
ICOMP CSIN

G
2

S
S
S
PR162 20_0603_5%
PC137 PR163 10K_0402_1% PC136 0.1U_0603_25V7K

4
3
2
1
1 2 1 2 6 19 1 2 PR165

1
PR164 VCOMP CSIP PR198 PL16 0.02_2512_1%
0.01U_0402_25V7K 1
2 100_0402_1% 2.2_0603_5% 10UH_PCMB104T-100MS_6A_20% BATT+
PR166 PC138 1 2 7 18 LX_CHG 1 2 CHG 1 4
ICM PHASE
1

22K_0402_5% D 100P_0402_50V8J
PACIN 1 2 2 PQ39 2 3
35,38 PACIN

1
RHU002N06_SOT323-3 6251VREF DH_CHG

4.7_1206_5%
G 8 17

SI4800BDY-T1-E3_SO8
28 ADP_I VREF UGATE

PR199
S PC139 PR167 PC140
3

5
6
7
8
PR168 2.2_0603_5% 0.1U_0603_25V7K

10U_1206_25V6M
1 2

PQ40
80.6K_0402_1% BST_CHG 1 BST_CHGA 2

10U_1206_25V6M
9 16 2 1

D
D
D
D
CHLIM BOOT

1
ACON 2 1 0.1U_0402_16V7K
35 ACON

2
28 IREF

1
PC141

PC142
PD14
0.01U_0402_25V7K

6251aclim 6251VDDP RB751V-40TE17_SOD323-2

680P_0402_50V7K
10 ACLIM VDDP 15

G
1

S
S
S

2
1

1
PC143

PC163
PQ41 PR170 1 26251VDD

4
3
2
1
DTC115EUA_SC70-3 100K_0402_1% 11 14 DL_CHG
VADJ LGATE

2
PR171
2

2
ACOFF 2 4.7_0603_5%
28,35 ACOFF
2

12 13 PC144

1
GND PGND 4.7U_0805_6.3V6K
PR173
274K_0402_1% ISL6251AHAZ-T_QSOP24
3

6251VREF 3
D

1 1 2

PQ42
1

SI2301BDS-T1-E3_SOT23-3
G
2

PR174
3 CP mode 100K_0402_1% PR183 3

Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05) 274K_0402_1%
6251VREF
where Vaclm=1.502V, Iinput=4.07A OVP voltage :
2

1
Vaclim=2.39*((10K//152K)/((5.76K//152K)+(10K//152K))) LI-4S :18.0V--BATT-OVP=2.677V
@PR186
@PR186 VS BATT+
1

D 100K_0402_1% 6251_EN
=1.502V BATT-OVP=0.1487*BATT+
2 PQ45

1
G RHU002N06_SOT323-3 C LI-3S :13.50V--BATT-OVP=2.007V
2
28 CALIBRATE

1
28 CHGSEL S 2 @ PQ46
3

B 2SC2411K_SOT23-3 PR175 BATT-OVP=0.1487*BATT+

0.01U_0402_25V7K
CC=0.6~4.48A 0.01U_0402_25V7K
E 845K_0603_1%

3
1

1
PC154

PC145
IREF=0.7224*Icharge

2
2

@ @ PR187

1
CSON 20K_0402_1% PR192
IREF=0.43V~3.24V
2

PR176 11.5K_0402_1%
300K_0603_0.1% 6251VREF 1 2 6251aclim
PU11A

2.37K_0402_1%
UMA@ PR193
PR177 LM358ADT_SO8

1
10K_0402_5%
Charging Voltage + 3

P
1 2 1 PR194
BATT Type 3S/4S# CHGSEL CV mode 0 20K_0402_1%
(0x15) 28 BATT_OVP - 2

G
VS
0.01U_0402_25V7K

1
4

2
1

1
PC146

PU11B PR178 PC147 UMA@ PQ47


2800mAH 4S pack 17400mV LOW LOW 17.20V LM358ADT_SO8 200K_0402_1% 0.01U_0402_25V7K RHU002N06_SOT323-3
8

1
D
2

2
5 2
P

2
7
+ 28 65W/90W# G
2800mAH 3S pack 13050mV HIGH LOW 12.90V 0
6 S

3
-
G

4 4
4

Normal 4S LI-ON Cells 16800mV LOW HIGH 16.80V

Normal 3S LI-ON Cells 12600mV HIGH HIGH 12.60V


Security Classification Compal Secret Data Compal Electronics, Inc.
Wake up charge while Issued Date 2007/01/16 Deciphered Date 2008/01/16 Title
no communication - HIGH HIGH 12.60V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JDW50/JDY70 LA3771P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 37 of 44
A B C D
A B C D

PH1 under CPU botten side :


CPU thermal protection at 90 degree C
Recovery at 70 degree C

VL
1

SUYIN_200275MR007G161ZL
BATT++ VS VL
1

PJP2 PL5
FBMA-L18-453215-900LMA90T_1812

2
BATT++
1 1 2 BATT+

1
PC31 PR44 PR42
2 TSA 0.1U_0603_25V7K 442K_0603_1% 150K_0402_1%
3 EC_SMC1 PR43 1 2

2
4 EC_SMD1 9.76K_0402_1%

1
5

2
6 PR45 PU2B
7

8
82.5K_0603_1% LM393DT_SO8
PC32 PC33 1 2 5

P
1000P_0603_50V7K 0.01U_0603_50V7K + MAINPW ON 19,35,36

100_0603_1%
<BOM Structure> 7

2
O

1
TM_REF1 6

100K_0603_1%_TH11-4H104FT
-

G
PR46

4
PH1
2

1
100_0603_1%
PR48

1U_0805_16V7K
2
1

1
6.49K_0603_1% PC34 PR49
PR47

PC35
1 2 1000P_0402_50V7K 150K_0402_1%
+3VALW P
2 1 VL
2

2
1
PR50

1
1K_0603_1%
2 PR51 2

150K_0402_1%
2

2
BATT_TEMP BATT_TEMP 28

EC_SMB_CK1 15,28,29

EC_SMB_DA1 15,28,29

PR52
1M_0402_1%
1 2

VIN VIN

PR54

1
10K_0402_5% PR55
PR53 VS 10K_0402_5%
84.5K_0402_1% 1 2 ACIN
ACIN 20,28
PR56

2
8
22K_0402_5% PU4A
1 2 3 LM393DT_SO8

P
3 3
+ PACIN
O 1 PACIN 35,37

20K_0402_1%
2 -

G
1
1

1
PC36

PR57

4
PQ11 1000P_0402_50V7K PC37 PZD2 PR58
TP0610K-T1-E3_SOT23-3 0.1U_0603_25V7K RLZ4.3B_LL34 10K_0402_5%

2
2
B+ 3 1 +VSBP

2
PR60
1

10K_0402_5%
1

PR59 2 1
100K_0402_5% PC38 PC39 RTCVREF
0.22U_1206_25V7K 0.1U_0603_25V7K
2

PR61
2

22K_0402_5%
VL 1 2 PU4B

8
LM393DT_SO8
5

P
+
2

PR62 Vin Detector 6


O 7
-

G
100K_0402_5%
Min. typ. Max.

4
PR63
H-->L 16.976V 17.257V 17.728V
1

D
1

0_0402_5%
PQ12
36 SPOK
1 2 2
G RHU002N06_SOT323-3 L-->H 17.430V 17.901V 18.384V
S
3
1

4 4

@ PC40
0.1U_0402_16V7K
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/01/16 Deciphered Date 2008/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B JDW50/JDY70 LA3771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 38 of 44
A B C D
5 4 3 2 1

+3VALW

1
PJP3

1
JUMP_43X118
+1.8V

2
2
1

2
10U_0805_6.3V6M
PJP4

PC73
D JUMP_43X118 D

+5VALW

1
2
RTCVREF
+1.8V

2
PU7
PU6 CM8562IS_PSOP8
1 6
VIN VCNTL +3VALW 1 8
VIN PGND
2 GND NC 5

1
1

2
1U_0603_16V6K
PC74 PC75
3 REFEN NC 7
+2.5VSP 2 VFB AGND 7

PC76
10U_0805_6.3V6M 1U_0603_6.3V6M

2
PR110 4 8

1
1K_0402_1% VOUT NC
3 6
VTT VCCA

10_0603_1%
PR111
9

2
GND

AGND
RT9173DPSP_SO8 4 5
VTT REFEN

RHU002N06_SOT323-3
2 1

1K_0402_1%

0.1U_0402_16V7K
PR113

9
+0.9VSP
1

2
0_0402_5% D PC77 PR112

2
1

200K_0402_1%
PQ19

PR114

PC78

PR115
SUSP 1 2 2 22U_1206_10V6M 60.4K_0402_1%

2
30,34 SUSP

0.1U_0603_25V7K
G

2
S PC79 PC80
3

PC81
22U_1206_10V6M 0.047U_0402_16V7K
2

1
1

2
PQ20 PR116

1
D RHU002N06_SOT323-3 0_0402_5%
2 1 2 SUSP
G
C C
S

3
PJP5 PJP6
2 1 2 1
+3VALWP 2 1
+3VALW +1.8VP 2 1
+1.8V
JUMP_43X118 JUMP_43X118

PJP7 PJP8
2 1 2 1
+5VALWP 2 1 +5VALW +2.5VSP 2 1 +2.5VS
JUMP_43X118 JUMP_43X118

PJP9 PJP10
2 1 2 1
+0.9VSP 2 1
+0.9VS +1.5VSP 2 1
+1.5VS
JUMP_43X118 JUMP_43X118

B PJP13 PJP12 B
2 1 2 1
+1.05VSP 2 1
+1.05VS +VSBP 2 1
+VSB
JUMP_43X118 JUMP_43X118

PJP14
2 1
+1.05VSP 2 1
+1.05VS
JUMP_43X118

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/01/16 Deciphered Date 2008/01/16 Title
+0.9VSP/+2.5VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom JDW50/JDY70 LA3771P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 39 of 44
5 4 3 2 1
5 4 3 2 1

+5VALW

D D

1
1
PR180

1
PC82 10_0603_5%
2.2U_0603_6.3V6K PR117 PD9

2
10_0603_5% VCCA_1.8V CHP202UPT_SOT323-3

1 2
B+

1U_0603_10V6K
VCCA_1.5V

PC149
1 2
B+_1.8/1.5

1U_0603_10V6K

1
PL9

PC83

2
FBMA-L11-322513-151LMA50T_1210 PR118
1 2 BST_1.5V-1 100K_0402_5%

2
4.7U_1206_25V6K
4.7U_1206_25V6K

2
1

1
PC85

BST_1.8V-1

8
7
6
5
PU8
PC86

PQ21
D
D
D
D
2

SI4800BDY-T1-E3_SO8 1 PGND1 VSSA1 28

DL_1.8V 2 27 PGOOD1_1.8V
G DL1 PGD1
S
S
S
PR119 PC87
Maximum continuous current=>6A 0_0603_5% 1 2 +5VALW 3 26 FB_1.8V B+_1.8/1.5
1
2
3
4

DH_1.8V-1 1U_0603_10V6K VDDP1 FB1 PC88


1 2

4.7U_1206_25V6K
+1.8VP

1
PL10 1 2 ILIM_1.8V4 25 VCCA_1.8V 1000P_0402_50V7K

4.7U_1206_25V6K
ILIM1 VCCA1 PQ22
1UH_SIL104-1R0-R_11A_30% PR120 34.8K_0402_1%

PC89

PC90
1 2
Vout_1.8V 1 2 LX_1.8V 5 24 Vout_1.8V 8 1

2
LX1 VOUT1 PR121 G2 D2
7 2

DH_1.5V-1
DH_1.8V D1/S2/K D2
6 DH1 TON1 23 2 1 B+_1.8/1.5 6 D1/S2/K G1 3
1

C PC91 PR123 820K_0402_5% 5 4 C


26.1K_0402_1%

D1/S2/K S1/A
1

1 2 1 2 BST_1.8V 7 BST1 EN/PSV1 22


PC92 PR124 PC93
PR122

AO4916_SO8
8
7
6
5

1 33P_0402_50V8K 0.1U_0603_25V7K 0_0603_5% 8 21 BST_1.5V1 2 1 2 PR126


330U_D2E_2.5VM

EN/PSV2 BST2 0_0603_5% 0_0603_5% Maximum continuous current=>6A


D
D
D
D
2

+ FB_1.8V B+_1.8/1.5 DH_1.5V 0.1U_0603_25V7K PL11


PC94

2 1 9 TON2 DH2 20 1 2
PQ23
SI4810BDY-T1-E3_SO8 PR125 Vout_1.5V 10 19 LX_1.5V
2.2UH_SIQB74B-2R2-R_6.5A_20%
1 2 Vout_1.5V
+1.5VSP
VOUT2 LX2
G
1

2
S
S
S

1M_0402_5% PR128

1
PR127 VCCA_1.5V ILIM_1.5V1

20K_0402_1%
11 18 2
1
2
3
4

VCCA2 ILIM2

1
10K_0402_1% PC96 29.4K_0402_1%
1000P_0402_50V7K FB_1.5V +5VALW PC97

PR129
12 17 1

330U_D2E_2.5VM
2
FB2 VDDP2 33P_0402_50V8K
2

2
DL_1.5V +

PC98
13 PGD2 DL2 16

2
14 15 FB_1.5V
VSSA2 PGND2

1
2

1
PR131 PC100
0_0402_5% 1U_0603_10V6K PR130

2
Close to IC Side 1 2 SC413TSTRT_TSSOP28 10K_0402_1%
23,27,28,30,34 SUSP#
Differential routing of feedback VFB=0.5V

2
1

@ PC101
to VSSA1 and VOUT1 PIN +5VALW 0.1U_0402_16V7K
2
1

PR132 PR133 Close to IC Side


B 100K_0402_5% 0_0402_5% B

1 2 Differential routing of feedback to VSSA2 and VOUT2 PIN


27,28,34 SYSON
2

1
@ PC102
PGOOD2_1.5V 0.1U_0402_16V7K

2
VFB=0.5V
VFB=0.5V Vo=VFB*(1+PR129/PR130)=1.5V
Vo=VFB*(1+PR122/PR127)=1.805V Ipeak=5.16A, Imax=3.612A
Ipeak=12.17A, Imax=8.519A Ton=(3.3E-12*(PR125+37K)*(Vout/VBat))+50ns
Ton=(3.3E-12*(PR121+37K)*(Vout/VBat))+50ns =0.3201us
=3.3*10e-12*(820K+37K)*(1.8/19)+50ns=0.3179us AO4916 Rds(on)=>Typ:21 mOhm
FDS6670AS:Rds(on)=>Typ:9 mOhm Max:27 mOhm
Max:11.5 mOhm Ivalleymin=9*10u*(29.4K/0.027*1.4)=7A
Iocp=Ivalley+Iripple/2 Ivalleymax=11*E-6*(29.4K/0.021*1.1)=12.833A
Iripple=(vin-vout)*(Ton/L)=5.467A, 1/2 Iripple=2.734A. Iripple=(vin-vout)*(Ton/L)=2.546A, 1/2Iriiple=1.273A

A
Ivalleymin=10E-6*(PR120/Rds(ON)max*1.5) Iocp=Ivalley+Iripple/2 A

=9*10e-6*(27.4K/0.0115*1.5)=14.295A>11.73*1.2=14.076A OCP==>8.273A~14.106A
Ivalleymax=10E-6*(PR120/Rds(ON)typ*1.2)
=11*10e-6*(27.4K/0.009*1.2)=27.907A. Security Classification Compal Secret Data Compal Electronics, Inc.
OCP==>17.029A~30.641A Issued Date 2007/01/16 Deciphered Date 2008/01/16 Title
+1.5VSP/+1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JDW50/JDY70 LA3771P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 40 of 44
5 4 3 2 1
5 4 3 2 1

D D

+5VALW

1
1
PR134
PR148 PC103 10_0603_5%
0_0402_5% 2.2U_0603_6.3V6K

2
1 2

2
30 VS_ON VCCA_1.05V PD10

1
PR142 1SS355TE-17_SOD323-2
B+_1.05

1U_0603_10V6K
1
@ PC121
@PC121 1M_0402_5% PL12

PC104
0.1U_0402_16V7K B+_1.05 2 1 FBMA-L11-322513-151LMA50T_1210
2

1
1 2 B+

BST_1.05V-1

4.7U_1206_25V6K
SI4800BDY-T1-E3_SO8

1
4.7U_1206_25V6K
1

PC109

PC110
5
D 6
7
D 8
PC116

2
1000P_0402_50V7K

D
2

PQ26
C C
+5VALW

16

15

14

13

G
3 S
S
1 S
PR141 PC113
BST_1.05V 1 2 1 2

TON

NC
EN/PSV

BST

2
0_0603_5% Maximum continuous current=>6A
1

Vout_1.05V 1 12 DH_1.05V 0.1U_0603_25V7K PL14


VOUT DH
PR149
100K_0402_5% VCCA_1.05V 2 11 LX_1.05V
1UH_SIL104-1R0-R_11A_30%
1 2 Vout_1.05V
+1.05VSP
VCCA LX PR145
FB_1.05V ILIM_1.05V

11K_0402_1%
3 10 1 2
2

FB ILIM

1
34K_0402_1%

5
6
7
8
PGOOD2_1.05V +5VALW PC117

PR146
4 9 1

330U_D2E_2.5VM
PGD VDDP

PGND
VSSA
PQ28 33P_0402_50V8K

D
D
D
D

2
+

NC

PC118
TP

DL
SI4810BDY-T1-E3_SO8

2
PU9 FB_1.05V

17

G
2

S
S
S
SC411MLTRT_MLPQ16_4X4

1
VFB=0.5V

4
3
2
1
DL_1.05V PR147
10K_0402_1%

1
PC120

2
1U_0603_10V6K

2
Close to IC Side
B B
Differential routing of feedback to VSSA2 and VOUT2 PIN

VFB=0.5V, Ipeak=9.37A, Imax=6.559A


The current rating of +1.05VSP include +VCC_GFX current.
Vo=VFB*(1+PR146/PR147)=1.05V
Ton=(3.3E-12*(PR142+37K)*(Vout/VBat))+50ns=0.2391us
SI4810BDY:Rds(on)=>Typ:16mOhm
Max:20mOhm
Ivalleymin=9*10E-6*(PR145/Rds(ON)max*1.5)
=9*10E-6*(34K/(0.02*1.5))=10.200A
Ivalleymax=11*10E-6*(PR145/Rds(ON)min*1.3)
=11*10E-6*(34K/(0.016*1.3))=17.981A
Iripple=(vin-vout)*(Ton/L)=4.292A, 1/2Iripple=2.146A
Iocp=Ivalley+Iripple/2

A OCP==>12.346A~20.127A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/01/16 Deciphered Date 2008/01/16 Title
+1.05VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JDW50/JDY70 LA3771P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 41 of 44
5 4 3 2 1
5 4 3 2 1

+5VS
CPU_B+ B+
PR64
0_1206_5% PL6
5VS1 2 1 FBMA-L18-453215-900LMA90T_1812
1 2

0.01U_0402_25V7K
1

@ PC42
100U_25V_M
PR65

2200P_0402_50V7K
0.1U_0603_25V7K
1
+

PC43
10_0402_5%

1
10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK
PC44

PC45

PC46

PC47

PC48
200K_0402_5%
2

2
1
2

2
D D

PR66
PC49

2
PC50 2.2U_0603_6.3V6K

2
PR67 1U_0603_6.3V6M

1
13K_0402_1%

5
PQ13
SI7686DP-T1-E3_SO8
PU5

1
NTC
PH2
@PH2
@ VCC 19 25
Use one 220uF or two 100uF
100K_0603_1%_TH11-4H104FT Vcc VDD PC51 4
1 2 6 8 PR69 0.22U_0603_16V7K
THRM TON 0_0603_5%
PR68 0_0402_5%
5 CPU_VID0 2 1 31 D0 BST1 30 BST1_CPU 1 2 BSTM1_CPU 1 2 PR71 +CPU_CORE
0_0603_5%

3
2
1
PR70 0_0402_5% 2 1 32 29 DH1_CPU 1 2 PL7
5 CPU_VID1 D1 DH1 0.36UH_PCMC104T-R36MN1R17_30A_20%
PR72 0_0402_5% 2 1 33 28 LX1_CPU 2 1 +CPU_CORE
5 CPU_VID2 D2 LX1

1
PR73 0_0402_5% DL1_CPU

4.7_1206_5%

2.1K_0402_1%
5 CPU_VID3 2 1 34 D3 DL1 26

2
PR74
FDS6676AS_SO8

5
6
7
8

5
6
7
8

PR76
PR75 0_0402_5%

FDS6676AS_SO8
5 CPU_VID4 2 1 35 D4 PGND1 27

PQ14

D
D
D
D

D
D
D
D
PQ15
PR77 0_0402_5% 2 1 36 18
5 CPU_VID5

2
D5 GND PR79 NTC

1
CSP1_CPU

10_0402_5%
PR78 0_0402_5% 1 2 37 17 3.48K_0402_1% PH3
5 CPU_VID6 D6 CSP1

G
S
S
S

S
S
S

PR80
680P_0402_50V7K
1 2 1 2

5
VCCSENSE
PR81 2 71.5K_0402_1%
1 7 16 CSN1_CPU

4
3
2
1

4
3
2
1
TIME CSN1

PC52
10KB_0603_5%_ERTJ1VR103J
2 1 9 12 FB_CPU 1 2

2
47P_0603_50V8J PC53 CCV FB
PR82 1 2 11 10 CCI_CPU PC54 0.22U_0603_16V7K
C 499_0402_1% REF CCI C

1 2 PC55 0.22U_0603_16V7K 39 21 DH2_CPU


6,20 PM_DPRSLPVR DPRSLPVR DH2 Choke
1 2 40 20 BST2_CPU
4,19 H_DPRSTP# DPRSTP BST2

1
PR83 0_0402_5%
1 2 3 22 LX2_CPU PR86 0_0402_5% Choke PR85
5 PSI# PSI LX2
PR84 0_0402_5% 1 2 0_0402_5%
+3VS 2 24 DL2_CPU
PWRGD DL2 @ PR87 1K_0402_1% @ PC56 1000P_0402_50V7K

2
2

0_0603_5%
1 23 1 2 1 2 CPU_VCC_SENSE
CLKEN PGND2

PR88
2

38 14 CSP2_CPU PR91 3.65K_0402_1%


PR89 @ PR90 SHDN CSP2
1 2 1 2
2K_0402_1% 2K_0402_1% 5 15 CSN2_CPU

1
VRHOT CSN2 @ PR95 PR92 100_0402_5%

2
4 13 3K_0603_1%
1

POUT GNDS PC57


1 2 1 2

BSTM2_CPU
6,14,20 VGATE

4700P_0402_25V7K
4700P_0402_25V7K

1
TP @ PR94
3K_0603_1% PC58
14 CLK_ENABLE# MAX8770GTL+_TQFN40 470P_0603_50V8J
41

2
PC59
1 2 1 2
28 VR_ON 1 2
PR97
1
2

PR98 20K_0402_1% CPU_B+

0.22U_0603_16V7K
1
0_0402_5% @ PR99 +3VS 2

PC60
10K_0402_5%
1

PR100

2
PR101 100_0402_5%

2200P_0402_50V7K
10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK

0.1U_0603_25V7K
1

VRHOT

56_0402_5% PQ16

1
PC62
SI7686DP-T1-E3_SO8
1

PC61

PC63

PC64

PC65
B B
2

5 VSSSENSE VSSSENSE

2
PR103
PR104 0_0603_5%
1

10K_0402_5% 1 2 4
1 2 PR105
28 POUT
10_0402_5%
2

PL8
PC66 0.36UH_PCMC104T-R36MN1R17_30A_20%
2

3
2
1
0.1U_0402_16V7K 2 1
1

Rdcr

1
Choke

4.7_1206_5%
PR106
5
6
7
8

5
6
7
8

2.1K_0402_1%
FDS6676AS_SO8

FDS6676AS_SO8

1
R1

D
D
D
D

D
D
D
D

2
PQ17

PQ18

PR107
680P_0402_50V7K
Valley current limit threshold : 19.5mV ~ 25.5mV R2 R3

G
S
S
S

S
S
S

PC67

2
1
4
3
2
1

4
3
2
1
PR108 PH4
3.48K_0402_1% NTC 10KB_0603_5%_ERTJ1VR103J
Rcs = Rdcr*(R2+R3)/(R1+R2+R3)

2
1 2 1 2
2 CSN1_CPU

2 CSN2_CPU
2 CSP1_CPU

2 CSP2_CPU

Ivalley = VIlim / Rcs


1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1 2
1000P_0402_50V7K
PC69

PC71

PR109 0_0402_5% PC68 0.22U_0603_16V7K


A
Iload = Ivalley + delta IL/2 A
PC70

PC72

1 2
1

Choke

Per phase, Iocp=23.279A~30.288A Ceq


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/01/16 Deciphered Date 2008/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JDW50/JDY70 LA3771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 42 of 44
5 4 3 2 1
5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1


for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
EC GPIO pin modify EC GPIO pin modify
D
1 0.1 ==> 0.2 8 DPST_PWM net modify 3/19
D

clk frequency error pin error 0.1 ==> 0.2 14 Q48,Q49,Q50 pin error
2
EC add a GPIO pin EC GPIO pin modify 0.1 ==> 0.2 16 del DPST_PWM net from North Bridge
3
follow ICL50 follow ICL50 20 CRT_DET# net modify
4 0.1 ==> 0.2

5 EMI request EMI request 0.1 ==> 0.2 24 Add R477, R748

6 ESD request ESD request 0.1 ==> 0.2 25 reserve D30,D31

7 test test 0.1 ==> 0.2 26 reserve MINI1_LED#

8 Blue LED issue Blue LED issue 0.1 ==> 0.2 27 BT_LED# schematic modify

9 EC GPIO pin modify EC GPIO pin modify 0.1 ==> 0.2 28 EC GPIO pin define modify

C
10 ESD request ESD request 0.1 ==> 0.2 29 reserve C895 to C904
C

11 easy short easy short 0.1 ==> 0.2 30 change J1,J2 jumper sybmol to 0603 symbol

12 ESD request ESD request 0.1 ==> 0.2 31 Add R751,R752,R753

13 chip issue chip issue 0.1 ==> 0.2 32 U31 chip update version

14 voice too small modify gain value 0.1 ==> 0.2 32 change R472 form 39k to 30k ohm

15 EMI request EMI request 0.1 ==> 0.2 32 change R523,R524,R50,R38,R26,R28 for 0 ohm to bead

16 DFX request DFX request 0.1 ==> 0.2 33 del pjp15

17 Wireless Lan S4 fail Wireless Lan fail 0.2 ==> 0.3 26 del R756, add R757

18 Wireless Lan S4 fail Wireless Lan fail 0.2 ==> 0.3 26 change C906,C907 from 22u_1206 to 10u_0805

Lead Free non LF==>Lead Free 0.2 ==> 0.3 17 change C211,C510,C514,C216,C508,C515
19
B KBC version update KBC version update 0.2 ==> 0.3 28 reserve 0.1u at pin 124 B
20
SPDIF udpate SPDIF circuit udpate 0.2 ==> 0.3 32 add q59,q60
21
DFX DFX issue 0.2 ==> 0.3 32 del JP13
22
23
24
25
26
27
28
29
A A

30

Compal Electronics, Inc.


Title
PIR (HW)
Size Document Number Rev
JDW50 LA-3771P 0.2

Date: Monday, April 16, 2007 Sheet 43 of 44

5 4 3 2 1
5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1


for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
Charger IC damage issue Charger IC damage issue Change PR161 from SD013220B80 to SD013200A80
D
1 0.2 40
D

Charger IC damage issue Charger IC damage issue 0.2 40 Change PR162 from SD013180A80 to SD013200A80
2
Charger IC damage issue Charger IC damage issue 0.2 40 Add PR197 SD013200A80
3
Charger IC damage issue Charger IC damage issue 0.2 40 Add PR198 SD013220B80
4
5 Charger IC damage issue Charger IC damage issue 0.2 40 Add PC133 SE026473K80

6 Add EMI solution in charger. Add EMI solution in charger. 0.3 40 Add PR199 SD001470B80(S RES 1/4 4.7 1206 5%). 04/01/07 PVT

7 Add EMI solution in charger. Add EMI solution in charger. 0.3 40 Add PC163 SE074681K80(S CER CAP 680P 50V K X7R 0402) 04/01/07 PVT

8
9

C
10 C

11
12
13
14
15
16
17
18

19
B B
20
21
22
23
24
25
26
27
28
29
A A

30

Compal Electronics, Inc.


Title
PIR (PWR)
Size Document Number Rev
HCW51 LA-3121P 0.2

Date: Monday, April 16, 2007 Sheet 44 of 44

5 4 3 2 1

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