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HomeELECTRONICSVLSI/VHDL/VerilogCoreProjectsALookAheadClockGatingBasedonAutoGatedFlipFlops2014

A LOOK AHEAD CLOCK GATING BASED ON AUTO GATED FLIP FLOPS 2014

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Clockgatingisveryusefulforreducingthepowerconsumedbydigitalsystems.
Threegatingmethodsareknown.Themostpopularissynthesisbased,deriving
clock enabling signals based on the logic of the underlying system. It Subject

unfortunately leaves the majority of the clock pulses driving the flipflops (FFs) Re: A Look Ahead Clock Gating Based on Auto Gated Flip Flops 2014
redundant. A datadriven method stops most of those and yields higher power
savings, but its implementation is complex and application dependent. A third Message

methodcalledautogatedFFs(AGFF)issimplebutyieldsrelativelysmallpower
savings.ThispaperpresentsanovelmethodcalledLookAheadClockGating(LACG),whichcombinesallthethree.LACGcomputes
theclockenablingsignalsofeachFFonecycleaheadoftime,basedonthepresentcycledataofthoseFFsonwhichitdepends.It
avoidsthetighttimingconstraintsofAGFFanddatadrivenbyallottingafullclockcycleforthecomputationoftheenablingsignalsand
their propagation. A closedform model characterizing the power saving per FF is presented. It is based on datatoclock toggling
probabilities,capacitanceparametersandFFsfanin.Themodelimpliesabreakevencurve,dividingtheFFsspaceintotworegionsof
positiveandnegativegatingreturnoninvestment.WhilethemajorityoftheFFsfallinthepositiveregionandhenceshouldbegated,
those falling in the negative region should not. Experimentation on industryscale data showed 22.6% reduction of the clock power,
translatedto12.5%powerreductionoftheentiresystem.

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