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IJSRD - International Journal for Scientific Research & Development| Vol.

4, Issue 05, 2016 | ISSN (online): 2321-0613

VLSI Implementation of Aging-Aware Reliable Multiplier with Adaptive


Hold Logic
Joy Chakravorty1 Pravin Ku. Tiwari2
1,2
Department of Electronics & Communication Engineering
1,2
Takshshila Inst. of Engg. & Tech, Jabalpur (M.P.)
Abstract Multipliers are among the most critical arithmetic aging effect is overdesign including such things as guard-
functional units. The overall performance of the Digital banding and gate over sizing; however, this approach can be
multiplier systems depends on throughput of the multiplier. very pessimistic and area and power inefficient.
The negative bias temperature instability effect occurs when To avoid this problem, many NBTI-aware
a pMOS transistor is under negative bias (Vgs = Vdd), methodologies have been proposed. An NBTI aware
increasing the threshold voltage of a pMOS transistor and technology mapping technique was proposed into guarantee
reducing the multiplier speed. Similarly, positive bias the performance of the circuit during its lifetime.In an
temperature instability occurs when an nMOS transistor is NBTI-aware sleep transistor was designed to reduce the
under positive bias. Both effects degrade the speed of the aging effects on pMOS sleep-transistors, and the lifetime
transistor and in the long term, the system may be fail due to stability of the power-gated circuits under consideration was
timing violations. Therefore, it is required to design reliable improved. Wu and Marculescu proposed a point logic
high-performance multipliers. In this paper, we implement an restructuring and pin reordering method, which is based on
agingaware multiplier design with a novel adaptive hold detecting functional symmetries and transistor stacking
logic (AHL) circuit. The multiplier is able to provide the effects. They also proposed an NBTI optimization method
higher throughput through the variable latency and can adjust that considered path sensitization. In dynamic voltage
the adaptive hold logic (AHL) circuit to lessen performance scaling and body-basing techniques were proposed to reduce
degradation that is due to the aging effect. The proposed power or extend circuit life.
design can be applied to the column bypass multiplier. A short path activation function algorithm was
Key words: Aging Effect, Adaptive Hold Logic (AHL), proposed into improve the accuracy of the hold logic and to
Negative Bias Temperature Instability (NBTI), Positive Bias optimize the performance of the variable-latency circuit.
Temperature Instability (PBTI), Reliable Multiplier, This paper has been organized in the following way, we
Variable Latency propose an aging-aware reliable multiplier design with novel
adaptive hold logic (AHL) circuit. The multiplier is based
I. INTRODUCTION on the variable-latency technique and can adjust the AHL
Digital multipliers are among the most critical arithmetic circuit to achieve reliable operation under the influence of
functional units in many applications, such as the Fourier NBTI and PBTI effects. To be specific, the contributions of
transform, discrete cosine transforms, and digital filtering. this paper are summarized as follows:
The through put of these applications depends on 1) Novel variable-latency multiplier architecture with an
multipliers, if the multipliers are too slow, the performance AHL circuit. The AHL circuit can decide whether the
of entire circuits will be reduced. Furthermore, negative bias input patterns require one or two cycles and can adjust
temperature instability (NBTI) occurs when a Pmos the judging criteria to ensure that there is minimum
transistor is under negative bias (Vgs = Vdd). In this performance degradation after considerable aging
situation, the interaction between inversion layer holes and occurs.
hydrogen-passivated Si atoms breaks the SiH bond 2) Comprehensive analysis and comparison of the
generated during the oxidation process, generating H or H2 multipliers performance under different cycle periods
molecules. When these molecules diffuse away, interface to show the effectiveness of our proposed architecture.
traps are left. The accumulated interface traps between 3) An aging-aware reliable multiplier design method that
silicon and the gate oxide interface result in increased is suitable for large multipliers. Although the
threshold voltage (Vth), reducing the circuit switching speed. experiment is performed in 16- and 32-bit multipliers,
When the biased voltage is removed, the reverse reaction our proposed architecture can be easily extended to
occurs, reducing the NBTI effect. However, the reverse large designs;
reaction does not eliminate all the interface traps generated
during the stress phase, and Vth is increased in the long term.
Hence, it is important to design a reliable high performance
multiplier. The corresponding effect on an nMOS transistor
is positive bias temperature instability (PBTI), which occurs
when an nMOS transistor is under positive bias. Compared
with the NBTI effect, the PBTI effect is much smaller on
oxide/polygate transistors, and therefore is usually ignored.
However, for high-k/metal-gate nMOS transistors with
significant charge trapping, the PBTI effect can no longer be
ignored. In fact, it has been shown that the PBTI effect is
more significant than the NBTI effect on 32-nm high-
k/metal-gate processes. A traditional method to mitigate the Fig. 1: 4x4 Nomal AM

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VLSI Implementation of Aging-Aware Reliable Multiplier with Adaptive Hold Logic
(IJSRD/Vol. 4/Issue 05/2016/098)

row-bypassing multiplier, the input signal of the AHL in the


architecture with the column-bypassing multiplier is the
multiplicand, whereas that of the row-bypassing multiplier
is the multiplicator. Razor flip-flops can be used to detect
whether timing violations occur before the next input pattern
arrives.

Fig. 2: 4x4 Row- Bypassing Multiplier Fig. 3: Razor flip flops

II. PROPOSED AGING-AWARE MULTIPLIER III. SYNTHESIS AND SIMULATION RESULTS


This section details the proposed aging-aware reliable
multiplier design. It introduces the overall architecture and
the functions of each component and also describes how to
design AHL that adjusts the circuit when significant aging
occurs.
A. Proposed Architecture
Fig. shows our proposed aging-aware multiplier
architecture, which includes two m-bit inputs (m is a
positive number), one 2m-bit output, one column- or row-
bypassing multiplier, 2m 1-bit Razor flip-flops, and an AHL
circuit.

Fig. 4: Top Module

Fig. 3: Proposed architecture (md-multiplicand; mr -


multiplicator).
The inputs of the row-bypassing multiplier are the
symbols in the parentheses. In the proposed architecture, the Fig. 5: Top module simulation waveform
column- and row-bypassing multipliers can be examined by
the number of zeros in either the multiplicand or
multiplicator to predict whether the operation requires one
cycle or two cycles to complete. When input patterns are
random, the number of zeros and ones in the multiplicat or
and multiplicand follows a normal distribution, as shown in
Figs. 9 and 10. Therefore, using the number of zeros or
ones as the judging criteria results in similar outcomes.
Hence, the two aging-aware multipliers can be implemented
using similar architecture, and the difference between the
two bypassing multipliers lies in the input signals of the
AHL. According to the bypassing selection in the column or
Fig. 6:Razor simulation waveform

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VLSI Implementation of Aging-Aware Reliable Multiplier with Adaptive Hold Logic
(IJSRD/Vol. 4/Issue 05/2016/098)

Fig. 7: Aging aware multiplier simulation waveform

IV. CONCLUSION
This paper proposed an aging-aware variable latency
multiplier design with the AHL. The multiplier is able to
adjust the AHL to mitigate performance degradation due to
increased delay. our proposed variable latency multipliers
have less performance degradation because variable latency
multipliers have less timing waste, but traditional multipliers
need to consider the degradation caused by both the BTI
effect and electro migration and use the worst case delay as
the cycle period. The experimental results show that our
proposed architecture with 4x4 multiplication with CLA as
last stage instead of Normal RCA adder it will decrease the
delay and improve the performance compared with previous
designs.

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