Pydi Bahubalindruni 1 .
Abstract This paper proposes a low power ring oscillator by combining cur-
rent starving technique with negative skewed delay approach. This design has
shown an improvement of more than 50% in the power delay product com-
pared to the state of the art techniques. Circuit simulations are carried out in
standard 65 nm technology. The proposed circuit has shown a robust perfor-
mance against temperature and voltage variation within 10%. Therefore this
circuit can find potential applications in IoT devices and RFID tags operating
from 10 MHz to 1 GHz.
Keywords low power ring oscillator, current starving, power delay product,
Negative skewed delay.
1 Introduction
Low power circuits are essential realizers of IoT systems. Oscillators are one
of the main blocks that act as the heart of the system. Among different ar-
chitectures of on-chip oscillators, ring oscillators (ROs) are preferred because
of their simplicity and less area. They are important blocks in many appli-
cations, such as, RFID tags, wireless sensor networks (WSN) and biomedical
circuits and systems. With the advancement of technology scaling, low power
RO with power consumption in the order of nano-watt is required for above
applications.
Significant work has been done in addressing the low power requirements
of RO. The most common low-power technique is current starving (CS) Wen
et al. (2013),Panyai and Thanachayanont (2012),Tabesh and Hamedi-Hagh
1 IIIT Delhi, Okhla Phase-3, Near Govindpuri Metro Station, Delhi-110020
E-mail: bpganga@iiitd.ac.in, rajendra15106@iiitd.ac.in
2 INESC TEC and Faculty of Engineering, University of Porto,
Campus FEUP, Rua Dr. Roberto Frias, 378, 4200-465 Porto, Portugal
E-mail: iman.kianpoor@gmail.com
2 Rajendra Nayak 1 , Iman Kianpoor 2 Pydi Bahubalindruni 1 .
2 Circuit Design
is given by,
1
f= (1)
2 n td
where n is the number of stages, td is the delay of each stage. By varying the
current( I) through the inverter, td can be varied and hence the frequency. I is
dictated by the aspect ratios of both PMOS and NMOS in the inverter stage.
To obtain high speed opertion while maintaining low power consumption, the
aspect ratio of PMOS to NMOS should be maintained between 1.4 - 1.7 HE
et al. (2006). In order to obtain optimum power and frequency, this ratio is
maintained throughout the paper for all the RO techniques to ensure similar
operating condition for a fair comparison of performance.
The dynamic power dissipation of RO is given by,
2
P ower = CL Vdd f (2)
where is the activity factor, CL is the sum of output load capacitance of each
inverter stage, Vdd is the supply voltage and f is the frequency of oscillation.
is 1 for general circuits. Power consumption is directly proportional to the
frequency as per (2). Therefore, this architecture needs to be further modified
to guarantee low power consumption, while operating at higher frequencies.
Vdd
Vout
same). In this configuration, as the bias current is low, in the order of nano-
ampere range, the transistors operate near sub-threshold region and hence low
power consumption can be achieved Harrison and Charles (2003). By varying
Ib , the time to charge and discharge the gate capacitance of the very next
stage can be varied and consequently the frequency. As expected from (2),
lower frequency means lesser is the power consumption and vice versa. In
order to achieve further low power consumption, Ib should be kept as low as
possible. However, it imposes limitation on the frequency of operation. This
design can not guarantee optimum PDP as it trades off between frequency of
operation and the power consumption. To improve the PDP, frequency has to
be improved without compromising power consumption by employing novel
circuit design techniques.
Vdd Vdd
Vout
Min1 Min2 Min3 Min4 Min5 Min6 Min7
number of transitions are higher, this topology shows higher power consump-
tion as compared to conventional RO (Fig.1).
Vdd
Vdd
Vout
Min1 Min2 Min3 Min4 Min5 Min6 Min7
Vdd Vdd
Vout
Min1 Min2 Min3 Min4 Min5 Min6 Min7
Vdd Vdd
Vout
Min1 Min2 Min3 Min4 Min5 Min6 Min7
that over a wide range of temperature, proposed technique has shown a robust
performance. In addition, the PDP is very low compared to other techniques
thereby ensuring better FOM.
10-1
Conventional
CS
NMOS skewed
PMOS skewed
NMOS skewed CS
10-2 PMOS skewed CS
PDP ( W.s)
10-3
10-4
0 20 40 60 80 100
o
Temp. ( C)
PMOS skewed CS
Amplitude (V)
1 0.92
0.5
0
0 2 4 6 8
Time (ns)
NMOS skewed CS
Amplitude (V)
1
0.96
0.5
0
0 2 4 6 8
Time (ns)
Fig. 8: Proposed ring oscillator output from both PMOS skewed CS and NMOS
skewed CS.
Table 1: Comparison with other designs when same aspect ratio is considered.
Design No. Work Description Technology (nm) Vdd (V) PDP (W*s)
1 7-Stage Ring 65 1.0 0.00403
2 CS 65 1.0 0.00144
3 PMOS skewed 65 1.0 0.00422
4 NMOS skewed 65 1.0 0.00457
5 Proposed NMOS skewed CS 65 1.0 0.00108
6 Proposed PMOS skewed CS 65 1.0 0.00067
4 Conclusions
Acknowledgements Authors would also like to thank prof. Joao Goes for his valuable
contributions. This work is funded by early career research grant ECR/2017/000931.
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