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# EXPERIMENT - 10

## TOOLS: Xilinx ISE Design Software

METHODOLOGY: Behavioral

THEORY: UP COUNTER- a 3-bit counter capable of counting from 0 to 7. The clock inputs
of the three flip-flops are connected in cascade. The T input of each flip-flop is connected to a
constant 1, which means that the state of the flip-flop will be toggled at each active edge (here, it
is positive edge) of its clock. We assume that the purpose of this circuit is to count the number of
pulses that occur on the primary input called Clock. Thus the clock input of the first flip-flop is
connected to the Clock line. The other two flip-flops have their clock inputs driven by the Q
output of the preceding flip-flop. Therefore, they toggle their states whenever the preceding flip-
flop changes its state from Q = 1 to Q = 0, which results in a positive edge of the Q signal.

## DOWN COUNTER- a down-counter which counts in the sequence 0, 7, 6, 5, 4, 3, 2, 1, 0, 7, and

so on. The modified circuit is shown in Figure 3. Here the clock inputs of the second and third
flip-flops are driven by the Q outputs of the preceding stages, rather than by the Q outputs.

UP/DOWN COUNTER- Both Synchronous and Asynchronous counters are capable of counting
Up or counting Down, but their is another more Universal type of counter that can count
in both directions either Up or Down depending on the state of their input control pin and these
are known as Bidirectional Counters.also known as Up/Down counters, are capable of counting
in either direction through any given count sequence and they can be reversed at any point within
their count sequence by using an additional control input.

## CIRCUIT DIAGRAM AND TRUTH TABLE:

Fig 10.1 Block diagram of 3 bit down asynchronous counter

## Fig 10.3 Block diagram of 3 bit up/down asynchronous counter

Fig 10.4 Block diagram of 3 bit down synchronous counter

## Fig 10.6 Block diagram of 3 bit up/down synchronous counter

VERILOG CODE:

UP COUNTER-
module UPCOUNT1(input clk,input rst,output q2,q1,q0);

tf t1(1,clk,rst,q0);

tf t2(1,~q0,rst,q1);

tf t3(1,~q1,rst,q2);

endmodule

initial

## always @(posedge clk1,posedge rst)

begin if (rst==1)

q=1'b0;

else if (t==0)

## q=q; else q=~q; end

endmodule

RTL:
Fig 10.7 RTL of 3 bit UP counter

TEST BENCH:
initial begin

// Initialize Inputs

rst = 1;#100;

rst = 0;#100;

end

initial clk=1'b0;

always

#100 clk=~clk;

endmodule

OUTPUT-

## Fig 10.8 output of 3 bit up counter

2-DOWN COUNTER:
module DOWNCOUNT(input clk,input rst,output q2,q1,q0);

tf t1(1,clk,rst,q0);

tf t2(1,q0,rst,q1);

tf t3(1,q1,rst,q2);

endmodule

initial

## always @(posedge clk1,posedge rst)

begin if (rst==1)

endmodule

RTL-

## Fig 10.9 RTL of 3 bit down counter

TEST BENCH-
initial begin

// Initialize Inputs

rst = 0;#1600;

rst = 1;#100;

always

#100 clk=~clk;

endmodule

OUTPUT WAVEFORM-

## Fig 10.10 output of 3 bit down counter

3-UP/DOWN COUNTER-
module upcount(input clk,input rst, input s,output q2,output q1,output q0);

wire w1,w2;

muxx m1(q0,~q0,s,w1);

muxx m2(q1,~q1,s,w2);

tff t1(1,clk,rst,q0);
tff t2(1,w1,rst,q1);

tff t3(1,w2,rst,q2);

endmodule

initial

q=1'b0;

begin

if(rst1==1)

begin

q=1'b0;

end

else if (t==0)

begin

q=q;

end

else if (t==1)

end

endmodule

## module muxx(input i0,input i1,input s,output y);

assign y=(~s&i0)|(s&i1);

endmodule
RTL:

TEST BENCH-
initial begin

## rst = 0;s = 0;#1600; rst = 0;s = 1;#1600; end

initial clk=1'b0;

endmodule

OUTPUT WAVEFORM-

.
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