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EMT 363 VLSI DESIGN

LOW POWER DESIGN (WEEK 9,10,11)

LOW POWER DESIGN


EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Outlines
Power and Energy
Dynamic Power
Static Power
Low Power Design
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Introduction (p/g 143, Weste)


EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Power dissipation in CMOS circuits


comes from 2 components
(i)
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Power dissipation in CMOS circuits (contd)


comes from 2 components
(ii)
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Power and Energy


Power is drawn from a voltage source attached to the VDD pin(s) of a
chip.

Instantaneous Power: P(t ) iDD (t )VDD


T T
E P(t )dt iDD (t )VDD dt
Energy: 0 0

T
E 1
Average Power: Pavg iDD (t )VDD dt
T T 0
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Dynamic Power
Dynamic power is required to charge and discharge load capacitances
when transistors switch.

One cycle involves a rising and falling output.


On rising output, charge Q = CVDD is required VDD
iDD(t)
On falling output, charge is dumped to GND
This repeats Tfsw times
C
over an interval of T fsw
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Dynamic Power (Contd)


T
1
Pdynamic iDD (t )VDD dt
T 0
T
VDD

T 0 iDD (t )dt VDD
iDD(t)
VDD
TfswCVDD
T C
CVDD f sw
2 fsw
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Activity Factor (p/g 144, Weste)


A powerful and easy way to reduce power consumption
Turning OFF unused logic blocks by stopping the clock clock gating

Can be estimated by calculating the switching probability


EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Activity Factor

Switching probability
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Activity Factor
Suppose the system clock frequency = f
Let fsw = af, where a = activity factor
If the signal is a clock, a = 1
If the signal switches once per cycle, a =
Dynamic gates:
Switch either 0 or 2 times per cycle, a =
Static gates:
Depends on design, but typically a = 0.1

Dynamic power: Pdynamic aCVDD 2 f


EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Exercise
Dynamic power is defined as

Pdynamic aCVDD 2 f

Answer the followings:


1) Derive the above equation
2) By using a CMOS inverter (with driving a load capacitance), discuss
the effect of dynamic power in electronic circuit
Exercise
Solution
Exercise
Given
(a) Predict the probability, P(X) and the activity factor, X for X.
Assume P(A) = P(B) = P(C) = .
(b) If the circuit area of X is 1.2 mm2 and the circuit operates in 2
GHz with 0.9 V supply with average switching capacitance of
450 pF/mm2, evaluate the dynamic power consumed by X.
use information provided in (a) to answer the question.
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Short Circuit Current


When transistors switch, both nMOS and pMOS networks may be
momentarily ON at once
Leads to a blip of short circuit current.
< 10% of dynamic power if rise/fall times are comparable for input
and output
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Example
200 Mtransistor chip
20M logic transistors
Average width: 12 l
180M memory transistors
Average width: 4 l
1.2 V 100 nm process
Cg = 2 fF/mm
Static CMOS logic gates: activity factor = 0.1
Memory arrays: activity factor = 0.05 (many banks!)
Estimate dynamic power consumption per MHz. Neglect wire
capacitance and short-circuit current.
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Solution

Clogic 20 10 12l 0.05mm / l 2 fF / mm 24nF


6

Cmem 180 10 4l 0.05m m / l 2 fF / m m 72nF


6

Pdynamic 0.1Clogic 0.05Cmem 1.2 f 8.6 mW/MHz


2
Example (weste p/g: 143)
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Static Power
Static power is consumed even when chip is quiescent.
Ratioed circuits burn power in fight between ON transistors
Leakage draws power from nominally OFF devices

Vgs Vt
Vds

I ds I ds 0e nvT
1 e
vT

Vt Vt 0 Vds s Vsb s
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Low Power Design


Reduce dynamic power
a: clock gating, sleep mode
C: small transistors (esp. on clock), short wires
VDD: lowest suitable voltage
f: lowest suitable frequency
Reduce static power
Selectively use ratioed circuits
Selectively use low Vt devices
Leakage reduction:
stacked devices, body bias, low temperature
EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)

Example (weste p/g: 155)

What is the total power consumption?


EMT 363 VLSI DESIGN
LOW POWER DESIGN (WEEK 9,10,11)