Naksha Technologies Inc ATPG Methodology Document

Naksha Technologies Inc
1313 North Milpitas Blvd #165-C

Millpitas, CA 95035
ATPG Methodology
Rev 2.4
Author: Prasad
Document History
Revision History Changes
15/4/05
Naksha Technologies Inc. Confidential 1 ATPG Flow

1 Introduction
SCAN testing is a structural methodology to detect manufacturing defects by using

Automatic Test Pattern Generation (ATPG) to calculate the test vectors. The SCAN
test is split into two parts:
1. Shift Mode
In the shift mode, all sequential elements are connected in such a way that they
operate as one or more shift registers. The shift chain is used to control the circuit
and observe the result.
2. Capture Mode
In the capture mode, the values stored in the sequential elements during shift are
propagated from the source via the functional logic to the sink. Each pad or
sequential element in the SCAN chain is able to operate as source as well as sink.
The ATPG tool is able to detect following different manufacturing defects.

1. Functional defects - Stuck at 0/1
2. At-speed defects - Slow transistor resistive bridges
3. IDDQ defects - CMOS stuck-on stuck-open
Our methodology flow is related to SAF (Stuck at Fault ) and TF ( Transition Fault )
defects.
Here we follow a stand alone group/block approach for the functional design, the
same we follow for the Scan design. The SCAN Design in each group is treated
separately and has stand alone scan chains for every Group. The final scan chain
connections, and the porting the group level scan_in/scan_out to the Chip level i/os are
done manually early in the RTL.
The number of scan chains is limited by the number of scan-ins and scan-outs that
can be accommodated on the chip. Also by considering requirements and limitations
of the chip testers , the scan chain length is fixed to around 5000. The scan in and
scan out are shared between the functional pins.
It is important for module designers to take the DFT into considerations since managing
DFT issues during logic design is a refined methodology with many benefits. The DFT
guidelines and rules must be understood and applied by design engineers thoroughly.
Each Group or the Block will be synthesized , scan stitched, clock-gated to reduce the
power and integrated to the chip Top. And also the DFT gating will be done in the PADs
to work in the proper direction in the SCAN mode.
TetraMAX is the automatic test pattern generation (ATPG) tool used in our DFT
methodology flow, to generate SAF ( Stuck at Fault ) pattern, TF(Transition fault)
Patterns and RS ( Ram sequential ) patterns.

The first cut synthesized, scan stitched, netlist is used to start with the ATPG run.
ATPG will be run at block/Group level and DRC warning to be checked and the Test
coverage (block level TC should be 99+ ) to be reviewed
As the blocks get stabilizes , start with the Chip level ATPG with the netlist from the
back-end ( place-and-route ). Start with SAF Patterns, using the default engine that is
the Basic-Scan, then migrate to most complex algorithms (fast Sequential , Full
Sequential ) with in the ATPG tool to improve the Test Coverage number.
Before Generating the Full SAF scan patterns , better to write out the Chain test
pattern in the verilog Format to do the Back annotated Timing simulation. First start
with the FAST corner and then to SLOW corner. The above process will make sure
the scan shift chain structure is OK.
Before the Tapeout Simulate around 10 to 100 parallel patterns (with 10 to 15 shifts) in
FAST corner first and then in SLOW corner and also make sure that the STA is OK in the
Scan mode, especially in the Fast corner.
Then generate TF patterns to check the transition faults by using system mode approach.
In the system clock mode, initiates launching logic value using a normal system
clock. It exercises target transition faults and then captures the new logic values with
a subsequent system clock.
All these SAF and TF vectors will be sending to the ATE ( Automatic Test
equipment ) and will be tested on the silicon. Some times we need to debug the
Potentially Faulty node in the silicon which will cause the Mismatches at the
tester .The Fail Log from the Tester ( ATE ) will vary with Tester to Tester. Hence the
basic information from the Tester needs to be translated to Failure Data File Format,
which can be given to the ATPG Tool to get the potentially faulty node information.

2 SCAN Design Grouping
SCAN Design in each block is treated separately and has stand alone scan chains for
every block. The final scan chain connections, and the porting the group level
scan_in/scan_out to the Chip level i/os are done manually in RTL. The scan methodology
is full scan and scan flip-flop types is multiplexed flip-flop. But few blocks like tap
controller and boundary scan registers are excluded from SCAN, since separate functional
test are used to target faults on those blocks.
The following diagram gives an example of the group level classification, for the latest
project, falcon.
Chip_Top
C1 C2 C3 C4 C5 C6 C7
Xfi, frm, qdl ul2 Yfi, Map, Emi, Cru, jdu

fmc, cfi, bfi dmp, smc Hic,
dfr, dmc Pcu,
xtn
C8 C9 C10 C11 C12 C14 C15
fft ift Dma, Pwz, Dfu0, Dsi_co agt,

Pio, Afi, Dfu1 agr
pdx Rmc,
teq
C1, C2, C4, C5, C8, C9, C11, C12 are per quad basis and hence have 2 instances at top level
C12 has 2 dfus and hence 4 instances at top level
C3, C6, C7, C10, C14 are global blocks and hence 1 instance each at top level

The scan insertion and the scan stitching is done separately, per Group basis. Top
level integration, top level scan chain connections, and scan I/O direction gating are
done early at RTL level. Group level netlist reading and linking are done while Top
level scan synthesis.
The Following Diagram gives the SCAN-ATPG flow.
Verilog pattern file
Timimg Simulation
using w/ w/o SDF

3 ATPG Flow
TetraMAX is the automatic test pattern generation (ATPG) tool used in our DFT
methodology flow, to generate SAF ( Stuck at Fault ) pattern, TF(transition fault)
Patterns and RS ( Ram sequential ) patterns, by making use of the three different
ATPG algorithms like Basic-Scan, Fast-Sequential, and Full-Sequential ( Details are
there at Chapter 8 )
Following gives the basic ATPG flow using TetraMax.
Verify the pattern Test the pattern

with Timing in the ATE

Points to be taken cared just before running the ATPG
1. Pre-process the Netlist from the synthesis tool to trace all the scan chains correctly. For
example, some of the analog pins like vcxo_clk may not be connected in the netlist.
So we need to connect them in the appropriate place.
2. Make sure that the ATPG Lib model matches with the Verilog Lib model.
3. Macros like RAMs, ROMs, PLL, and RFs should be modeled such a way that, it
must not create any issues like reduction in test coverage and simulation mismatches
while gate level verification.
SRAMs in the SMS ( Star memory system from Virag) were equipped
with internal scan muxes (Asynchronous write-through modes), thus were
modeled as empty feed-through with assign statements. We must use the
ATPG model written out by the VIRAG lib compiler during ATPG Tool.
Others (RF) were modeled as black boxes or empty boxes and used with
bypass collars that were active only during scan in the bist wrapper
logic. Hence we can model RF as empty boxes to do the ATPG in the
safe side.
SMS fuse boxes, ROMs and Other Analog Blocks were modeled as black
boxes.
The port level pin vcxo_clk comes to the PLL block, feed-through as
pll_vcxo_clk and driving many scan elements in the design. Hence PLL
was modeled as empty boxes with chip level crystal clock vcxo_clk
feed-throughs with assign statements.
Following are the some points to be noted during the first phase of ATPG run
1. Set the pin constrains to make all the scan clocks and asynchronous Resets
controllable from port level ( clock mux selection , reset mux selection , PLL
bypass etc )
2. Set the Port level pin with appropriate value to make SMS SRAMs asynchronous
feed thorough
3. Set the pin constrains to make the boundary scan logic transparent at all the pins.
This can be achieved by resetting the JTAG controller by forcing active value to
JTAG_TRST_L.

4. Set the bonding Option pins with appropriate values.
5. Make sure that all the scan chains traces properly.
6. Make sure that there no unconnected nets at instantiation of reference module,

provided the reference module has the same input port and uses internally. The
ATPG DRC section will come up with error/warning (B12).
7. Make sure that there are NO bus contentions during any of the test procedure
(load_unload or setup) in the STIL. If so drive Z during that time, and rerun the
ATPG.
8. Make sure that all the latches in the design are transparent while SHIFTING.
9. Make sure that Number of scan cells traced by to the ATPG tool in each chain
correlates with the synthesis tool scan length.
10. Make sure that NO shadow registers are identified by the ATPG Tool.
11. Make sure that Lockup Latches are present where ever there is scan clock mixing.
12. More over, read carefully the all warnings generated by ATPG tools and find
out the explanation for the same.

4 DFT Requirements during Front End Design
It is important for module designers to take the DFT into considerations since managing
DFT issues during logic design is a refined methodology with many benefits. The DFT
guidelines and rules must be understood and applied by design engineers thoroughly.
4.1.1 Scan length and number of scan chains
Scan chain length and design scanability dominate the ATPG run time and the length
of test vector as well as the production test time. To make a test time as short as
possible, two main points are extremely helpful. One is to have a full scan design and
second is to implement as many scan chains as possible.
Of course, the number of scan chains is limited by the number of scan in and scan out
that we can be accommodated on the chip. The scan in and scan out can be shared
between the functional pins. Also consider requirements and limitations of your chip
testers on deciding the max-scan length and number of chains. In previous project, the
scan chain length is around 5000 and 34 chains.
After identifying the total number of scan chains, we need to allocate chains to each
group.
4.1.2 Scan control signals
Two dedicated pins are used for SCAN.
1. SCAN_ENABLE
SCAN_ENABLE is the signal select between Shift Mode ( SE = 1 ) and

Capture Mode ( SE = 0) .
In the shift mode, all sequential elements are connected in such a way
that they operate as one or more shift registers. The shift chain is used
to control the circuit and observe the result.
In the capture mode, the values stored in the sequential elements

during shift are propagated from Q/QN pin of the scanable sequential
elements via combinational logic to the D pin of the next scan flop.
Normally the Scan enable goes to each and every sequential scan
cells to switch between the shift and capture mode. And also used at
the Clock gating cell to get controllability for the clock during Scan-
Shift.
The port level SCAN_ENABLE pin is gated with SCAN_MODE to generate the
internal scan_enable signal which is fed to all the Scan flops in the design. Hence we
can share the same pin in functional mode.

2. SCAN_MODE
SCAN_MODE is the static signal which is tied to HIGH during SCAN. This signal is mainly used for
fixing DFT violations.
4.1.3 Port for test I/O
The following guidelines apply to the selection of existing ports to be used for any
test purpose.
1. A port that already feeds the input of a flip-flop in a scan chain is the best
port to redefine as a scan chain input.
2. A port that already comes directly from the output of a flip-flop in a scan
chain is the best port to redefine as a scan chain output.
3. A three-state output can be redefined as a bidirectional port and used in

input mode while TEST is asserted.
4. A standard output can be redefined as a bidirectional port and used in input

mode while TEST is asserted.
5. An input port that feeds directly into the input of a flip-flop in a scan chain
can be redefined as a shared port.
6. An output port that comes directly from the output of a flip-flop in a scan
chain can be redefined as a bidirectional port and used in input mode while
TEST is asserted.
7. An output port that is a derived clock or pass-through clock can be

redefined as a bidirectional port and used in input mode while TEST is
asserted.
8. An input port that has a small amount of fan-out before entering a flip-flop
is a good choice to be redefined for use as a test-related input while TEST is
asserted.
9. Special High speed timing critical ports should be avoided when we choose
the test ports.
After getting number of scan chains for the whole chip, we need to allocate to each
block/Group. The test input and test output ports need to be added at the RTL level
itself, depends on the number of chains in each Group ( ex C1 , C2 ,C3 etc).
The output enables of the identified test ports to be gated with SCAN_MODE ( if
BIDI or TRISTATE ) and need to be ported to the appropriate groups test ports.

4.1.4 Bidirectional Port Controls
Force scan chain outputs that use bidirectional or three-state ports into an output
mode while shifting scan chains in ATPG test mode, using the top-level control pin
scan_enable or scan_mode.
It is better to force all bidirectional ports which are not used as scan out port, to input
mode while shifting scan chains in ATPG test mode, using a top-level port as control
scan enable. If we are not doing so, we should ensure that the ATE should drive Z
while shifting the scan chains.
Force scan chain outputs that use bidirectional or three-state ports into an
Output mode while shifting scan chains in ATPG test mode, using a top-level port
(usually SCAN_ENABLE)
4.1.5 RAM and ROM Bypass during ATPG
Since RAMs and ROMs are tested via BIST (achieving very high fault coverage),
they do not need to be tested and fault graded by ATPG tools. But even when RAM is
made fully testable (via BIST logic), a significant reduction in test coverage of the
surrounding logic may result (shadow logic).
SMS - SRAM were equipped with internal scan muxes (Asynchronous write-through
modes), thus Data In is directly feed through to the Data out. This can be achieved by
asserting the port level signal called AWT of SRAM. By doing so the RAM shadow
logic can be covered using ATPG. But during RAM sequential ATPG we do not need
to bypass the memory. ATPG tool will pulse the ram control signals through the
preceding scan cells by shifting through the Scan cells. Hence the AWT of the SRAM
is gated in the following way.
AWT signals to SRAM = SCAN_MODE & SEQ_ATPG

Note : SEQ_ATPG is the Port level signal
ATPG (SCAN_MODE = 1)
BASIC ATPG RAM SEQ ATPG
(SEQ_ATPG = 1) (SEQ_ATPG = 0)
AWT signals to all the SMS-SRAMs will AWT signals to all the SMS-SRAMs will be De-
be asserted , there by Data Input will asserted , there by RAM will work normally.
feed through to the Data Output.
For the ATPG Tool RAM will be like a ATPG Tool will Toggle the RAM address
WIRE, and hence the Shadow logic of and Control signals by shifting the Data
the SRAMs can be covered. through the Scan chains. And Capture the
Data from the Data Output port of the
SRAMs.

Following gives the Gating of the TEST signal inside the SMS to make the SRAMs
ATPG friendly.
RFs (register Files) were bypassed externally using the scan control signal
SCAN_MODE or SCAN_ENABLE. Minimum extra flops are added to get
observability on the shadow logic between the RAM control/address generation
Registers and the RAM input Pins.
Test signal to the LOGIC VISION bist controller is
RF_scan_mode = SCAN_MODE & (SEQ_ATPG | SCAN_ENABLE)
4.1.6 Clock/Async Reset Control
While in ATPG test mode, ensure that clocks and asynchronous set or reset signals
come from primary inputs. Bypass internally generated clocks or asynchronous set or
reset signals using test control signal SCAN_MODE. Basically constrain the clock
path such a way that, Clean Port level clock reaches the Clock pi of all the SCAN
elements. The clock gating used to save the power should be controlled using
SCAN_ENABLE, such that pure clean port level clock will reach the clock pin of the
scan elements at least during SCAN SHIFT.
Use the SCAN_MODE control signal to multiplex the power-on reset signal so that it
comes from an existing reset input or some other primary input during SCAN. And
also use the SCAN_MODE control signal to block the power-on reset source so that it
has no effect during test.

Avoid using bidirectional clocks or asynchronous set or reset ports while in ATPG
test mode. If design supports bidirectional clocks or asynchronous set or reset ports,
force them to operate as unidirectional ports while in ATPG test mode.

5 DFT Requirements during SCAN Synthesis
The DFT at module level includes scan insertion and test design rule check. The
guidelines include two main domains: general scan-based test design rules and some
special considerations for chip test integration.
We will use the first cut synthesis netlist to start the ATPG run. We will run ATPG at
block level and check the DRC warning and review the Test coverage (block level TC
should be 99+ ) to make the DRC error/warning debug easier .
5.1.1 Shadow Register Analysis
A shadow register is not in the scan chain, but is loaded when its master register in the
scan chain is loaded, by the same clock or by a separate clock. A shadow register is
considered a control point but not an observe point. During the DRC analysis,
TetraMAX searches for non scan cells that can be considered shadow registers. ATPG
tool will try to cover the Shadow register through other scan cells.
If the master scan cell and the shadow register are in different clock domain, there is a
possibility of capturing a wrong data. So it is better NOT to use this approach. So we
need to tell the tool to NOT to identify shadow register in the design and try to cover
them by this approach (set drc -NO Shadows ). Hence Tool will try to cover this
registers with normal ATPG methods.
5.1.2 Transparent Latches
A transparent latch is a latch in which the enable line can be asserted so that data
passes through it without activating any of the designs defined clocks. During the
rule checking process, TetraMAX automatically determines the location of all latches
in the design and checks to see whether the latches can be made transparent. For
ATPG, you must be able to disconnect the latch control from any clock ports.
When latches are transparent, it is easier for TetraMAX to detect faults around those
latches. When latches are not transparent, you might need to use a Full-Sequential
ATPG run to get good fault coverage around those latches.
We need to make sure that all the Latches in the design should be transparent during
ATPG. If not, we need to add some extra test logic to make them Transparent.
5.1.3 Power reduction and Clock Gating
Now a ways Most of the Libraries support DFT friendly Clock gating cells. We must use
SCAN_ENABLE as the gating signal while ATPG..
Gated clock = Latched (SCAN_ENABLE | Functional Enable) & clock
During the SHIFT scan_enable will be 1b1 and clean clock will fed to the CLK pin of
the scan cells, and During CAPTURE ATPG tool will assert the Functional Enable node
( by shifting the Appropriate bits through scan cells during previous scan-load ) to feed
clean clock to the scan cells. So By doing so shadow logic of the Functional Enable
generation logic will also get tested or covered.
5.1.4 Clock mixing and Edge mixing using lockup latch
Use a single clock tree to clock all flip-flops in the same scan chain. If the design
contains multiple clock trees, insert resynchronization latches (lockup latches) in the
scan data path between scan cell flip-flops that use different clock sources.
Treat each clock tree as a separate clock source in designs that have a single clock
input port but multiple clock tree distributions. Under these conditions, treat each
clock tree as a separate clock source. Insert resynchronization latches between scan
cells where the clock source switches from one clock tree to another.
If possible, clock all flip-flops on the same scan chain on the same clock edge. If this
is not possible, then group together all flip-flops that are clocked on the trailing clock
edge and place them at the front of the scan chain (closest to the scan chain input) and
group together all flip-flops that are clocked on the leading clock edge and place them
closest to the scan chain output.

6 DFT Requirements during Layout
6.1.1 Scan clock Skew and Tree balancing
There are NO strict Requirements of the Tree Balancing because of the Following Reason
1. Clock will be balanced in the functional Mode, and the same will apply to the SCAN.
2. LOCKUP Latch at the Clock-Crossing will take care issues during SHIFT .
3. We constrain the ATPG Tool such a way that Multiple clock domain CAPTURE Patterns
are NOT generated.
4. Scan Enable Timing is relaxed since we are using system_mode TF patterns.
6.1.2 Sanity checks in Layout Netlist
1. Make sure that the scan Re-ordering not messed between Two different clock
domains scan cells and between same domain scan cells with different Edges
in each chain.
2. Make sure that the Lockup latches are present at edge mixing and clock
mixing.
3. Make sure that there are NO shadow register in the design.
4. Make sure there are NO un resolved components in the design ( Special layout
cells like Antenna and power pads should me modeled properly )

7 Fault models , Categories and Classes
7.1.1 Fault model
1. Stuck
The best known fault class is the stuck-at fault class. The fault model covers
functional defects generated by shorts or opens in the device interconnect.
Stuck-At 1: The terminal of the gate is stuck at its high value.

Stuck-At 0: The terminal of the gate is stuck at its low value.
Stuck Open: The terminal of the gate is not connected at all (high
impedance).
2. Transition
The transition delay fault model enhances the stuck-at fault model by introducing a time
assessment. It is possible to launch the transition by a change in one or more sources
(registers or pads).
slow-to-rise transition: The device is defective, because it is too slow to

toggle a node from 0 to 1 in a given time frame
slow-to-fall transition: The device is defective, because it is too slow to

toggle a node from1 to 0 in a given time frame.
7.1.2 Fault Categories and Classes
There are five higher-level fault categories containing a total of 11 lower-level

fault classes, organized as follows:
DT: detected
DR: detected robustly
DS: detected by simulation
DI: detected by implication
PT: possibly detected
AP: ATPG untestable-possibly detected
NP: not analyzed-possibly detected
UD: undetectable
UU: undetectable unused
UT: undetectable tied
UB: undetectable blocked
UR: undetectable redundant
AU: ATPG untestable
AN: ATPG untestable-not detected
ND: not detected
NC: not controlled
NO: not observed
7.1.3 Test coverage
Test coverage gives the most meaningful measure of test pattern quality and is the
default coverage reported in the fault summary report. Test coverage is
Defined as the percentage of detected faults out of detectable faults, as follows:
Test coverage = ( detected faults / detectable faults )
i.e., ( DT + PT/2 ) / ( All faults UD )
Note : we must collapse all equivalent faults before calculating TC to get an accurate number
To improve performance, most ATPG tools identify all equivalent faults and use only
a single member of each fault equivalence class. For example, a stuck-at-0 fault on
the input pin of a BUF gate is equivalent to the stuck-at-0_fault on the output pin of
the same gate. The collapsed fault list would contain only one of those faults which is
termed the "primary" fault. For a given set of equivalent faults, the choice of which
one is the primary fault is controlled by the equivalency analysis and is not
predictable. So it is better to Report for the TC after collapsing the equivalent Faults.
The AU and ND categories are the main cause of the reduction in the Test coverage.
The AU (ATPG untestable) category of faults contains faults that are not necessarily
intrinsically untestable, but are untestable using ATPG methods. These faults cannot
be proven to be undetectable and might be testable using other methods (for example,
functional tests). The AU category has one class, AN (ATPG untestable, not detected).
In AU, the first category is a fault cannot be controlled or observed because setting up
the required patterns would violate a PI or ATPG constraint. Second one is the Faults
associated with non scan sequential devices (latches and flip-flops) are not testable
with simple ATPG methods.
The ND (not detected) category is a fault was not completed or was aborted.
Incomplete or aborted analyses could be caused by the default ATPG iteration limits
or by designs that are too complex for the ATPG algorithm to solve. The ND category
has two classes. First one NC (not controlled) class contains faults that the ATPG
algorithm could not control to achieve both a logic 0 and a logic 1 state. Nodes that
are always at an X state are classified as NC because ATPG cannot achieve either a
logic 0 or a logic 1. Second one is the NO (not observed) class contains faults that
could be controlled, but could not be propagated into a scan chain cell or to a design
output for observation. Usually a design begins with most faults in the NC class. As
the ATPG algorithm progresses, the faults are moved to the NO class and then to a DS

or other class. If too many NC or NO faults remain after test pattern generation, you
can try to increase the test coverage by increasing the ATPG effort level.
So the only way to increase TC is by reducing the ND and AU faults by
1. Use of the complex algorithms like fast sequential Atpg engine (set atpg
-capture_cycles n) and full sequential Atpg Engine (set atpg -full_seq_atpg).
2. Increase the ATPG effort level ( set drc -abort_limit )
We need to try with the default engine that is the Basic-Scan first, and then check the
results. If test coverage is not high enough, we can then try Fast-Sequential to detect
the remaining faults (read back only the AU and ND faults from previous run ) and
check the results again. If the results are still not good enough, you can then try Full-
Sequential. We should always do the Atpg run in this order since the fast sequential
and the full sequential runs are too complex and time consuming and also vector
count will increase drastically.
Note : we can use full sequential engine only for Stuck at fault ( SAF) ATPG.

8 Stuck at Fault Pattern Generation and Methodology
The Basic SAF patterns are created with the simple ATPG method with a single Capture
cycle Basic-Scan ATPG Engine operates as a full-scan, combinational-only ATPG tool. In
other words, to get high test coverage, all the sequential elements need to be scan
elements.
The Basic SAF sequence is start with SETUP where all the clocks will be OFF and all the
necessary PI constrains will be forced and SCAN_ENABLE will be LOW and ALL the
BIDI will be forced to Z.
Next step is to assert SCAN_ENABLE and load the scan chains. The Timing of single
SHIFT cycle is as follows
Single SHIFT cycle in SAF
1. Force Scan input
2. Measure Scan Output
3. Pulse the shift clock
Time period 100ns
@ 40 ns SO compared
@ 0 ns SI 50 ns 80 ns 100 ns
forced
We need to repeat the shift cycle as many number of scan cells in the longest chain.

Capture in Basic SAF
Capture in the Basic SAF will be done with a single tester cycle.
Force Primary inputs
Measure the Primary output
Pulse the Capture clock
Time period 100ns
@ 40 ns PO compared
@ 0 ns PI 50 ns 80 ns 100 ns
forced
Scan_clock
Scan enable
SETUP DUMMY LOAD_UNLOAD DUMMY CAPTURE
Preample cycle to take Pulse # longest SCAN_ENABLE to

care of the Assertion of chain length to settle down to the
SCAN_ENABLE load all the inactive state
chains

If test coverage is not high enough with the Basic SAF patterns, we need to enable the
Fast-Sequential engine. In this mode, multiple capture (set atpg -capture_cycles 2 -
10 ) procedures are allowed between scan load and scan unload, allowing data to be
propagated through nonscan sequential elements in the design.
Still Complex ATPG engine is the Full-Sequential ATPG, like Fast-Sequential ATPG,
supports multiple capture cycles (set atpg -full_seq_atpg that is capture cycle more
than 10 ) between scan load and unload, thus increasing test coverage in partial-scan
designs. However, clock and reset signals to the nonscan elements do not need to be
controllable at the primary inputs and there is no specific limit on the number of
capture cycles used between scan loads and unload
Sequence starts with the Basic-Scan algorithm first to detect most of the faults,
followed by the more computationally intensive algorithms (Fast-Sequential and Full-
Sequential) to detect the remaining faults.

9 Transition Fault patterns and its methodology
9.1.1 TF generation modes
In Two ways we can implement the transition fault pattern generation.
1. Last shift
In the last_shift mode, TetraMAX initiates launching a logic value in the last scan
load cycle when the scan_enable is active (in scan shift mode). It exercises target
transition faults and then captures new logic values in a system clock cycle when
the scan enable is inactive (in capture mode).
It is based on the Basic-Scan ATPG engine. It generates only Basic-Scan patterns

(using a single capture procedure between scan load and scan unload). Here the
pattern generation is simple but we need to really take care of the
scan_enable timing, at minimum a single cycle scan enable is required for
proper operation.
2. System Clock
In the system_clock mode, initiates launching a logic value using a normal system
clock. It exercises target transition faults and then captures the new logic values
with a subsequent system clock.

The system_clock mode is based on the Fast-Sequential ATPG engine. It always
generates Fast-Sequential patterns. Here the Launch is through the D pin of the scan
flops.
We followed the system_mode approach since it is very difficult to meet the timing of
the scan_enable in this multi million design chip. For System clock mode, we may
need postamble cycle after load_unload. This is due to the fact that the 2 consecutive
cycles after load_unload will run at-speed. And, we can put an extra cycle after
load_unload for the scan enable to settle down to the inactive state.
9.1.2 STIL file modification
1. Define At speed waveform in the STIL file
Time period 14ns
0 ns 7 ns 14 ns
WaveformTable "_14ns_WFT_" {
Period '14ns';
Waveforms {
"_default_In_Timing_" { 0 { '0ns' D; } }
"_default_In_Timing_" { 1 { '0ns' U; } }
"_default_In_Timing_" { Z { '0ns' Z; } }
"_default_In_Timing_" { N { '0ns' N; } }
"_default_Clk0_Timing_" { P { '0ns' D; '7ns' U; '14ns' D;}}
"_default_Out_Timing_" { X { '0ns' X; } }
"_default_Out_Timing_" { H { '0ns' X; '6ns' H; } }
"_default_Out_Timing_" { T { '0ns' X; '6ns' T; } }
"_default_Out_Timing_" { L { '0ns' X; '6ns' L; } }
}
2. Use the At speed waveform for All Capture clocks with a single cycle capture
definition in the STIL file.
"capture_EXT_CLK" {
W "_7ns_WFT_";
F { "HIC_RD_L"=1; "SCAN_MODE"=1;"SEQ_ATPG"=1;}
V { "_pi"=\r333 # ; "_po"=\r322 #;"EXT_CLK"=P;}
}
9.1.3 Script modification
We need to do some modification in the SAF ATPG scripts to make at speed ATPG
scripts.
1. Because the narrow window from the cycle boundary to the capture event is
often too small for the IO paths, all faults on the pad input logic need to be
masked for at-speed transition delay testing.
set delay -NOPI_changes
2. The high load on the output pads, due to the tester environment, also requires
the masking of any fault in the pad output logic for at-speed transition delay
testing as well.
Add PO Masks All
3. First of all, for at-speed SCAN testing, the design should be designed without
any multicycle paths, this means all timing paths fit into one clock cycle.
ATPG tools assume that all paths are single cycle. If Multi cycle paths are
already present in the design, try to remove the faults related to that block.
Ex: Remove Faults -Slow RF C1_Q0/sms_c1/u_sms_c1_sms
4. Try to give dummy cycle when ever scan enable switches ( after load_unload
and after the capture )
5. declare the BIDI pads as slow pads.

Add SLow Bidis -All
6. Enable the Fast sequential Engine by Setting the Capture depth to 2
Set Atpg -CApture_cycles 2
7. Use system_clock mode for generating the TF patterns and also Use the same
clock for launch and Capture.
set delay -launch_cycle system_clock

set delay -common_launch_capture_clock
8. Allows pattern generation using any single clock, including patterns where no
clock is used.
set drc -Clock Any
9. Set the fault model as transition
10. Save the Pattern also in BIN format along with the WGL, in case if we want to
use for diagnosis.

10 ATPG Patterns verification - sign- off
First start simulating the chain vector in FAST corner and followed by SLOW
corner.
Create a small set of patterns in TetraMAX for debugging before starting an

ATPG run for 100% coverage
set atpg -Pattern 10
run atpg
write patterns falcon_chain_par.v format
VERILOG_table -Parallel 10 -Last 0 -replace
Write Patterns falcon_par_10pat.v -FOrmat
VERILOG_table -Parallel 10 -replace -First 1 -Last 10
Set Atpg -CApture_cycles 4
set atpg -Abort_limit 1000
set atpg -Pattern -0
run atpg auto
Save patterns in the TetraMAX proprietary binary format for later reuse.
Other output formats may not contain all the information that TetraMAX
needs to write to another format later on or to diagnose the TF vectors
Simulate around 10 to 100 parallel patterns (with 10 to 15 shifts) in FAST

corner first and then in SLOW corner.
Make sure that STA is OK in SCAN mode ( mainly on FAST corner Hold
violations, but also in the SLOW corner )

11 Tester Failure Diagnosis
11.1.1 Failure Data File
The Basic and important information is the Failure Data File, which need to be fed to the
ATPG Tool (TetraMax) to identify the potential faulty nodes.
The Format of the Failure information File is as follows

Failed_Pattern_number port [cell_pos] [(Expected_data/Measured_data)]
Where:
Failed_Pattern_number is the pattern number where the failure occurred
(starting with pattern # 0).
port is the name of the output port where the failing measure was detected.
Cell_pos is the cell position for the failing scan cell assuming the failure
occurred during a scan shift cycle. This is equal to the number of tester shift
cycles that have occurred since the start of the current scan out process.
Expected_data/measured_data are optional comments.
11.1.2 Fail Log from Tester
The Fail Log from the Tester will vary with Tester to Tester. Hence the basic information
from the Tester need to be translated to Failure Data File Format, which can be given
to the ATPG Tool to get the Potentially faulty nodes.
Following gives some of examples of the Fail Log from the Tester.
1. Type 1
bme_atpg Fail unit 1
bme_atpg200pat_min 54936 to 790799 *FAIL*
atpg_0_min
LOW FAIL = .
HIGH FAIL = /

TRISTATE FAIL = *
SX:NO COMPARE = -
Vector Loop Cycle FAILED DUT PIN
104958 0 50023 .DEBUG_6
126924 0 71989 .DEBUG_6
139188 0 84253 /DEBUG_6
141550 0 86615 .DEBUG_6
141552 0 86617 /DEBUG_6
Type2
Datalog report
12/09/2004 14:48:31
Prog Name: IK22401_A1.3_FT.xls
Job Name: CP1
Lot:
Operator: nakshafl
Test Mode: Engineering
Node Name: FLEX338
Part Type:
Channel map: Chan_site1
Environment:
Site Number:
Device#: 1

Number Site Test Name Pattern 1st Failed Cycle
Total Failed Cycles
<ATPG_TF2_NOM>
188 0 ATPG_TF2_NOM.0 viper_atpg_0_v7_tf (F) 3 1
PINS
Cycle Relative R
257701 257700 0 X
-> (P) H
257702 257701 0 X
-> (P) L
257703 257702 0 X
-> (P) L
257704 257703 0 H
-> (F) L
257705 257704 0 L
-> (P) L

11.1.3 Translation of Tester information
Normally the Basic Information from the Tester will be the Failed Cycle number ,
failed Pin name , Expected and /measured Value and the Vector name. We need to
understand the scan vector sequence to really debug the Pattern and the scan cell.
Basic Scan Operations
1. Setup
"test_setup" {
W "_default_WFT_";
V { "HIC_RD_L"=1; }
Setup Cycles = # of V cycles in the test_setup
2. Load/Unload
load_unload {
V { "SCAN_ENABLE" = 0; }
V { SCAN_ENABLE=1 "AFE_TXDATA[6]" = Z ; . }
Shift {
V { _si=#; _so=#; "AFE0_RXCLK" = P; "AFE1_RXCLK" = P;

"JTAG_TDCLK" = P; "MEM_CLKIN" = P; "RX_CLK" = P; "TX_CLK" = P;
"vcxo_clk" = P; "MDC" = P; }}
V { "SCAN_ENABLE" = 0; }
Dummy cycle where scan_enable kept Inactive for one cycle ( optional )
Assert Scan_enable (dummy preamble cycles for load/unload ) and off clocks
Shift # longest scan length times

1. Force Scan input
2. Measure Scan Output
3. Pulse the shift clock
De-assert scan enable (dummy postamble cycles for load/unload ) ( optional )
# of load/unload cycles = # of dummy preamble cycles for load/unload

+ # of longest chain
+ # of dummy postamble cycles
3. Capture
Force Primary inputs
Measure the Primary output
Pulse the Capture clock
capture can be three separate tester cycles, one for force_pi, one for measure_po, and
one for pulse clock
Also the capture can happen in a single tester cycle
"capture_EXT_CLK" {
W "_7ns_WFT_";
F { "EXT_CLK_SEL"=1; }
V { "_pi"=\r219 # ; "_po"=\r215 # ; "EXT_CLK"=P; }
But when ever we do transition ATPG, capture SHOULD be defined as a single cycle.
ATPG Tool will use the same Timing for LAUNCH and consecutive cycle will act as
CAPTURE.
"capture_EXT_CLK" {
W "_7ns_WFT_";
F { "EXT_CLK_SEL"=1; "EXT_VCLK_SEL"=1; }
V { "_pi"=\r219 # ; "_po"=\r215 # ; "EXT_CLK"=P; }

}
Capture cycles = # of V cycles in the capture procedure
Max_length = Number of scan cells found in longest chain in the design.
11.1.4 Failed Pattern calculation
Tester Cycles Per Pattern = ( # load/unload cycles + # capture cycles )

Where # of load/unload cycles = # of dummy preamble cycles for load/unload
+ # of longest chain
+ # of dummy postamble cycles
# capture cycles can vary depend on the test procedure file .
Formula for Calculating Failed Pattern is

Int (( Tester Cycle number -- Setup cycles )/( Tester Cycles Per Pattern )) - 1
We need to subtract 1 because first load/Unloand will only load the pattern , but the
second loand_unlaod on wards, it loads nth pattern and unloads (n-1)th pattern.
Formula for getting Scan cell ID number OR the Scan cell position is
( (Tester Cycle number -- Setup cycles ) % ( Tester Cycles Per Pattern ) )
There is an In-house script to generate automated tetramax script and also to do the
debug . The Pointer to the script is
/home/ASIC_Release/$PROJECT/atpg_lib/atpg_fa.pl
USAGE: atpg_fa.pl -p <project_name> -t <tester_result_file> -o <group_offsets>
[-a <atpg_dir>] [-w <wgl_dir>] [-d <def_dir>] [-c] [-s] [-v]
[-m shift_period] [-n capture_period]
[-i setup_cycles] [-j dummy shift cycles ]
<group_offsets> File in which ofset of groups and xy_unit is given.
<atpg_dir> Dir where ATPG patterns are created or placed for the tester.
<wgl_dir> Dir where WGL files are kept for the tester, if different from atpg_dir.
<def_dir> Dir where DEF files are kept for the chip, if non standard.
-c For the patterns, which also contain the chain test.(like Jaguar).
-s ATPG patterns with signle cycle capture.
-u Transition ATPG patterns
-v Don't run tetra-Max
Ex : atpg_fa.pl -p bme -t v5_tester_report -a /home/ASIC_REV_Release-

OLD/bme_RevC/ate/patterns/TF/v5.0 -i 6 -j 2 -v -u
11.1.5 Diagnosis Procedure
1. Load the Design and Libraries
2. Restore the same environment to generate the patterns
3. Add all the faults
4. Set appropriate Fault model and correct capture depth.
5. Read the pattern in BIN format and set as External pattern
6. Run diagnosis using the Failure Data file.
11.1.6 Things To Keep In Mind
1. For scan out failures, take extra care in identifying the cell position; can be
affected by:
- Preamble/Postamble cycles
- setup can carry more number of cycles
- Non-clocking capture cycles can exist
- ATPG pattern numbering starts with 0
2. Restore the environment to EXACTLY what it was when TEST mode was
entered and "run drc" executed. If anything in the environment changes, it
might cause invalid results

3. If failure was observed during PO measure, then failure detected belongs to
current ATPG
pattern
4. If failure was observed during scan shifting, then recall that load/unload of scan
chains is
overlapped, so the failure being detected now occurred during the previous ATPG
pattern.
5. Always try to save the pattern in both Binary and WGL format. Transition pattern
debug needs the patterns to be in BIN format.

12 Recommendations and checklist
1. Insert the scan chain at module level and connect them on the
chip level. Do an entire plan for all scan in and scan out signals.
2. Test clock must be controlled dedicatedly to avoid potential

timing problems especially when multiple clock domains exist.
3. Async resets must be controlled properly and bypass using a

chips port level pin .
4. Handle bi-directional IOs and tri-state buses carefully. Proper

configuration and control must be included in the test plan.
5. It is important for module designers to take the DFT into

considerations since managing DFT issues during logic design is a
refined methodology with many benefits. The DFT guidelines and
rules must be understood and applied by design engineers
thoroughly.
6. Read carefully the reports generated by DFT or ATPG tools to

look for potential problems in your design or more opportunities
of improving the test coverage
7. Ensure that clocks and asynchronous set/reset signals come from

a primary input. Bypass clock dividers. Control the gated clocks
with Scan_enable Bypass phase-locked loops (PLLs) as clock
sources.
8. Provide complete control of clock paths to scan chain flip-flops.
If a clock passes through a MUX, constrain the select line of the
MUX to a constant value. If a clock passes through a
combinational gate, constrain the other inputs of the gate to a
constant value. Pass clock signals directly through JTAG I/O
cells without passing through a MUX, unless the MUX control
can be constrained. Avoid using bidirectional clocks and
asynchronous set/reset ports.
9. Do not allow an open path from a pulsed input signal (clock or

asynchronous set/reset) to a data-capture input of a sequential
device. Do not allow a path from a pulsed input to both the data
input and the clock of the same flip-flop. Do not allow a path

from a pulsed input to both the data input and the asynchronous
set or reset input of the same flip-flop.
10. For multi-driver nets, ensure that only one driver is enabled
during the shifting of scan chains.
11. Force all bidirectional ports to input mode while shifting scan
chains, using a top-level port as control.
12. Force scan chain outputs that use bidirectional or three-state

ports into output mode while shifting scan chains, using a top-
level port (usually SCAN_ENABLE).
13. Use a single clock tree to clock all flip-flops in the same scan
chain.
14. Treat each clock tree as a separate clock source in designs that
have a single clock input port but multiple clock tree
distributions.
15. Use the same clock edge for all flip-flops in the same scan chain.

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Naksha Technologies Inc

1313 North Milpitas Blvd #165-C

Naksha Technologies Inc. Confidential 1 ATPG Flow

SCAN testing is a structural methodology to detect manufacturing defects by using

The ATPG tool is able to detect following different manufacturing defects.

Naksha Technologies Inc. Confidential 2 ATPG Flow

Naksha Technologies Inc. Confidential 3 ATPG Flow

Xfi, frm, qdl ul2 Yfi, Map, Emi, Cru, jdu

C8 C9 C10 C11 C12 C14 C15

fft ift Dma, Pwz, Dfu0, Dsi_co agt,

Naksha Technologies Inc. Confidential 4 ATPG Flow

The Following Diagram gives the SCAN-ATPG flow.

Verilog pattern file

Naksha Technologies Inc. Confidential 5 ATPG Flow

Following gives the basic ATPG flow using TetraMax.

Verify the pattern Test the pattern

Naksha Technologies Inc. Confidential 6 ATPG Flow

Naksha Technologies Inc. Confidential 7 ATPG Flow

5. Make sure that all the scan chains traces properly.

6. Make sure that there no unconnected nets at instantiation of reference module,

Naksha Technologies Inc. Confidential 8 ATPG Flow

4.1.1 Scan length and number of scan chains

4.1.2 Scan control signals

Two dedicated pins are used for SCAN.

SCAN_ENABLE is the signal select between Shift Mode ( SE = 1 ) and

In the capture mode, the values stored in the sequential elements

Naksha Technologies Inc. Confidential 9 ATPG Flow

4.1.3 Port for test I/O

3. A three-state output can be redefined as a bidirectional port and used in

4. A standard output can be redefined as a bidirectional port and used in input

7. An output port that is a derived clock or pass-through clock can be

Naksha Technologies Inc. Confidential 10 ATPG Flow

4.1.5 RAM and ROM Bypass during ATPG

AWT signals to SRAM = SCAN_MODE & SEQ_ATPG

Naksha Technologies Inc. Confidential 11 ATPG Flow

Test signal to the LOGIC VISION bist controller is

RF_scan_mode = SCAN_MODE & (SEQ_ATPG | SCAN_ENABLE)

4.1.6 Clock/Async Reset Control

Naksha Technologies Inc. Confidential 12 ATPG Flow

Naksha Technologies Inc. Confidential 13 ATPG Flow

5.1.1 Shadow Register Analysis

5.1.2 Transparent Latches

5.1.3 Power reduction and Clock Gating

5.1.4 Clock mixing and Edge mixing using lockup latch

Naksha Technologies Inc. Confidential 15 ATPG Flow

6.1.1 Scan clock Skew and Tree balancing

4. Scan Enable Timing is relaxed since we are using system_mode TF patterns.

6.1.2 Sanity checks in Layout Netlist

3. Make sure that there are NO shadow register in the design.

Naksha Technologies Inc. Confidential 16 ATPG Flow

7.1.1 Fault model

Stuck-At 1: The terminal of the gate is stuck at its high value.

slow-to-rise transition: The device is defective, because it is too slow to

slow-to-fall transition: The device is defective, because it is too slow to

There are five higher-level fault categories containing a total of 11 lower-level

7.1.3 Test coverage

Test coverage = ( detected faults / detectable faults )

i.e., ( DT + PT/2 ) / ( All faults UD )

Naksha Technologies Inc. Confidential 18 ATPG Flow

So the only way to increase TC is by reducing the ND and AU faults by

2. Increase the ATPG effort level ( set drc -abort_limit )

Naksha Technologies Inc. Confidential 19 ATPG Flow

bme_atpg200pat_min 54936 to 790799 FAIL