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A B C D E

MODEL NAME : QCL00_QCL20


PCB NO : LA-8241P
BOM P/N : 4619GP31L21 Inspiron DIS
1 4619GQ31L21 Inspiron UMA 1

4619GP31L01 Vostro DIS


4619GQ31L01 Vostro UMA

Dell / Compal Confidential


Schematic Document
Inspron A5 & Vostro 3560 (Intel Chief River)
2 2

Ivy Bridge(rPGA) + Panther Point(mainstream)


Discrete AMD Thames-XT
2012-02-01 X76@ : VRAM Group
3 46@ : for 46 level CH@ : Chelsea M2 3

@ : Nopop Component Rev: 1.0 SE@ : Seymour M2


CONN@ : Connector Component TH@ : Thames-XT
KB930@ : ENE KB930 Implemented MB Type BOM P/N Config DIS@ : Only for Discrete
KB9012@ : ENE KB9012 Implemented
EXP@ : Express Card Implemented
FFS@ : Only for Free Fall Sensor
VOS@ : Only for Vostro
4 INS@ : Only for Inspiron 4

UMA@ : Only for UMA


GCLK@ : Green CLK implemented Security Classification Compal Secret Data Compal Electronics, Inc.
AMP@ : External Amplifier implemented Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

KBBL@ : Keyboard Back Light implemented DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Date:
Document Number

LA-8241P
Wednesday, February 01, 2012 Sheet 1 of 56
Rev
1.0

A B C D E
A B C D E

Compal Confidential CPU XDP


Fan Control
Project Code : QCL00 / QCL20 P.25 Conn. P.6
File Name : LA-8241P 64M*16
VRAM * 4 Intel
DDR3 P.40

64bit
Ivy Bridge Memory Bus (DDR3)
1
Dual Channel DDRIII-DIMM X2 1

AMD PEG 3.0 x16


Processor BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
64M*16 Thames-XT / 1.5V DDR3 1333 MHz page 11,12
VRAM * 4
35W QC rPGA 988
Chelsea Pro
DDR3 P.41 64bit
24-26 W P.34~39 35W DC rPGA 988 8GB Max
P.5~10

FDI x8 DMI x4
100MHz 100MHz
2.7GT/s 5GB/s

SATA3.0 Port 0
SATA HDD Conn. FFS P.29
P.29
CRT Port 1
CRT Conn. Mini Card-2 (mSATA)
P.22 ( Full )
Port 5 P.32
2 LVDS Daughter board 2

LVDS Conn. Port 2


P.22
Intel SATA ODD Conn.
P.29
HDMI Panther Point
HDMI Conn. PCH HM77 USB 3.0 Port 1,2
P.23
USB 3.0 Conn. 1 P.33
Port 0,1 USB 3.0 Conn. 2 -( USB Charger )
USB2.0 USB2.0 Port 3,4
Port 2,3 USB 3.0 Conn. 3
Port 11 PCI-E x1
BGA 989 Balls USB 3.0 Conn. 4 P.32
Daughter board
Port 12
Port 3 Port 2 Port 1 Digital Camera P.22

Mini Card-1 Express Card Ethernet Port 4 Mini Card-1 (WLAN)


WLAN / BT4.0 RTL8105E (10/100) ( Half ) P.32

Half RTL8111F (10/100/1000) Daughter board


P.32 P.28 P.32
Port 10 Card Reader
RTS5139 P.32 3 in 1 Socket
3

34mm Slot RJ45 Daughter board 3

Port 8
Finger Print P.32
Daughter board Daughter board Daughter board HD Audio
P13~20

SPI Digital Mic.


RTC CKT. SPI ROM
P.13 4MB P.13 LPC Bus Audio Codec Headphone Jack
33MHz CX20672 P.30
Power On/Off CKT. SPI Mic. Jack
P.25 SPI ROM
2MB P.13
ENE KBC SPI
DC/DC Interface CKT. KB9012 / Amplifier
P.27
TPA3113D2 P.31 Int. Speaker R/L
KB930 page 24

PS/2 only for Vostro 3560


4 4

Int.KBD Touch Pad Dashboard SPI ROM


page 25 page 25
Button page
x3 32 128K page 26
reserved for KB930

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8241P
Date: Wednesday, February 01, 2012 Sheet 2 of 56
A B C D E
A B C D E

Compal Confidential
Project Code : QCL00 / QCL20
File Name : LA-8241P
1 1

8 pin-Hot Bar LS-8241P (Ins) LED/B


Led1 Led2
4 pin-Hot Bar
LS-8251P (Vos)
Led1 Led2 Led3
LS-8245P (Ins)
LS-8255P (Vos) SW1 SW1 SW2 SW3
LED/B

FFC FFC
4 pin 8 pin Lid (Vostro)

JFC
JPWR JLVDS
8 pin FFC
40 pin
4 pin 4 pin
2
LA-8241P M/B LS-8242P (Ins) IO/B 2

Lid (Inspiron) 80 pin


JBTB1
LS-8252P (Vos)
Touch Pad

L R
JFP
6 pin
JTP JCR2
Camera
4 pin
4 pin (Vostro)

TP Led (Vos)
TP Led (Ins)
LCD Panel
FFC 40 pin Wire
4 pin
4 pin-Hot Bar
3 JLED JCR1 3
Card Reader/B
4 pin 26
10 pin JEXP
LS-8243P (Ins)
26 pin
1 LS-8253P (Vos)
(Vostro) (Inspiron)

FFC
10 pin

LS-8244P (Ins)
LS-8254P (Vos) LED/B
Express Card
10 pin-Hot Bar
4 pin-Hot Bar
Led1 Led2 Led3 Led4
Finger Print/B
LS-8256P (Vos)
Top Side
4 4
Bottom Side

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 01, 2012 Sheet 3 of 56
A B C D E
A

Board ID Table for AD channel


Vcc 3.3V +/- 5% BOARD ID Table USB PORT# DESTINATION
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision 0 USB conn.1
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.1 1 USB conn.2 - Power Share
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.2
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.2 2 USB conn.3
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 0.3 0.2
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 0.3 0.3 3 USB conn.4
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6 1.0 1.0
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 1.0 4 MINI CARD-1 (WLAN)
QCL00 QCL20 QCL01 PCH
SMBUS Control Table
5 NC
Express Thermal VGA Thermal
SOURCE MINI1 MINI2 BATT SODIMM FFS VGA XDP Charger
Card Sensor Sensor 6 NC
EC_SMB_CK1
EC_SMB_DA1
KB9012
V V 7 NC
EC_SMB_CK2
EC_SMB_DA2
KB9012
V V 8 Finger Print
PCH_SML0CLK PCH Link
PCH_SML0DATA 9 NC
PCH_SML1CLK PCH
PCH_SML1DATA 10 Card Reader
MEM_SMBCLK
MEM_SMBDATA
PCH
V V V V V V 11 Express Card

12 Camera

CLKOUT DESTINATION 13 NC
1 1

PCI0 PCH_LOOPBACK

PCI1 EC LPC

PCI2 None
SATA DESTINATION PCI EXPRESS DESTINATION
PCI3 None
SATA0 HDD Lane 1 10/100/1G LAN
PCI4 None
SATA1 SSD Lane 2 MINI CARD-1 (WLAN)

SATA2 ODD Lane 3 Express Card


DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION
SATA3 None Lane 4 None
CLKOUT_PCIE0 10/100/1G LAN CLKOUTFLEX0 None
SATA4 None Lane 5 None
CLKOUT_PCIE1 MINI CARD-1 WLAN CLKOUTFLEX1 None
SATA5 None Lane 6 None
CLKOUT_PCIE2 Express Card CLKOUTFLEX2 None
Symbol Note : Lane 7 None
CLK CLKOUT_PCIE3 None CLKOUTFLEX3 None
Lane 8 None
CLKOUT_PCIE4 None : means Digital Ground

CLKOUT_PCIE5 None
: means Analog Ground
CLKOUT_PCIE6 None
Security Classification Compal Secret Data Compal Electronics, Inc.
CLKOUT_PCIE7 None Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
CLKOUT_PEG_B None AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-8241P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 01, 2012 Sheet 4 of 56
A
5 4 3 2 1

+VCCP

PEG_ICOMPI and RCOMPO signals should be shorted and routed

1
with - max length = 500 mils - typical impedance = 43 mohms JCPU1I
RC2 PEG_ICOMPO signals should be routed with - max length = 500 mils
24.9_0402_1% - typical impedance = 14.5 mohms
T35 F22

2
JCPU1A VSS161 VSS234
T34 F19
D PEG_COMP VSS162 VSS235 D
J22 T33 E30
PEG_ICOMPI VSS163 VSS236
J21 T32 E27
PEG_ICOMPO VSS164 VSS237
<15> DMI_CRX_PTX_N0 B27 H22 T31 E24
DMI_RX#[0] PEG_RCOMPO VSS165 VSS238
<15> DMI_CRX_PTX_N1 B25 T30 E21
DMI_RX#[1] VSS166 VSS239
<15> DMI_CRX_PTX_N2 A25 T29 E18
DMI_RX#[2] VSS167 VSS240
<15> DMI_CRX_PTX_N3 B24 K33 T28 E15
DMI_RX#[3] PEG_RX#[0] VSS168 VSS241
M35 T27 E13
PEG_RX#[1] VSS169 VSS242
<15> DMI_CRX_PTX_P0 B28 L34 T26 E10
DMI_RX[0] PEG_RX#[2] VSS170 VSS243
<15> DMI_CRX_PTX_P1 B26 J35 P9 E9
DMI_RX[1] PEG_RX#[3] VSS171 VSS244

DMI
<15> DMI_CRX_PTX_P2 A24 J32 P8 E8
DMI_RX[2] PEG_RX#[4] VSS172 VSS245
<15> DMI_CRX_PTX_P3 B23 H34 P6 E7
DMI_RX[3] PEG_RX#[5] VSS173 VSS246
PEG_RX#[6] H31 P5 VSS174 VSS247 E6
<15> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 P3 VSS175 VSS248 E5
E22 G30 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N7 <34> P2 E4
<15> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6 VSS176 VSS249
<15> DMI_CTX_PRX_N2 F21 DMI_TX#[2] PEG_RX#[9] F35 PEG_GTX_C_HRX_N6 <34> N35 VSS177 VSS250 E3
D21 E34 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N5 <34> N34 E2
<15> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N4 VSS178 VSS251
PEG_RX#[11] E32 PEG_GTX_C_HRX_N4 <34> N33 VSS179 VSS252 E1
G22 D33 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N3 <34> N32 D35
<15> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] VSS180 VSS253
D22 D31 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N2 <34> N31 D32
<15> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] VSS181 VSS254

PCI EXPRESS* - GRAPHICS


F20 B33 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N1 <34> N30 D29
<15> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] PEG_GTX_C_HRX_N0 VSS182 VSS255
<15> DMI_CTX_PRX_P3 C21 DMI_TX[3] PEG_RX#[15] C32 PEG_GTX_C_HRX_N0 <34> N29 VSS183 VSS256 D26
N28 VSS184 VSS257 D20
PEG_RX[0] J33 N27 VSS185 VSS258 D17
PEG_RX[1] L35 N26 VSS186 VSS259 C34
PEG_RX[2] K34 M34 VSS187 VSS260 C31
FDI_CTX_PRX_N0 A21 H35 L33 C28
<15> FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] VSS188 VSS261
<15> FDI_CTX_PRX_N1 H19 FDI0_TX#[1] PEG_RX[4] H32 L30 VSS189 VSS262 C27
FDI_CTX_PRX_N2 E19 G34 L27 C25
<15> FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI0_TX#[2] PEG_RX[5] VSS190 VSS263
F18 G31 L9 C23
<15>
<15>
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
B21
C20
FDI0_TX#[3]
FDI1_TX#[0] Intel(R) FDI PEG_RX[6]
PEG_RX[7] F33
F30 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P7 <34>
L8
L6
VSS191
VSS192
VSS264
VSS265 C10
C1
<15> FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI1_TX#[1] PEG_RX[8] PEG_GTX_C_HRX_P6 VSS193 VSS266
<15> FDI_CTX_PRX_N6 D18 FDI1_TX#[2] PEG_RX[9] E35 PEG_GTX_C_HRX_P6 <34> L5 VSS194 VSS267 B22
C FDI_CTX_PRX_N7 PEG_GTX_C_HRX_P5 C
E17 E33 L4 B19
<15> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
F32
D34
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
<34>
<34>
<34>
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
FDI_CTX_PRX_P0 A22 E31 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P2 <34> L1 B13
<15> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI0_TX[0] PEG_RX[13] PEG_GTX_C_HRX_P1 VSS198 VSS271
<15> FDI_CTX_PRX_P1 G19 FDI0_TX[1] PEG_RX[14] C33 PEG_GTX_C_HRX_P1 <34> K35 VSS199 VSS272 B11
FDI_CTX_PRX_P2 E20 B32 PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_P0 <34> K32 B9
<15> FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI0_TX[2] PEG_RX[15] VSS200 VSS273
<15> FDI_CTX_PRX_P3 G18 FDI0_TX[3] K29 VSS201 VSS274 B8
FDI_CTX_PRX_P4 B20 M29 K26 B7
<15> FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI1_TX[0] PEG_TX#[0] VSS202 VSS275
<15> FDI_CTX_PRX_P5 C19 M32 J34 B5
FDI_CTX_PRX_P6 FDI1_TX[1] PEG_TX#[1] VSS203 VSS276
<15> FDI_CTX_PRX_P6 D19 M31 J31 B3
FDI_CTX_PRX_P7 FDI1_TX[2] PEG_TX#[2] VSS204 VSS277
<15> FDI_CTX_PRX_P7 F17 L32 H33 B2
FDI1_TX[3] PEG_TX#[3] VSS205 VSS278
L29 H30 A35
FDI_FSYNC0 PEG_TX#[4] VSS206 VSS279
<15> FDI_FSYNC0 J18 K31 H27 A32
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] VSS207 VSS280
<15> FDI_FSYNC1 J17 K28 H24 A29
FDI1_FSYNC PEG_TX#[6] VSS208 VSS281
J30 H21 A26
FDI_INT PEG_TX#[7] PEG_HTX_GRX_N7 CC9 DIS@ 220nF_0402_16V7K VSS209 VSS282
<15> FDI_INT H20 J28 1 2 PEG_HTX_C_GRX_N7 <34> H18 A23
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 CC10 DIS@ 220nF_0402_16V7K VSS210 VSS283
H29 1 2 PEG_HTX_C_GRX_N6 <34> H15 A20
FDI_LSYNC0 PEG_TX#[9] PEG_HTX_GRX_N5 CC11 DIS@ 220nF_0402_16V7K VSS211 VSS284
<15> FDI_LSYNC0 J19 G27 1 2 PEG_HTX_C_GRX_N5 <34> H13 A3
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PEG_HTX_GRX_N4 CC12 DIS@ 220nF_0402_16V7K VSS212 VSS285
<15> FDI_LSYNC1 H17 E29 1 2 PEG_HTX_C_GRX_N4 <34> H10
FDI1_LSYNC PEG_TX#[11] PEG_HTX_GRX_N3 CC13 DIS@ 220nF_0402_16V7K VSS213
F27 1 2 PEG_HTX_C_GRX_N3 <34> H9
PEG_TX#[12] PEG_HTX_GRX_N2 CC14 DIS@ 220nF_0402_16V7K VSS214
D28 1 2 PEG_HTX_C_GRX_N2 <34> H8
+VCCP PEG_TX#[13] PEG_HTX_GRX_N1 CC15 DIS@ 220nF_0402_16V7K VSS215
F26 1 2 PEG_HTX_C_GRX_N1 <34> H7
PEG_TX#[14] PEG_HTX_GRX_N0 CC16 DIS@ 220nF_0402_16V7K VSS216
E25 1 2 PEG_HTX_C_GRX_N0 <34> H6
+EDP_COM PEG_TX#[15] VSS217
1 2 A18 H5
RC36 24.9_0402_1% eDP_COMPIO VSS218
A17 M28 H4
eDP_ICOMPO PEG_TX[0] VSS219
2 1 B16 M33 H3
RC158 10K_0402_5% eDP_HPD PEG_TX[1] VSS220
M30 H2
PEG_TX[2] VSS221
@ L31 H1
PEG_TX[3] VSS222
C15 L28 G35
eDP_AUX PEG_TX[4] VSS223
D15 K30 G32
eDP_AUX# PEG_TX[5] VSS224
eDP

K27 G29
PEG_TX[6] VSS225
J29 G26
B PEG_TX[7] PEG_HTX_GRX_P7 CC25 DIS@ 220nF_0402_16V7K VSS226 B
C17 J27 1 2 PEG_HTX_C_GRX_P7 <34> G23
eDP_TX[0] PEG_TX[8] PEG_HTX_GRX_P6 CC26 DIS@ 220nF_0402_16V7K VSS227
F16 H28 1 2 PEG_HTX_C_GRX_P6 <34> G20
eDP_TX[1] PEG_TX[9] PEG_HTX_GRX_P5 CC27 DIS@ 220nF_0402_16V7K VSS228
C16 G28 1 2 PEG_HTX_C_GRX_P5 <34> G17
eDP_TX[2] PEG_TX[10] PEG_HTX_GRX_P4 CC28 DIS@ 220nF_0402_16V7K VSS229
G15 E28 1 2 PEG_HTX_C_GRX_P4 <34> G11
eDP_TX[3] PEG_TX[11] PEG_HTX_GRX_P3 CC29 DIS@ 220nF_0402_16V7K VSS230
F28 1 2 PEG_HTX_C_GRX_P3 <34> F34
PEG_TX[12] PEG_HTX_GRX_P2 CC30 DIS@ 220nF_0402_16V7K VSS231
C18 D27 1 2 PEG_HTX_C_GRX_P2 <34> F31
eDP_TX#[0] PEG_TX[13] PEG_HTX_GRX_P1 CC31 DIS@ 220nF_0402_16V7K VSS232
E16 E26 1 2 PEG_HTX_C_GRX_P1 <34> F29
eDP_TX#[1] PEG_TX[14] PEG_HTX_GRX_P0 CC32 DIS@ 220nF_0402_16V7K VSS233
D16 D25 1 2 PEG_HTX_C_GRX_P0 <34>
eDP_TX#[2] PEG_TX[15]
F15
eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0
CONN@

Sandy Bridge_rPGA_Rev1p0
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/6) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8241P
Date: Wednesday, February 01, 2012 Sheet 5 of 56
5 4 3 2 1
5 4 3 2 1

+VCCP +VCCP

<15,24> PCH_PWROK +3V_PCH


JXDP1
1 2 +3VS
GND0 GND1

0.1U_0402_16V7K
XDP_PREQ#_R 3 4 <15> SYS_PWROK RC128
XDP_PRDY#_R OBSFN_A0 OBSFN_C0 +1.5V_CPU_VDDQ
5 OBSFN_A1 OBSFN_C1 6

1
7 8 @ 1
GND2 GND3

0_0402_5%

CC33
XDP_BPM#0 9 10 RC127 @ RC6
OBSDATA_A0 OBSDATA_C0

1
XDP_BPM#1 11 12 0_0402_1% 10K_0402_5%
OBSDATA_A1 OBSDATA_C1 @ RC8
13 GND4 GND5 14
XDP_BPM#2 15 16 2
200_0402_1%

2
OBSDATA_A2 OBSDATA_C2

1
XDP_BPM#3 17 18 UC1
OBSDATA_A3 OBSDATA_C3
19 20 1 5

2
GND6 GND7 B VCC
<8> CFG10
0_0402_5% 2 @ 1 RC13 CFG10_R 21
OBSFN_B0 OBSFN_D0
22 <15> PM_DRAM_PWRGD 1 @ 2D_PWG 2 A
D D
<8> CFG11
0_0402_5% 2 @ 1 RC15 CFG11_R 23
OBSFN_B1 OBSFN_D1
24 RC11 0_0402_1% 3
GND Y
4 VDDPWRGOOD
25 26
XDP_BPM#4 GND8 GND9
27 28 RC4 74AHC1G09GW TSSOP 5P RC8
XDP_BPM#5 OBSDATA_B0 OBSDATA_D0
29
OBSDATA_B1 OBSDATA_D1
30 +3V_PCH 1 2 CRB 1.1K

2
31 32 200_0402_1% CHECK LIST 0.7 --> 4.75K
XDP_BPM#6 GND10 GND11 RC19
33 34 INTEL recommand 1.1K
XDP_BPM#7 OBSDATA_B2 OBSDATA_D2 @
35 36 39_0402_1%
OBSDATA_B3 OBSDATA_D3 PDG 0.71 rev -->200
37 38
H_CPUPWRGD GND12 GND13
1K_0402_5% 1 @ 2 RC22 H_CPUPWRGD_XDP 39 40 CLK_CPU_ITP
CLK_CPU_ITP <14>

1
PWRGOOD/HOOK0 ITPCLK/HOOK4
<15,24> PBTN_OUT# 0_0402_5% 1 @ 2 RC23 CFD_PWRBTN#_XDP 41 42 CLK_CPU_ITP# CLK_CPU_ITP# <14>
HOOK1 ITPCLK#/HOOK5
43 44
VCC_OBS_AB VCC_OBS_CD
<8> CFG0
1K_0402_5% 1 @ 2 RC24 XDP_HOOK2 45 HOOK2 RESET#/HOOK6 46 XDP_RST#_R 1 @ 2 PLT_RST#

1
D
<15,50> VGATE 0_0402_1% 1 @ 2 RC26 SYS_PWROK_XDP 47 HOOK3 DBR#/HOOK7 48 XDP_DBRESET# RC25 1K_0402_5%
49 50 <10,27> RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3# 2 QC1
GND14 GND15 XDP_TDO RC28 1 @
<11,12,14,28,29,32> PCH_SMBDATA 51 SDA TD0 52 2 0_0402_5% PCH_JTAG_TDO <13> G SSM3K7002F_SC59-3
53 54 XDP_TRST#_R S
<11,12,14,28,29,32> PCH_SMBCLK

3
SCL TRST#
<13> PCH_JTAG_TCK 1 2 RC30 XDP_TCK1 55 TCK1 TDI 56 XDP_TDI RC31 1 @ 2 0_0402_5% PCH_JTAG_TDI <13> @
0_0402_5% @ XDP_TCK_R 57 58 XDP_TMS_R RC29 1 @ 2 0_0402_5%
TCK0 TMS PCH_JTAG_TMS <13>
59 GND16 GND17 60

The resistor SAMTE_BSH-030-01-L-D-A


for HOOK2 should be CONN@ +3VALW
+VCCP
placed such that the +3VALW +VCCP

0.1U_0402_16V7K
stub is very small
on CFG0 net 1

0.1U_0402_16V7K

0.1U_0402_16V7K

1
CC34
1 1
1

@ RC32
2

CC35

CC36
RC27 75_0402_5%
1K_0402_5%
2 2

2
UC2
2

C C
1 NC VCC 5
SYS_PWROK_XDP <16,24,28,32> PLT_RST# 2 RC33
A BUFO_CPU_RST#
3 4 1 2 BUF_CPU_RST#
GND Y 43_0402_1%
Place near JXDP1
SN74LVC1G07DCKR_SC70-5~D

0.1U_0402_16V7K

1
1 @
RC34

CC63
0_0402_5%
JCPU1B
2

2
A28 CLK_CPU_DMI_R RC37 1 @ 2 0_0402_1%
BCLK CLK_CPU_DMI <14>

MISC

CLOCKS
C26 A27 CLK_CPU_DMI#_R RC38 1 @ 2 0_0402_1%
<17> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <14>

AN34
SKTOCC# CLK_CPU_DPLL_R RC39 1
DPLL_REF_CLK
A16 2 1K_0402_1%
+VCCP A15 CLK_CPU_DPLL#_R RC40 1 2 1K_0402_1% PU/PD for JTAG signals
DPLL_REF_CLK# +VCCP
+VCCP
PAD~D T1 @ H_CATERR# AL33
Remove DPLL Ref clock (for eDP only)
CATERR#
2

THERMAL
RC43 XDP_TMS_R 51_0402_5% 1 2 RC45
62_0402_5% AN33 R8 H_DRAMRST#
<17,24> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
XDP_TDI_R 51_0402_5% 1 2 RC46

DDR3
MISC
1

RC41 XDP_PREQ# 51_0402_5% 1 @ 2 RC47


<24,44> H_PROCHOT# 1 2 H_PROCHOT#_R AL32
PROCHOT# SM_RCOMP[0]
AK1 SM_RCOMP0 140_0402_1%1 2 RC55
56_0402_1% A5 SM_RCOMP1 25.5_0402_1%1 2 RC58 XDP_TDO 51_0402_5% 1 2 RC48
B SM_RCOMP[1] SM_RCOMP2 200_0402_1%1 B
SM_RCOMP[2]
A4 2 RC60
H_THERMTRIP# AN32 DDR3 Compensation Signals
<17> H_THERMTRIP# THERMTRIP# XDP_TCK_R 51_0402_5% 1 2 RC52

XDP_TRST#_R 51_0402_5% 1 2 RC54

AP29 XDP_PRDY# RC1211 @ 2 0_0402_5% XDP_PRDY#_R


PRDY# XDP_PREQ# RC1221 @ XDP_PREQ#_R
AP27 2 0_0402_5%
PREQ#
AR26 XDP_TCK RC1231 @ 2 0_0402_1% XDP_TCK_R
TCK
PWR MANAGEMENT

@ AR27 XDP_TMS RC1241 @ 2 0_0402_1% XDP_TMS_R


JTAG & BPM

RC49 2 H_PM_SYNC_R TMS XDP_TRST# RC1251 @ XDP_TRST#_R


<15> H_PM_SYNC 1 AM34 AP30 2 0_0402_1%
0_0402_1% PM_SYNC TRST#
AR28 XDP_TDI_R RC50 1 @ 2 0_0402_1% XDP_TDI
TDI XDP_TDO_R
@ AP26 RC51 1 @ 2 0_0402_1% XDP_TDO
RC53 2 H_CPUPWRGD_R TDO +3VS
<17> H_CPUPWRGD 1 AP33
0_0402_1% UNCOREPWRGOOD
XDP_DBRESET# 1K_0402_5% 1 2 RC42
RC57 AL35 XDP_DBRESET#_R 1 @ XDP_DBRESET#
2 0_0402_1% XDP_DBRESET# <15>
VDDPWRGOOD 1 DBR#
2 VDDPWRGOOD_R V8 RC56
130_0402_1%~D SM_DRAMPWROK
AT28 XDP_BPM#0_R RC59 1 @ 2 0_0402_5% XDP_BPM#0 H_CPUPWRGD_R 10K_0402_5%1 2 RC44
BPM#[0] XDP_BPM#1_R RC61 @ 0_0402_5% XDP_BPM#1
AR29 1 2
BPM#[1] XDP_BPM#2_R RC62 @ 0_0402_5% XDP_BPM#2
AR30 1 2
BUF_CPU_RST# BPM#[2] XDP_BPM#3_R RC63 @ 0_0402_5% XDP_BPM#3
AR33 AT30 1 2
RESET# BPM#[3] XDP_BPM#4_R RC64 @ 0_0402_5% XDP_BPM#4
AP32 1 2
BPM#[4] XDP_BPM#5_R RC65 @ 0_0402_5% XDP_BPM#5
AR31 1 2
BPM#[5] XDP_BPM#6_R RC66 @ 0_0402_5% XDP_BPM#6
AT31 1 2
BPM#[6] XDP_BPM#7_R RC67 @ 0_0402_5% XDP_BPM#7
AR32 1 2
BPM#[7]
CC64 XDP_BPM#4 RC68 1 @ 2 0_0402_5%
A XDP_BPM#5 CFG12 <8> A
RC69 1 @ 2 0_0402_5%
H_CPUPWRGD_R XDP_BPM#6 CFG13 <8>
1 2 RC70 1 @ 2 0_0402_5%
XDP_BPM#7 CFG14 <8>
@ Sandy Bridge_rPGA_Rev1p0 RC71 1 @ 2 0_0402_5%
CFG15 <8>
CONN@
10P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/6) PM,XDP,CLK
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8241P
Date: Wednesday, February 01, 2012 Sheet 6 of 56
5 4 3 2 1
5 4 3 2 1

JCPU1C

JCPU1D

AB6 M_CLK_DDR0
<11> DDR_A_D[0..63] SA_CLK[0] M_CLK_DDR0 <11>
AA6 M_CLK_DDR#0
SA_CLK#[0] M_CLK_DDR#0 <11>
D DDR_A_D0 C5 V9 DDR_CKE0_DIMMA AE2 M_CLK_DDR2 D
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <11> <12> DDR_B_D[0..63] SB_CLK[0] M_CLK_DDR2 <12>
DDR_A_D1 D5 AD2 M_CLK_DDR#2
SA_DQ[1] SB_CLK#[0] M_CLK_DDR#2 <12>
DDR_A_D2 D3 DDR_B_D0 C9 R9 DDR_CKE2_DIMMB
SA_DQ[2] SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <12>
DDR_A_D3 D2 DDR_B_D1 A7
DDR_A_D4 SA_DQ[3] M_CLK_DDR1 DDR_B_D2 SB_DQ[1]
D6 AA5 M_CLK_DDR1 <11> D10
DDR_A_D5 SA_DQ[4] SA_CLK[1] M_CLK_DDR#1 DDR_B_D3 SB_DQ[2]
C6 AB5 M_CLK_DDR#1 <11> C8
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_CKE1_DIMMA DDR_B_D4 SB_DQ[3] M_CLK_DDR3
C2 V10 DDR_CKE1_DIMMA <11> A9 AE1 M_CLK_DDR3 <12>
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D5 SB_DQ[4] SB_CLK[1] M_CLK_DDR#3
C3 A8 AD1 M_CLK_DDR#3 <12>
DDR_A_D8 SA_DQ[7] DDR_B_D6 SB_DQ[5] SB_CLK#[1] DDR_CKE3_DIMMB
F10 D9 R10 DDR_CKE3_DIMMB <12>
DDR_A_D9 SA_DQ[8] DDR_B_D7 SB_DQ[6] SB_CKE[1]
F8 D8
DDR_A_D10 SA_DQ[9] DDR_B_D8 SB_DQ[7]
G10 AB4 G4
DDR_A_D11 SA_DQ[10] RSVD_TP[1] DDR_B_D9 SB_DQ[8]
G9 AA4 F4
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D10 SB_DQ[9]
F9 SA_DQ[12] RSVD_TP[3] W9 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D13 F7 DDR_B_D11 G1 AA2
DDR_A_D14 SA_DQ[13] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
G8 SA_DQ[14] G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D15 G7 DDR_B_D13 F5
DDR_A_D16 SA_DQ[15] DDR_B_D14 SB_DQ[13]
K4 SA_DQ[16] RSVD_TP[4] AB3 F2 SB_DQ[14]
DDR_A_D17 K5 AA3 DDR_B_D15 G2
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D16 SB_DQ[15]
K1 SA_DQ[18] RSVD_TP[6] W10 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D19 J1 DDR_B_D17 J8 AB1
DDR_A_D20 SA_DQ[19] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
J5 SA_DQ[20] K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D21 J4 DDR_B_D19 K9
DDR_A_D22 SA_DQ[21] DDR_CS0_DIMMA# DDR_B_D20 SB_DQ[19]
J2 SA_DQ[22] SA_CS#[0] AK3 DDR_CS0_DIMMA# <11> J9 SB_DQ[20]
DDR_A_D23 K2 AL3 DDR_CS1_DIMMA# DDR_B_D21 J10
SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# <11> SB_DQ[21]
DDR_A_D24 M8 AG1 DDR_B_D22 K8 AD3 DDR_CS2_DIMMB#
SA_DQ[24] RSVD_TP[7] SB_DQ[22] SB_CS#[0] DDR_CS2_DIMMB# <12>
DDR_A_D25 N10 AH1 DDR_B_D23 K7 AE3 DDR_CS3_DIMMB#
SA_DQ[25] RSVD_TP[8] SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# <12>
DDR_A_D26 N8 DDR_B_D24 M5 AD6
DDR_A_D27 SA_DQ[26] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
N7 SA_DQ[27] N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D28 M10 DDR_B_D26 N2
DDR_A_D29 SA_DQ[28] M_ODT0 DDR_B_D27 SB_DQ[26]
M9 SA_DQ[29] SA_ODT[0] AH3 M_ODT0 <11> N1 SB_DQ[27]
DDR_A_D30 N9 AG3 M_ODT1 DDR_B_D28 M4
SA_DQ[30] SA_ODT[1] M_ODT1 <11> SB_DQ[28]
DDR SYSTEM MEMORY A

DDR_A_D31 M7 AG2 DDR_B_D29 N5 AE4 M_ODT2


SA_DQ[31] RSVD_TP[9] SB_DQ[29] SB_ODT[0] M_ODT2 <12>
DDR_A_D32 AG6 AH2 DDR_B_D30 M2 AD4 M_ODT3

DDR SYSTEM MEMORY B


SA_DQ[32] RSVD_TP[10] SB_DQ[30] SB_ODT[1] M_ODT3 <12>
DDR_A_D33 AG5 DDR_B_D31 M1 AD5
DDR_A_D34 SA_DQ[33] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
C
AK6 SA_DQ[34] AM5 SB_DQ[32] RSVD_TP[20] AE5 C
DDR_A_D35 AK5 DDR_B_D33 AM6
DDR_A_D36 SA_DQ[35] DDR_B_D34 SB_DQ[33]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] <11> AR3 SB_DQ[34]
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D35 AP3
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D36 SB_DQ[35]
AJ5 SA_DQ[38] SA_DQS#[1] G6 AN3 SB_DQ[36] DDR_B_DQS#[0..7] <12>
DDR_A_D39 AJ6 J3 DDR_A_DQS#2 DDR_B_D37 AN2 D7 DDR_B_DQS#0
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D38 SB_DQ[37] SB_DQS#[0] DDR_B_DQS#1
AJ8 SA_DQ[40] SA_DQS#[3] M6 AN1 SB_DQ[38] SB_DQS#[1] F3
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D39 AP2 K6 DDR_B_DQS#2
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
AJ9 AM8 AP5 N3
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AK9 AR12 AN9 AN5
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
AH8 AM15 AT5 AP9
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AH9 AT6 AK12
DDR_A_D46 SA_DQ[45] DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AL9 AP6 AP15
DDR_A_D47 SA_DQ[46] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AL8 AN8
DDR_A_D48 SA_DQ[47] DDR_B_D46 SB_DQ[45]
AP11 DDR_A_DQS[0..7] <11> AR6
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D47 SB_DQ[46]
AN11 D4 AR5
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D48 SB_DQ[47]
AL12 F6 AR9 DDR_B_DQS[0..7] <12>
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AM12 K3 AJ11 C7
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AM11 N6 AT8 G3
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AL11 AL5 AT9 J6
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AP12 AM9 AH11 M3
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AN12 AR11 AR8 AN6
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AJ14 AM14 AJ12 AP8
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AH14 AH12 AK11
DDR_A_D58 SA_DQ[57] DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AL15 AT11 AP14
DDR_A_D59 SA_DQ[58] DDR_B_D57 SB_DQ[56] SB_DQS[7]
AK15 AN14
DDR_A_D60 SA_DQ[59] DDR_B_D58 SB_DQ[57]
AL14 DDR_A_MA[0..15] <11> AR14
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D59 SB_DQ[58]
AK14 AD10 AT14
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D60 SB_DQ[59]
AJ15 W1 AT12 DDR_B_MA[0..15] <12>
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AH15 W2 AN15 AA8
SA_DQ[63] SA_MA[2] DDR_A_MA3 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
W7 AR15 T7
SA_MA[3] DDR_A_MA4 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
V3 AT15 R7
SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[2] DDR_B_MA3
V2 T6
SA_MA[5] DDR_A_MA6 SB_MA[3] DDR_B_MA4
W3 T2
SA_MA[6] DDR_A_MA7 SB_MA[4] DDR_B_MA5
<11> DDR_A_BS0 AE10 W6 T4
SA_BS[0] SA_MA[7] DDR_A_MA8 SB_MA[5] DDR_B_MA6
B
<11> DDR_A_BS1 AF10 V1 T3 B
SA_BS[1] SA_MA[8] DDR_A_MA9 SB_MA[6] DDR_B_MA7
<11> DDR_A_BS2 V6 W5 <12> DDR_B_BS0 AA9 R2
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_BS[0] SB_MA[7] DDR_B_MA8
AD8 <12> DDR_B_BS1 AA7 T5
SA_MA[10] DDR_A_MA11 SB_BS[1] SB_MA[8] DDR_B_MA9
V4 <12> DDR_B_BS2 R6 R3
SA_MA[11] DDR_A_MA12 SB_BS[2] SB_MA[9] DDR_B_MA10
W4 AB7
SA_MA[12] DDR_A_MA13 SB_MA[10] DDR_B_MA11
<11> DDR_A_CAS# AE8 AF8 R1
SA_CAS# SA_MA[13] DDR_A_MA14 SB_MA[11] DDR_B_MA12
<11> DDR_A_RAS# AD9 V5 T1
SA_RAS# SA_MA[14] DDR_A_MA15 SB_MA[12] DDR_B_MA13
<11> DDR_A_WE# AF9 V7 <12> DDR_B_CAS# AA10 AB10
SA_WE# SA_MA[15] SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_B_RAS# AB8 R5
SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_B_WE# AB9 R4
SB_WE# SB_MA[15]

Sandy Bridge_rPGA_Rev1p0
CONN@
Sandy Bridge_rPGA_Rev1p0
CONN@
+1.5V
1

1 @ 2 RC75
RC74 0_0402_5% 1K_0402_5%
QC2
BSS138_SOT23
2
S

<6> H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# <11,12>


RC76 1K_0402_5%
G
2
1

RC77 1 @ 2 DRAMRST_CNTRL_PCH <14>


4.99K_0402_1% RC72 0_0402_1%
A A
DRAMRST_CNTRL
DRAMRST_CNTRL <11>
2

1
CC37
.047U_0402_16V7K
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/6) DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8241P
Date: Wednesday, February 01, 2012 Sheet 7 of 56
5 4 3 2 1
5 4 3 2 1

CFG Straps for Processor


D D
CFG2

1
JCPU1E RC78
1K_0402_1%

L7 @ T2 PAD~D

2
RSVD28 @ T3 PAD~D
AG7
CFG0 RSVD29 @ T4 PAD~D
<6> CFG0 AK28 AE7
PAD~D T85 @ CFG1 CFG[0] RSVD30 @ T5 PAD~D
AK29 AK2
CFG2 CFG[1] RSVD31 @ T6 PAD~D
AL26 W8
PAD~D T86 @ CFG3 CFG[2] RSVD32
AL27 CFG[3]
CFG4 AK26
CFG5 CFG[4] @ T7 PAD~D
AL29 CFG[5] RSVD33 AT26 PEG Static Lane Reversal - CFG2 is for the 16x
CFG6 AL30 AM33 @ T8 PAD~D
CFG7 CFG[6] RSVD34 @ T9 PAD~D
AM31 CFG[7] RSVD35 AJ27
PAD~D T87 @ CFG8 AM32 1:(Default) Normal Operation; Lane #
PAD~D T88 @ CFG9 CFG[8]
AM30 CFG[9] CFG2 definition matches socket pin map definition
<6> CFG10 CFG10 AM28
+VCC_GFXCORE_AXG CFG11 CFG[10]
<6> CFG11 AM26 CFG[11]
+VCC_CORE <6> CFG12 CFG12
CFG13
AN28
AN31
CFG[12]
T8 @ T10 PAD~D
*0:Lane Reversed
<6> CFG13 CFG[13] RSVD37
<6> CFG14 CFG14 AN26 J16 @ T11 PAD~D
CFG[14] RSVD38
2

@ <6> CFG15 CFG15 AM27 H16 @ T12 PAD~D CFG4


RC79 PAD~D T89 @ CFG16 CFG[15] RSVD39 @ T13 PAD~D
AK31 CFG[16] RSVD40 G16

1
50_0402_1% PAD~D T90 @ CFG17 AN29 CFG[17]
2

@ @ RC81
RC80 1K_0402_1%
1

50_0402_1%
AR35 @ T14 PAD~D

2
VCC_AXG_VAL_SENSE RSVD41 @ T15 PAD~D
AJ31 AT34
1

VSS_AXG_VAL_SENSE VAXG_VAL_SENSE RSVD42 @ T16 PAD~D


AH31 VSSAXG_VAL_SENSE RSVD43 AT33
VCC_VAL_SENSE AJ33 AP35 @ T17 PAD~D
VSS_VAL_SENSE VCC_VAL_SENSE RSVD44 @ T18 PAD~D
C
AH33 VSS_VAL_SENSE RSVD45 AR34 C

PAD~D T19 @ AJ26 Display Port Presence Strap


+SA_DIMM_VREFDQ RSVD5

RESERVED
+SB_DIMM_VREFDQ @ T20 PAD~D
+SA_DIMM_VREFDQ B4
RSVD46 B34
A33 @ T21 PAD~D CFG4
* 1 : Disabled; No Physical Display Port
+SB_DIMM_VREFDQ D1
RSVD6 RSVD47
A34 @ T22 PAD~D attached to Embedded Display Port
RSVD7 RSVD48 @ T23 PAD~D
B35
RSVD49 @ T24 PAD~D
RSVD50
C35 0 : Enabled; An external Display Port device is
1

@ @ PAD~D T25 @ F25


connected to the Embedded Display Port
RC84 RC85 PAD~D T26 @ RSVD8
F24
1K_0402_1% 1K_0402_1% PAD~D T27 @ RSVD9
F23
PAD~D T28 @ RSVD10 @ T29 PAD~D
D24 AJ32
2

PAD~D T30 @ RSVD11 RSVD51 @ T31 PAD~D CFG6


G25 AK32
PAD~D T32 @ RSVD12 RSVD52
G24
PAD~D T33 @ RSVD13 CFG5
E23
PAD~D T34 @ RSVD14
D23
RSVD15

1
PAD~D T35 @ C30 AH27 @ T36 PAD~D
PAD~D T37 @ RSVD16 VCC_DIE_SENSE RC87 @ RC86
A31
PAD~D T38 @ RSVD17 1K_0402_1% 1K_0402_1%
B30
PAD~D T39 @ RSVD18
B29
PAD~D T40 @ RSVD19
D30 AN35 CLK_RES_ITP <14>

2
PAD~D T41 @ RSVD20 RSVD54
B31 AM35 CLK_RES_ITP# <14>
PAD~D T42 @ RSVD21 RSVD55
A30
PAD~D T43 @ RSVD22
C29
RSVD23

PAD~D T44 @ J20


RC159 RSVD24
PAD~D T45 @ B18 AT2 @ T46 PAD~D
H_VCCP_SEL RSVD25 RSVD56 @ T47 PAD~D
+3VS 2 1 A19 AT1
VCCIO_SEL RSVD57 @ T48 PAD~D
RSVD58
AR1 PCIE Port Bifurcation Straps
10K_0402_5% PAD~D T49 @
B J15 B
RSVD27
11: (Default) x16 - Device 1 functions 1 and 2 disabled
@ T50 PAD~D CFG[6:5]
KEY
B1 *10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Sandy Bridge_rPGA_Rev1p0
CONN@

CFG7

1
@ RC89
1K_0402_1%

2
VSS_AXG_VAL_SENSE

VSS_VAL_SENSE PEG DEFER TRAINING


2

@ @
RC90 RC91 CFG7
*1: (Default) PEG Train immediately
50_0402_1% 50_0402_1%
following xxRESETB de assertion

0: PEG Wait for BIOS for training


1

A A

INTEL 12/28 recommand


to add RC120, RC121, RC122, RC123
Please place as close as JCPU1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/6) RSVD,CFG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8241P
Date: Wednesday, February 01, 2012 Sheet 8 of 56
5 4 3 2 1
5 4 3 2 1

JCPU1F POWER
QC=94A
+VCC_CORE +VCCP
DC=53A

AG35
8.5A
VCC1
D AG34 AH13 D
VCC2 VCCIO1
AG33 AH10
VCC3 VCCIO2
AG32 AG10
VCC4 VCCIO3
AG31 AC10
VCC5 VCCIO4
AG30 Y10
VCC6 VCCIO5
AG29 U10
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
AF34 J12
VCC12 VCCIO11
AF33 J11
VCC13 VCCIO12
AF32 VCC14 VCCIO13 H14
AF31 VCC15 VCCIO14 H12
AF30 VCC16 VCCIO15 H11
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13

PEG AND DDR


AF27 VCC19 VCCIO18 G12
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 VCC22 VCCIO21 F12
AD33 VCC23 VCCIO22 F11
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
C
AC30 VCC36 VCCIO34 B14 C
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49 +VCCP
AA26
VCC50

CORE SUPPLY
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55

1
Y30
VCC56 RC95 RC93
Y29
VCC57 Place the PU
Y28
VCC58 RC95 close to CPU 75_0402_5%
resistors close to CPU
Y27 130_0402_1%~D
VCC59
Y26

2
VCC60
V35

SVID
VCC61 H_CPU_SVIDALRT# RC94 1
V34 AJ29 2 43_0402_1% VR_SVID_ALRT# <50>
VCC62 VIDALERT# RC92 1 @
V33 AJ30 H_CPU_SVIDCLK 2 0_0402_1% VR_SVID_CLK <50>
VCC63 VIDSCLK H_CPU_SVIDDAT RC96 1 @
V32 AJ28 2 0_0402_1% VR_SVID_DAT <50>
VCC64 VIDSOUT
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
B U35 B
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80 +VCC_CORE
R35
VCC81
R34
VCC82
R33
VCC83

1
R32
VCC84 RC97
R31
VCC85
R30 100_0402_1%
VCC86
R29
VCC87
SENSE LINES

R28

2
VCC88
R27 AJ35 VCCSENSE_R RC98 1 @ 2 0_0402_1% VCCSENSE <50>
VCC89 VCC_SENSE
R26 AJ34 VSSSENSE_R RC99 1 @ 2 0_0402_1% VSSSENSE <50>
VCC90 VSS_SENSE
P35
VCC91
P34
VCC92

1
P33
VCC93 +VCCP RC100
P32 B10
VCC94 VCCIO_SENSE
P31 A10 100_0402_1%
VCC95 VSSIO_SENSE
P30
VCC96 RC108
P29

2
VCC97
P28 2 1
VCC98
1

P27 10_0402_1%
VCC99
P26
VCC100 RC111
VCCIO_SENSE <47>
10_0402_1%
2

A A

Sandy Bridge_rPGA_Rev1p0
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/6) PWR,BYPASS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8241P
Date: Wednesday, February 01, 2012 Sheet 9 of 56
5 4 3 2 1
5 4 3 2 1

+1.5V_CPU_VDDQ Source
+1.5V QC3 +1.5V_CPU_VDDQ
+3VALW B+_BIAS AO4728L_SO8~D
8 1
7 2

20K_0402_5%
6 3 1

10U_0805_10V6K
5

CC38

RC103
RC101
RC102 100K_0402_5%

4
100K_0402_5% 2

2
RUN_ON_CPU1.5VS3 JCPU1H

0.1U_0603_50V_X7R
AT35 AJ22
VSS1 VSS81

330K_0402_1%
QC5B 1 AT32 AJ19
RUN_ON_CPU1.5VS3# VSS2 VSS82
D 5 AT29 AJ16 D
VSS3 VSS83

CC39
RC105
AT27 AJ13
2N7002DW-7-F_SOT363-6 VSS4 VSS84
AT25 AJ10

4
2 VSS5 VSS85
AT22 AJ7

2
VSS6 VSS86

6
AT19 AJ4
QC5A VSS7 VSS87
AT16 AJ3
@ RC104 2N7002DW-7-F_SOT363-6 VSS8 VSS88
AT13 AJ2
VSS9 VSS89
<24,27,28,46,47,48> SUSP# 1 2 2 AT10 AJ1
0_0402_5% VSS10 VSS90
AT7 AH35
RC107 +VCC_GFXCORE_AXG VSS11 VSS91
AT4 AH34

1
VSS12 VSS92
<24> CPU1.5V_S3_GATE 1 2 RUN_ON_CPU1.5VS3# <6,27> AT3 AH32
0_0402_5% VSS13 VSS93
AR25 AH30
VSS14 VSS94
1 RC113 AR22 AH29
@ VSS15 VSS95
AR19 AH28
CC40 VSS16 VSS96
1 2 AR16 AH26
0.1U_0402_10V7K~D 10_0402_1% VSS17 VSS97
AR13 AH25
2 VSS18 VSS98
AR10 AH22
VCC_AXG_SENSE VSS19 VSS99
VCC_AXG_SENSE <50> AR7 AH19
VSS20 VSS100
AR4 AH16
VSS21 VSS101
AR2 AH7
RC157 VSS22 VSS102
1 2 100_0402_1% AP34 AH4

+VCC_GFXCORE_AXG JCPU1G
POWER VSS_AXG_SENSE
@ AP31
AP28
AP25
VSS23
VSS24
VSS25
VSS103
VSS104
VSS105
AG9
AG8
AG4
VSS_AXG_SENSE <50> VSS26 VSS106
AP22 AF6
VSS27 VSS107
33A AT24 AP19 AF5

SENSE
LINES
RC114 VSS28 VSS108
AK35 +1.5V_CPU_VDDQ AP16 AF3
VAXG1 VAXG_SENSE VSS29 VSS109
AT23 AK34 1 2 AP13 AF2
VAXG2 VSSAXG_SENSE +1.5V VSS30 VSS110
AT21 AP10 AE35
VAXG3 10_0402_1% VSS31 VSS111
AT20 AP7 AE34
VAXG4 VSS32 VSS112
AT18 1 2 AP4 AE33
VAXG5 RC129 1K_0402_5% VSS33 VSS113
AT17 AP1 AE32
VAXG6 VSS34 VSS114

1
AR24 AN30 AE31
VAXG7 @ VSS35 VSS115
AR23 1 2 AN27 AE30
VAXG8 1K_0402_5% VSS36 VSS116
AR21 +V_SM_VREF should @ RC106 0_0402_5% AN25 AE29
AR20
VAXG9
have 10 mil trace width RC112 AN22
VSS37
VSS VSS117
AE28

VREF
VAXG10 VSS38 VSS118
AR18 AN19 AE27

2
VAXG11 VSS39 VSS119
AR17 AN16 AE26
VAXG12 +V_SM_VREF_CNT +V_SM_VREF VSS40 VSS120
AP24 AL1 3 1 AN13 AE9
VAXG13 SM_VREF VSS41 VSS121
AP23 AN10 AD7
VAXG14 VSS42 VSS122

1
AP21 @ AN7 AC9
VAXG15 VSS43 VSS123

1
C AP20 AN4 AC8 C
VAXG16 RC126 QC4 @ 1K_0402_5% VSS44 VSS124
AP18 AM29 AC6
VAXG17 2 NTR4503NT1G_SOT23-3~D RC116 VSS45 VSS125
AP17 AM25 AC5
VAXG18 1K_0402_5% VSS46 VSS126
AN24 AM22 AC3

2
VAXG19 RUN_ON_CPU1.5VS3 VSS47 VSS127
AN23 AM19 AC2

2
VAXG20 VSS48 VSS128
AN21
AN20
VAXG21 5A AM16
AM13
VSS49 VSS129
AB35
AB34
DDR3 -1.5V RAILS
VAXG22 +1.5V_CPU_VDDQ @ VSS50 VSS130
AN18 AM10 AB33
VAXG23 JP10 VSS51 VSS131
AN17 AM7 AB32
GRAPHICS

VAXG24 VSS52 VSS132


AM24 AF7 1 2 +1.5V AM4 AB31
VAXG25 VDDQ1 VSS53 VSS133
AM23 AF4 AM3 AB30
VAXG26 VDDQ2 PAD-OPEN 4x4m VSS54 VSS134
AM21 AF1 AM2 AB29
VAXG27 VDDQ3 VSS55 VSS135

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D
AM20
VAXG28 VDDQ4
AC7 1 1 1 1 1 1 1 J8 OPEN AM1
VSS56 VSS136
AB28
AM18 AC4 AL34 AB27
VAXG29 VDDQ5 VSS57 VSS137

CC41

CC42

CC43

CC44

CC45

CC46
AM17 AC1 + CC47 AL31 AB26
VAXG30 VDDQ6 330U_D2_2VM_R6M~D VSS58 VSS138
AL24 Y7 AL28 Y9
VAXG31 VDDQ7 2 2 2 2 2 2 VSS59 VSS139
AL23 Y4 AL25 Y8
VAXG32 VDDQ8 2 VSS60 VSS140
AL21 Y1 AL22 Y6
VAXG33 VDDQ9 VSS61 VSS141
AL20 U7 AL19 Y5
VAXG34 VDDQ10 VSS62 VSS142
AL18 U4 AL16 Y3
VAXG35 VDDQ11 VSS63 VSS143
AL17 U1 AL13 Y2
VAXG36 VDDQ12 VSS64 VSS144
AK24 P7 AL10 W35
VAXG37 VDDQ13 VSS65 VSS145
AK23 P4 AL7 W34
VAXG38 VDDQ14 VSS66 VSS146
AK21 P1 AL4 W33
VAXG39 VDDQ15 VSS67 VSS147
AK20 AL2 W32
VAXG40 VSS68 VSS148
AK18 AK33 W31
VAXG41 VSS69 VSS149
AK17 AK30 W30
VAXG42 VSS70 VSS150
AJ24 AK27 W29
VAXG43 VSS71 VSS151
AJ23 AK25 W28
VAXG44 VSS72 VSS152
AJ21 AK22 W27
VAXG45 VSS73 VSS153
AJ20 +VCCSA AK19 W26
VAXG46 VSS74 VSS154
AJ18 AK16 U9
VAXG47 VSS75 VSS155
AJ17 1 AK13 U8
VAXG48 VSS76 VSS156
10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0603_6.3V6M
AH24 1 1 1 1 @ AK10 U6
SA RAIL

VAXG49 + CC48 VSS77 VSS157


AH23
VAXG50 6A AK7
VSS78 VSS158
U5
CC49

CC50

CC51

CC52
AH21 M27 330U_D2_2VM_R6M~D AK4 U3
VAXG51 VCCSA1 VSS79 VSS159
AH20 M26 AJ25 U2
VAXG52 VCCSA2 2 2 2 2 2 VSS80 VSS160
AH18 L26
VAXG53 VCCSA3
AH17 J26
VAXG54 VCCSA4
J25
VCCSA5
J24
B VCCSA6 Sandy Bridge_rPGA_Rev1p0 B
H26
VCCSA7 CONN@
H25
+1.8VS VCCSA8
1.8V RAIL

1.2A
RC109 1 @ 2 0_0805_1% +1.8VS_VCCPLL B6 H23 +1.5V_CPU_VDDQ +1.5V
VCCSA_SENSE <49>
MISC

VCCPLL1 VCCSA_SENSE
A6
VCCPLL2
10U_0805_4VAM~D

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_4VAM~D

10U_0805_4VAM~D

1 1 1 1 @ 1 @ A2
VCCPLL3 CC53 2 1 0.1U_0402_10V7K~D
CC54

CC55

CC56

CC61

CC62

330U_D2_2.5VM_R6M~D

1 C22 VCCSA_VID0 <49>


FC_C22
C24 VCCSA_VID1 <49>
2 2 2 2 2 VCCSA_VID1
CC57

+ CC58 2 1 0.1U_0402_10V7K~D
1

@ RC110
2 Sandy Bridge_rPGA_Rev1p0 CC59 2 1 0.1U_0402_10V7K~D
0_0402_5%
CONN@
2

CC60 2 1 0.1U_0402_10V7K~D

add CC181 , CC182, 4 caps are all pop.


follow checklist 1.0 5/24

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/6) PWR,VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8241P
Date: Wednesday, February 01, 2012 Sheet 10 of 56
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V
JDIMM1
+V_DDR_REFA 1 2
<7> DDR_A_DQS#[0..7] +1.5V +V_DDR_REFA VREF_DQ VSS1
3 4 DDR_A_D4
VSS2 DQ4

2.2U_0603_6.3V6K

0.1U_0402_16V7K
DDR_A_D0 5 6 DDR_A_D5
<7> DDR_A_DQS[0..7] DQ0 DQ5

1
DDR_A_D1 7 8
RD1 DQ1 VSS3 DDR_A_DQS#0
<7> DDR_A_D[0..63] 1 1 9 VSS4 DQS#0 10
1K_0402_1% 11 12 DDR_A_DQS0
DM0 DQS0

CD1

CD2
<7> DDR_A_MA[0..15] 13 VSS5 VSS6 14
+V_DDR_REFA DDR_A_D2 15 16 DDR_A_D6

2
2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
19 20
DDR_A_D8 VSS7 VSS8 DDR_A_D12
21 22
DQ8 DQ12

1
DDR_A_D9 23 24 DDR_A_D13
D DQ9 DQ13 D
25 26
RD3 DDR_A_DQS#1 VSS9 VSS10
27 28
1K_0402_1% DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 30 DDR3_DRAMRST# <7,12>
DQS1 RESET#
31 32

2
DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 38
DDR_A_D16 VSS13 VSS14 DDR_A_D20
39 40
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 42
DQ17 DQ21
43 44
DDR_A_DQS#2 VSS15 VSS16
45 46
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
Layout Note: All VREF traces should 49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
Place near JDIMM1 have 10 mil trace width 51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
+1.5V 65 66
DDR_A_D26 VSS23 VSS24 DDR_A_D30
67 DQ26 DQ30 68
DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31
71 VSS25 VSS26 72
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1
CD3

CD4

CD5

CD6

DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 VDD1 VDD2 76
2 2 2 2 DDR_A_MA15
77 NC1 A15 78
<7> DDR_A_BS2 DDR_A_BS2 79 80 DDR_A_MA14
BA2 A14
81 VDD3 VDD4 82
C DDR_A_MA12 DDR_A_MA11 C
83 A12/BC# A11 84
DDR_A_MA9 85 86 DDR_A_MA7
A9 A7
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
+1.5V DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
A1 A0
99 100
M_CLK_DDR0 VDD9 VDD10 M_CLK_DDR1
<7> M_CLK_DDR0 101 102 M_CLK_DDR1 <7>
CK0 CK1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

M_CLK_DDR#0 103 104 M_CLK_DDR#1


<7> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <7> +1.5V
105 106
VDD11 VDD12
330U_SX_2VY~D

@ 1 DDR_A_MA10 107 108 DDR_A_BS1


A10/AP BA1 DDR_A_BS1 <7>
1 1 1 1 1 1 1 <7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_RAS# <7>
BA0 RAS#
CD7

CD8

CD9

CD10

CD11

CD12

CD13

CD14

+ 111 112
VDD13 VDD14

1
DDR_A_WE# 113 114 DDR_CS0_DIMMA#
<7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
DDR_A_CAS# 115 116 M_ODT0 RD4
2 2 2 2 2 2 2 2 <7> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
117 118 1K_0402_1%
DDR_A_MA13 VDD15 VDD16 M_ODT1
119 120 M_ODT1 <7>
DDR_CS1_DIMMA# A13 ODT1
<7> DDR_CS1_DIMMA# 121 122

2
S1# NC2
123 124
VDD17 VDD18 +VREF_CA
125 126
NCTEST VREF_CA
127 128
VSS27 VSS28

2.2U_0603_6.3V6K

0.1U_0402_16V7K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37 RD5
133 134 1 1
DDR_A_DQS#4 VSS29 VSS30 1K_0402_1%
135 136
DQS#4 DM4

CD15

CD16
Layout Note: DDR_A_DQS4 137 138
DQS4 VSS31 DDR_A_D38
139 140
Place near JDIMM1.203,204

2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2
141 142
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_A_D44
145 146
B DDR_A_D40 VSS34 DQ44 DDR_A_D45 B
147 148
DDR_A_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_A_DQS#5
151 152
VSS36 DQS#5 DDR_A_DQS5
153 154
DM5 DQS5
155 156
+0.75VS DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 162
DDR_A_D48 VSS39 VSS40 DDR_A_D52
163 164
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
DQ49 DQ53
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

167 168 @ RD8 1 2 0_0402_5%


1 1 1 1 DDR_A_DQS#6
DDR_A_DQS6
169
171
VSS41
DQS#6
DQS6
VSS42
DM6
VSS43
170
172 M3
CD17

CD18

CD19

CD20

173 174 DDR_A_D54 QD1


VSS44 DQ54

D
DDR_A_D50 175 176 DDR_A_D55 3 1 BSS138_NL_SOT23-3
2 2 2 2 DQ50 DQ55 +SA_DIMM_VREFDQ +V_DDR_REFA
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 180
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 182

G
2
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_A_DQS#7 DRAMRST_CNTRL
185 186 <7> DRAMRST_CNTRL
VSS48 DQS#7 DDR_A_DQS7
187 188
DM7 DQS7
189 190
DDR_A_D58 VSS49 VSS50 DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63 @ RD9
195 196 1 2 0_0402_5%
VSS51 VSS52
1 2 197 198
RD6 10K_0402_5% 199 SA0 EVENT# PCH_SMBDATA
+3VS 200 PCH_SMBDATA <6,12,14,28,29,32>
VDDSPD SDA
0.1U_0402_16V7K

2.2U_0603_6.3V6K

1 2 201 202 PCH_SMBCLK QD2


SA1 SCL PCH_SMBCLK <6,12,14,28,29,32>

D
1 1 RD7 10K_0402_5% 203 204 +0.75VS +SB_DIMM_VREFDQ 3 1 BSS138_NL_SOT23-3 +V_DDR_REFB
VTT1 VTT2
CD21

CD22

+0.75VS
205 206
G1 G2

G
2
A 2 2 BELLW_80001-5021 A
CONN@ DRAMRST_CNTRL

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMA
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8241P
Date: Wednesday, February 01, 2012 Sheet 11 of 56
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V
JDIMM2
+1.5V +V_DDR_REFB 1 2
+V_DDR_REFB VREF_DQ VSS
3 4 DDR_B_D4
VSS DQ4

2.2U_0603_6.3V6K

0.1U_0402_16V7K
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS 8

1
1 1 9 10 DDR_B_DQS#0
VSS DQS0# DDR_B_DQS0
11 DM0 DQS0 12

CD27

CD26
RD15 13 14
1K_0402_1% DDR_B_D2 VSS VSS DDR_B_D6
15 DQ2 DQ6 16
+V_DDR_REFB 2 2 DDR_B_D3 17 18 DDR_B_D7

2
DQ3 DQ7
19 20
DDR_B_D8 VSS VSS DDR_B_D12
<7> DDR_B_DQS#[0..7] 21 22
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 24
D DQ9 DQ13 D
<7> DDR_B_DQS[0..7] 25 26
VSS VSS

1
DDR_B_DQS#1 27 28
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#
<7> DDR_B_D[0..63] 29 30 DDR3_DRAMRST# <7,11>
DQS1 RESET#
RD16 Note: 31
VSS VSS
32
1K_0402_1% DDR_B_D10 33 34 DDR_B_D14
<7> DDR_B_MA[0..15] Check voltage tolerance of DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15

2
DQ11 DQ15
VREF_DQ at the DIMM socket 37
VSS VSS
38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS VSS
45 46
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS DDR_B_D28
All VREF traces should 55 56
DDR_B_D24 VSS DQ28 DDR_B_D29
have 10 mil trace width 57 DQ24 DQ29 58
DDR_B_D25 59 60
DQ25 VSS DDR_B_DQS#3
61 VSS DQS3# 62
63 64 DDR_B_DQS3
DM3 DQS3
65 VSS VSS 66
Layout Note: DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 70
Place near JDIMMB 71
DQ27 DQ31
72
VSS VSS

DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 VDD VDD 76
77 78 DDR_B_MA15
DDR_B_BS2 NC A15 DDR_B_MA14
<7> DDR_B_BS2 79 BA2 A14 80
81 VDD VDD 82
+1.5V DDR_B_MA12 83 84 DDR_B_MA11
C DDR_B_MA9 A12/BC# A11 DDR_B_MA7 C
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
A8 A6
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DDR_B_MA5 91 92 DDR_B_MA4
A5 A4
1 1 1 1 93 VDD VDD 94
CD28

CD29

CD30

CD31

DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 100
2 2 2 2 M_CLK_DDR2 VDD VDD M_CLK_DDR3
<7> M_CLK_DDR2 101 102 M_CLK_DDR3 <7>
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
<7> M_CLK_DDR#2 103 104 M_CLK_DDR#3 <7>
CK0# CK1# +1.5V
105 106
DDR_B_MA10 VDD VDD DDR_B_BS1
107 108 DDR_B_BS1 <7>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<7> DDR_B_BS0 109 110 DDR_B_RAS# <7>
BA0 RAS#
111 112
VDD VDD

1
DDR_B_WE# 113 114 DDR_CS2_DIMMB#
<7> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
DDR_B_CAS# 115 116 M_ODT2 RD17
+1.5V <7> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
117 118 1K_0402_1%
DDR_B_MA13 VDD VDD M_ODT3
119 120 M_ODT3 <7>
DDR_CS3_DIMMB# A13 ODT1
<7> DDR_CS3_DIMMB# 121 122

2
S1# NC
123 124
VDD VDD
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

@ 125 126 +VREF_CB


TEST VREF_CA
127 128
VSS VSS
330U_SX_2VY~D

2.2U_0603_6.3V6K

0.1U_0402_16V7K
@ 1 DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36

1
1 1 1 1 1 1 1 DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37
CD32

CD33

CD34

CD35

CD36

CD37

CD38

CD39

+ 133 134 RD18


VSS VSS 1 1
DDR_B_DQS#4 135 136 1K_0402_1%
DQS4# DM4

CD40

CD41
DDR_B_DQS4 137 138
2 2 2 2 2 2 2 2 DQS4 VSS DDR_B_D38
139 140

2
DDR_B_D34 VSS DQ38 DDR_B_D39 2 2
141 142
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS DDR_B_D44
145 146
DDR_B_D40 VSS DQ44 DDR_B_D45
147 148
B DDR_B_D41 DQ40 DQ45 B
149 150
DQ41 VSS DDR_B_DQS#5
151 152
VSS DQS5# DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS VSS DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
Layout Note: 161
VSS VSS
162
DDR_B_D48 163 164 DDR_B_D52
Place near JDIMMB.203,204 DDR_B_D49 165
DQ48 DQ52
166 DDR_B_D53
DQ49 DQ53
167 168
DDR_B_DQS#6 VSS VSS
169 170
DDR_B_DQS6 DQS6# DM6
171 172
DQS6 VSS DDR_B_D54
173 174
DDR_B_D50 VSS DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS DDR_B_D60
179 180
+0.75VS DDR_B_D56 VSS DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS DDR_B_DQS#7
185 186
VSS DQS7# DDR_B_DQS7
187 188
DM7 DQS7
189 190
VSS VSS
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DDR_B_D58 191 192 DDR_B_D62


DDR_B_D59 DQ58 DQ62 DDR_B_D63
1 1 1 1 193 194
DQ59 DQ63
195 196
+3VS VSS VSS
CD42

CD43

CD44

CD45

197 198
SA0 EVENT# PCH_SMBDATA
+3VS 199 200 PCH_SMBDATA <6,11,14,28,29,32>
2 2 2 2 VDDSPD SDA PCH_SMBCLK
2 1 201 202 PCH_SMBCLK <6,11,14,28,29,32>
SA1 SCL
+0.75VS 203 204 +0.75VS
VTT VTT
1

0.1U_0402_16V7K

2.2U_0603_6.3V6K

RD19
10K_0402_5%

10K_0402_5% 205 206


GND1 GND2
RD20

1 1 207 208
BOSS1 BOSS2
CD46

CD47

A A
2

BELLW_80001-1021
2 2 CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8241P
Date: Wednesday, February 01, 2012 Sheet 12 of 56
5 4 3 2 1
5 4 3 2 1

PCH_RTCX1 +3VS

1 2 PCH_RTCX2
RH1 10M_0402_5% SERIRQ RH10 2 1 10K_0402_5%
YH1 @ +RTCVCC
1 2 2 1 HDA_SDOUT HDD_DET# RH12 2 1 10K_0402_5%
close to YH1 CH1 10P_0402_50V8J 330K_0402_5%
PCH_INTVRMEN RH13 2 1 PCH_SATALED#RH14 2 1 10K_0402_5%
32.768KHZ_12.5PF_9H03200019 1 2 PCH_RTCX1 @
<31> PCH_RTCX1_R
RH30 0_0402_5% 2 1 HDA_BIT_CLK PCH_INTVRMEN RH16 2 @ 1
18P_0402_50V8J

GCLK@ CH2 10P_0402_50V8J UH1 @


330K_0402_5% +3VS

* LH
1 1
CH3 CH4 INTVRMEN

D
2 2
18P_0402_50V8J
+RTCVCC
Reserve for RF please close to UH1
Integrated
Integrated
VRM enable
VRM disable HDA_SPKR RH17 2 @ 1 1K_0402_5%
D
RH2 1 2 SM_INTRUDER# BD82HM77 QPRG C1 BGA 989P PCH LOW=Default
1M_0402_5%
SA00005AG1L *HIGH=No Reboot

UH1A
SA00005AG1L
keep away hot spot HDA_SDO +3V_PCH
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0 ME debug mode , this signal has a weak internal PD
1 RTCX1 FWH0 / LAD0 LPC_AD0 <24>

1
CMOS A38 LPC_AD1

LPC
FWH1 / LAD1 LPC_AD1 <24>
CH5 CLRP1 PCH_RTCX2 C20 B37 LPC_AD2 L=>security measures defined in the Flash HDA_SDOUT RH23 2 @ 1 1K_0402_5%
RTCX2 FWH2 / LAD2 LPC_AD2 <24>
1U_0603_10V6K SHORT PADS C37 LPC_AD3
LPC_AD3 <24> Descriptor will be in effect (default)

2
2 PCH_RTCRST# FWH3 / LAD3
1 2
RH3 20K_0402_5%
D20
RTCRST#
FWH4 / LFRAME#
D36 LPC_FRAME#
LPC_FRAME# <24>
*Low = Disabled
High = Enabled
1 2 PCH_SRTCRST# G22 H=>Flash Descriptor Security will be overridden
RH4 20K_0402_5% SRTCRST#
1 E36

RTC
LDRQ0#

1
SM_INTRUDER# K22 K36
CH6 CLRP2 INTRUDER# LDRQ1# / GPIO23
1U_0603_10V6K SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ SERIRQ <24>

2
2 ME CMOS INTVRMEN SERIRQ
CLP1 & CLP2 place near DIMM
SATA0RXN
AM3 SATA_PRX_DTX_N0 <29> HDA_SYNC
<30> HDA_BITCLK_AUDIO 1 2 HDA_BIT_CLK HDA_BIT_CLK N34 AM1 SATA_PRX_DTX_P0 <29>
HDA_BCLK SATA0RXP

SATA 6G
RH5 33_0402_5% AP7 SATA_PTX_DRX_N0 CH7 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0_C <29> HDD This signal has a weak internal pull-down
+5VS HDA_SYNC SATA0TXN
L34 AP5 SATA_PTX_DRX_P0 CH8 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P0_C <29> On Die PLL VR is supplied by
HDA_RST# HDA_SYNC SATA0TXP
<30> HDA_RST_AUDIO# 1 2 1.5V when smapled high
RH6 33_0402_5% HDA_SPKR T10 AM10 SATA_PRX_DTX_N1 <32>
<30> HDA_SPKR SPKR SATA1RXN 1.8V when sampled low
2
G

AM8 SATA_PRX_DTX_P1 <32>


HDA_RST# SATA1RXP Needs to be pulled High for Huron River platfrom
K34 AP11 SATA_PTX_DRX_N1 CH18 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N1_C <32> mSATA
HDA_SYNC_R HDA_SYNC HDA_RST# SATA1TXN
<30> HDA_SYNC_AUDIO 1 2 3 1 AP10 SATA_PTX_DRX_P1 CH17 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P1_C <32>
RH7 33_0402_5% SATA1TXP +3V_PCH
S

<30> HDA_SDIN0 HDA_SDIN0 E34 AD7 SATA_PRX_DTX_N2 <29>


QH1 BSS138_SOT23 HDA_SDIN0 SATA2RXN
AD5 SATA_PRX_DTX_P2 <29>
SATA2RXP
1 2 1 @ 2 G34 AH5 SATA_PTX_DRX_N2 CH9 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N2_C <29> ODD HDA_SYNC RH32 2 1 1K_0402_5%
HDA_SDIN1 SATA2TXN
RH8 1M_0402_5% RH9 0_0402_5% AH4 SATA_PTX_DRX_P2 CH10 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P2_C <29>
SATA2TXP
C34
HDA_SDIN2

IHDA
C AB8 C
SATA3RXN
A34 AB10
HDA_SDOUT HDA_SDIN3 SATA3RXP
1 2 AF3
<24> ME_EN
RH11 1K_0402_1%
HDA_SDOUT A36
SATA3TXN
SATA3TXP
AF1 RTC Battery
HDA_SDO

SATA
<30> HDA_SDOUT_AUDIO 1 2 HDA_SDOUT Y7
RH15 33_0402_5% SATA4RXN
Y5
SATA4RXP
C36 AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD1
N32
SATA4TXP +RTCBATT
HDA_DOCK_RST# / GPIO13
Y3
SATA5RXN
Y1
SATA5RXP
AB3
SATA5TXN

2
+3V_PCH +3V_PCH +3V_PCH PCH_JTAG_TCK J3 AB1
<6> PCH_JTAG_TCK JTAG_TCK SATA5TXP
+CHGRTC RH34
PCH_JTAG_TMS H7 Y11 +1.05VS_VCC_SATA 1K_0402_5%

JTAG
<6> PCH_JTAG_TMS JTAG_TMS SATAICOMPO
1

@ RH18 @ RH19 @ RH20 PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2


<6> PCH_JTAG_TDI

1
JTAG_TDI SATAICOMPI
200_0402_5% 200_0402_5% 200_0402_5% RH21 37.4_0402_1% W=20mils
PCH_JTAG_TDO H1 W=20mils
<6> PCH_JTAG_TDO JTAG_TDO

2
AB12 +1.05VS_SATA3
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI SATA3RCOMPO DH1


JP12
AB13 SATA3_COMP 1 2 BAT54CW_SOT323-3
SATA3COMPI
1

RH22 49.9_0402_1% 2 1
RH24 RH25 RH26 +CHGRTC 2 1 +3VLP
100_0402_1% 100_0402_1% 100_0402_1% PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2 JUMP_43X39

1
SPI_CLK SATA3RBIAS RH28 750_0402_1%~D
PCH_SPI_CS0# Y14
+RTCVCC
2

SPI_CS0# W=20mils 1
PCH_SPI_CS1# T1 CH12
SPI

SPI_CS1# PCH_SATALED# 1U_0603_10V6K


P3 PCH_SATALED# <32>
SATALED#
PCH_SPI_SI V4 V14 HDD_DET#_R RH268 1 2 0_0402_5% HDD_DET# 2
SPI_MOSI SATA0GP / GPIO21 HDD_DET# <29>
PCH_SPI_SO U3 P1 BBS_BIT0_R 2 1 10K_0402_5% +3VS
SPI_MISO SATA1GP / GPIO19 RH29

B BD82HM77 QPRG C1 BGA 989P PCH B

+3V_PCH
+3V_PCH
NEC flash issue.
+3V_PCH
+3V_PCH +3V_PCH
0.1U_0402_16V7K

0.1U_0402_16V7K
CH11
1
SPI ROM FOR ME CH98
1
2

@
( 4MByte )

2
RH262 RH33 2 @
3.3K_0402_5% 3.3K_0402_5% SPI ROM FOR WIN8( 2MByte ) RH263 2
PCH_JTAG_TCK 1 2 @ 3.3K_0402_5%
RH35 51_0402_5% UH6
1

+3V_PCH PCH_SPI_CS0# 1 RH264 2 0_0402_5% PCH_SPI_CS0#_R 1 8

1
UH2 PCH_SPI_SO PCH_SPI_SO_L 2 CS# VCC PCH_SPI_HOLD#
2 1 7
PCH_SPI_CS1# PCH_SPI_CS1#_R PCH_SPI_WP# SO/SIO1 HOLD# PCH_SPI_CLK_L
1 RH36 2 0_0402_5% 1 8 RH265 33_0402_5% 3 6 2 RH266 133_0402_5% PCH_SPI_CLK
PCH_SPI_SO PCH_SPI_SO_R CS# VCC PCH_SPI_HOLD# WP# SCLK PCH_SPI_SI_L PCH_SPI_SI
2 RH37 1 33_0402_5% 2
SO HOLD#
7 4
GND SI/SIO0
5 2 1
1 2 PCH_SPI_WP# PCH_SPI_WP# 3
WP# SCLK
6 PCH_SPI_CLK_R 2 RH27 133_0402_5% PCH_SPI_CLK RH267 33_0402_5%
RH38 3.3K_0402_5% 4 5 PCH_SPI_SI_R 2 RH39 133_0402_5% PCH_SPI_SI EN25Q32B-104HIP_SO8
GND SI
1 2 PCH_SPI_HOLD# EN25QH16-104HIP_SO8
RH40 3.3K_0402_5% 1 EON EN25Q32B-104HIP_SO8
CH99
@ 10P_0402_50V8J
2
EON EN25QH16-104HIP_SO8

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/8) SATA,HDA,SPI, LPC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8241P
Date: Wednesday, February 01, 2012 Sheet 13 of 56
5 4 3 2 1
5 4 3 2 1

SMBCLK 1 2 +3V_PCH
RH45 2.2K_0402_5%
UH1B SMBDATA 1 2
RH46 2.2K_0402_5%
<32> PCIE_PRX_LANTX_N1 PCIE_PRX_LANTX_N1 BG34 SML0CLK 1 2
PCIE_PRX_LANTX_P1 PERN1 SMBALERT# RH47 2.2K_0402_5%
<32> PCIE_PRX_LANTX_P1 BJ34 PERP1 SMBALERT# / GPIO11 E12
10/100/1G LAN ---> CH19 1 2 0.1U_0402_10V7K~D PCIE_PTX_LANRX_N1_C AV32 SML0DATA 1 2
<32> PCIE_PTX_LANRX_N1 PETN1
CH20 1 2 0.1U_0402_10V7K~D PCIE_PTX_LANRX_P1_C AU32 H14 SMBCLK RH49 2.2K_0402_5%
<32> PCIE_PTX_LANRX_P1 PETP1 SMBCLK
MEMORY SML1CLK 1 2
<32> PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_N2 BE34 C9 SMBDATA RH50 2.2K_0402_5%
PCIE_PRX_WLANTX_P2 PERN2 SMBDATA SML1DATA
<32> PCIE_PRX_WLANTX_P2 BF34 PERP2 1 2
WLAN (Mini Card 1)---> CH21 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_N2_C BB32 RH51 2.2K_0402_5%
<32> PCIE_PTX_WLANRX_N2 PETN2
CH22 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_P2_C AY32 SMBALERT# 1 2

SMBUS
D <32> PCIE_PTX_WLANRX_P2 PETP2 D
A12 DRAMRST_CNTRL_PCH RH52 10K_0402_5%
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7>
<28> PCIE_PRX_EXPTX_N3 PCIE_PRX_EXPTX_N3 BG36 PCH_HOT# 1 2
PCIE_PRX_EXPTX_P3 PERN3 SML0CLK RH86 10K_0402_5%
<28> PCIE_PRX_EXPTX_P3 BJ36 PERP3 SML0CLK C8
Express Card ---> CH15 1 2 0.1U_0402_10V7K~D PCIE_PTX_EXPRX_N3_C AV34 DRAMRST_CNTRL_PCH 1 2
<28> PCIE_PTX_EXPRX_N3 PETN3
CH16 1 2 0.1U_0402_10V7K~D PCIE_PTX_EXPRX_P3_C AU34 G12 SML0DATA RH53 1K_0402_5%
<28> PCIE_PTX_EXPRX_P3 PETP3 SML0DATA
BF36 PERN4
BE36 PERP4
AY34 C13 PCH_HOT#
PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_HOT# <24>
BB34 CLKIN_DMI2# RH54 1 2 10K_0402_5%
PETP4 SML1CLK CLKIN_DMI2 RH55 10K_0402_5%
E14 1 2

PCI-E*
SML1CLK / GPIO58 CLKIN_DMI# RH56 10K_0402_5%
BG37 PERN5 1 2
BH37 M16 SML1DATA CLKIN_DMI RH57 1 2 10K_0402_5%
PERP5 SML1DATA / GPIO75 CLKIN_DOT96# RH58 10K_0402_5%
AY36 PETN5 1 2
BB36 Total device 20090512 CLKIN_DOT96 RH59 1 2 10K_0402_5%
PETP5 CLKIN_SATA# RH60 10K_0402_5%
1 2
BJ38 add double mosfet prevent CLKIN_SATA RH61 1 2 10K_0402_5%
PERN6 CLK_PCH_14M RH62 10K_0402_5%
BG38 PERP6 ATI M92 electric leakage 1 2

Controller
AU36 PETN6 CL_CLK1 M7
AV36 PETP6 If use extenal CLK gen, please place close to CLK gen

Link
BG40 T11 +3V_PCH else, please place close to PCH
PERN7 CL_DATA1
BJ40 PERP7 No support iAMT
AY40 PETN7
BB40 PETP7 CL_RST1# P10

2
BE38 RH64
PERN8
BC38 PERP8 10K_0402_5%
AW38 PETN8
AY38

1
PETP8
M10 PEG_A_CLKRQ# PEG_A_CLKRQ# <35>
C RH67 1 PEG_A_CLKRQ# / GPIO47 C
<32> CLK_PCIE_LAN# 2 0_0402_5% PCIE_LAN# Y40 CLKOUT_PCIE0N
10/100/1G LAN ---> RH68 1 2 0_0402_5% PCIE_LAN Y39
<32> CLK_PCIE_LAN CLKOUT_PCIE0P
+3V_PCH RH69 2 1 10K_0402_5% AB37 CLK_PEG_VGA# CLK_PEG_VGA# <34>
CLKOUT_PEG_A_N

CLOCKS
LAN_CLKREQ# J2 AB38 CLK_PEG_VGA +3VS +3VS
<32> LAN_CLKREQ# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PEG_VGA <34>

RH75 2 1 0_0402_5% PCIE_WLAN# AB49 AV22 CLK_CPU_DMI#


<32> CLK_PCIE_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <6>
RH76 2 1 0_0402_5% PCIE_WLAN AB47 AU22 CLK_CPU_DMI
<32> CLK_PCIE_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN (Mini Card 1)---> +3VS RH77 2 1 10K_0402_5%
<32> WLAN_CLKREQ# WLAN_CLKREQ# M1 PCIECLKRQ1# / GPIO18
CLKOUT_DP_N AM12

2
CLKOUT_DP_P AM13
RH79 2 1 0_0402_5% PCIE_EXP# AA48 RH71 RH72
<28> CLK_PCIE_EXP# CLKOUT_PCIE2N
RH80 2 1 0_0402_5% PCIE_EXP AA47 2.2K_0402_5% 2.2K_0402_5%
<28> CLK_PCIE_EXP CLKOUT_PCIE2P
Express Card ---> +3VS RH81 2 1 10K_0402_5% BF18 CLKIN_DMI#
CLKIN_DMI_N

2
<28> EXPCLK_REQ# EXPCLK_REQ# V10 BE18 CLKIN_DMI

1
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
SMBCLK 6 1 PCH_SMBCLK <6,11,12,28,29,32>
Y37 BJ30 CLKIN_DMI2#
CLKOUT_PCIE3N CLKIN_GND1_N CLKIN_DMI2 DMN66D0LDW-7_SOT363-6
Y36 CLKOUT_PCIE3P CLKIN_GND1_P BG30
QH2A
+3V_PCH RH74 2 1 10K_0402_5% GPIO25 A8 RH78
PCIECLKRQ3# / GPIO25 CLKIN_DOT96#
CLKIN_DOT_96N G24 1 @ 2

5
E24 CLKIN_DOT96 0_0402_5%
CLKIN_DOT_96P
Y43
*PCIE REQ power rail: Y45
CLKOUT_PCIE4N SMBDATA 3 4
CLKOUT_PCIE4P PCH_SMBDATA <6,11,12,28,29,32>
AK7 CLKIN_SATA#
suspend: 0 3 4 5 6 7 +3V_PCH RH66 1 2 10K_0402_5% GPIO26 L12
CLKIN_SATA_N
AK5 CLKIN_SATA DMN66D0LDW-7_SOT363-6
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
core: 1 2 QH2B
RH82
V45 K45 CLK_PCH_14M 1 @ 2
CLKOUT_PCIE5N REFCLK14IN 0_0402_5%
V46 CLKOUT_PCIE5P
B B

+3V_PCH RH83 1 2 10K_0402_5% GPIO44 L14 H45 CLK_PCI_LPBACK


PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <16>

AB42 V47 XTAL25_IN


CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49

+3V_PCH RH84 1 2 10K_0402_5% GPIO56 E6 PEG_B_CLKRQ# / GPIO56


Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN
XCLK_RCOMP RH85 90.9_0402_1% +3V_PCH
V40 CLKOUT_PCIE6N
V42 CLKOUT_PCIE6P
+3V_PCH RH88 1 2 10K_0402_5% GPIO45 T13 PCIECLKRQ6# / GPIO45
XTAL25_IN V38 K43 CLK_FLEX0 @ T53 PAD~D

FLEX CLOCKS
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64

2
V37 CLKOUT_PCIE7P
2 1 XTAL25_OUT F47 CLK_14M_R 1 RH125 2 @ T54 PAD~D
1M_0402_5% RH89 RH90 1 CLKOUTFLEX1 / GPIO65
+3V_PCH 2 10K_0402_5% GPIO46 K12 PCIECLKRQ7# / GPIO46
22_0402_5% SML1CLK 1 6 PCH_SMLCLK <24>
H47 CLK_LAN_25M_R 2 @ 1
CLKOUTFLEX2 / GPIO66 CLK_LAN_25M <32> DMN66D0LDW-7_SOT363-6
CLK_CPU_ITP# RH91 2 1 0_0402_5% CLK_BCLK_ITP# AK14 RH270 22_0402_5%
<6> CLK_CPU_ITP# CLKOUT_ITPXDP_N
CLK_CPU_ITP RH92 2 1 0_0402_5% CLK_BCLK_ITP AK13 K49 DGPU_PRSNT# 2 1 +3VS QH3A
<6> CLK_CPU_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 RH269 10K_0402_5%
1

5
UMA@

2
27P_0402_50V8J

27P_0402_50V8J

1 1 RH93 2 @ 1 0_0402_5% BD82HM77 QPRG C1 BGA 989P PCH


GND OSC

OSC

<8> CLK_RES_ITP#
RH94 2 @ 1 0_0402_5% RH261 SML1DATA 4 3 PCH_SMLDATA <24>
<8> CLK_RES_ITP
CH27 CH28 DIS@ 10K_0402_5%
DMN66D0LDW-7_SOT363-6
25MHZ_20PF_FSX3M-25.M20FDO

GND

2 2
QH3B

1
YH2
2

@ @ close to RH270
A RH63 CH25 A
close to YH2 CLK_PCH_14M 2 1 1 2 <31> LAN_X1 1 2 CLK_LAN_25M
33_0402_5% 22P_0402_50V8J~D RH31 0_0402_5%
1 2 XTAL25_IN GCLK@
<31> PCH_X1
RH41 0_0402_5%
GCLK@
@ @
RH65 CH26
CLK_PCI_LPBACK 2 1 1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
33_0402_5% 22P_0402_50V8J~D 2012/01/17 2013/01/16 Title
Issued Date Deciphered Date
Reserve for EMI please close to
UH1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/8) PCIE, SMBUS, CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8241P
Date: Wednesday, February 01, 2012 Sheet 14 of 56
5 4 3 2 1
5 4 3 2 1

UH1C

<5> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 <5>


DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 <5>
DMI_CTX_PRX_N2 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N2
<5> DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 <5> UH1D
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3
<5> DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 <5>
DMI3RXN FDI_RXN3 FDI_CTX_PRX_N4 ENBKL
BC12 FDI_CTX_PRX_N4 <5> <24> ENBKL J47 AP43
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5 PCH_ENVDD L_BKLTEN SDVO_TVCLKINN
<5> DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 <5> <22> PCH_ENVDD M45 AP45
DMI_CTX_PRX_P1 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N6 L_VDD_EN SDVO_TVCLKINP
<5> DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 <5>
DMI_CTX_PRX_P2 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7
<5> DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 <5> <22> VGA_PWM P45 AM42
DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7 L_BKLTCTL SDVO_STALLN
<5> DMI_CTX_PRX_P3 BJ20 AM40
DMI3RXP FDI_CTX_PRX_P0 LVDS_DDC_CLK SDVO_STALLP
BG14 FDI_CTX_PRX_P0 <5> <22> LVDS_DDC_CLK T40
DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1 LVDS_DDC_DATA L_DDC_CLK
<5> DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 <5> <22> LVDS_DDC_DATA K47 AP39
DMI_CRX_PTX_N1 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P2 L_DDC_DATA SDVO_INTN
<5> DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 <5> AP40
D DMI_CRX_PTX_N2 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P3 CTRL_CLK SDVO_INTP D
<5> DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 <5> T45
DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4 CTRL_DATA L_CTRL_CLK
AV18 BE12 P39

DMI
FDI
<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <5> L_CTRL_DATA
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6 LVDS_IBG
<5> DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 <5> AF37 P38 PCH_SDVO_CTRLCLK <23>
DMI_CRX_PTX_P1 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P7 PAD~D T56 LVD_IBG SDVO_CTRLCLK
<5> DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 <5> AF36 M39 PCH_SDVO_CTRLDATA <23>
DMI_CRX_PTX_P2 DMI1TXP FDI_RXP7 LVD_VBG SDVO_CTRLDATA
<5> DMI_CRX_PTX_P2 AY18
DMI_CRX_PTX_P3 DMI2TXP
<5> DMI_CRX_PTX_P3 AU18 AE48
DMI3TXP FDI_INT LVD_VREFH
AW16 FDI_INT <5> AE47 AT49
FDI_INT LVD_VREFL DDPB_AUXN
AT47
+1.05VS FDI_FSYNC0 DDPB_AUXP HDMI_DET
BJ24 AV12 FDI_FSYNC0 <5> AT40 HDMI_DET <23>
DMI_ZCOMP FDI_FSYNC0 LVDS_ACLK- DDPB_HPD
AK39

LVDS
<22> LVDS_ACLK- LVDSA_CLK#
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1 LVDS_ACLK+ AK40 AV42 HDMI_A2N_VGA
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5> <22> LVDS_ACLK+ LVDSA_CLK DDPB_0N HDMI_A2N_VGA <23>
RH99 49.9_0402_1% AV40 HDMI_A2P_VGA
DDPB_0P HDMI_A2P_VGA <23>
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 LVDS_A0- AN48 HDMI AV45 HDMI_A1N_VGA
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> <22> LVDS_A0- LVDSA_DATA#0 DDPB_1N HDMI_A1N_VGA <23>
RH100 750_0402_1%~D LVDS_A1- AM47 AV46 HDMI_A1P_VGA

Digital Display Interface


<22> LVDS_A1- LVDSA_DATA#1 DDPB_1P HDMI_A1P_VGA <23>
4mil width and place BB10 FDI_LSYNC1 LVDS_A2- AK47 AU48 HDMI_A0N_VGA
FDI_LSYNC1 FDI_LSYNC1 <5> <22> LVDS_A2- LVDSA_DATA#2 DDPB_2N HDMI_A0N_VGA <23>
AJ48 AU47 HDMI_A0P_VGA
within 500mil of the PCH LVDSA_DATA#3 DDPB_2P
AV47 HDMI_A3N_VGA
HDMI_A0P_VGA <23>
DDPB_3N HDMI_A3N_VGA <23>
LVDS_A0+ AN47 AV49 HDMI_A3P_VGA
<22> LVDS_A0+ LVDSA_DATA0 DDPB_3P HDMI_A3P_VGA <23>
A18 DSWODVREN LVDS_A1+ AM49
DSWVRMEN <22> LVDS_A1+ LVDSA_DATA1
LVDS_A2+ AK49
<22> LVDS_A2+ LVDSA_DATA2

System Power Management


AJ47 P46
PAD~D T57 LVDSA_DATA3 DDPC_CTRLCLK
C12 E22 PCH_DPWROK 1 RH128 2 0_0402_5% PCH_RSMRST#_R P42
SUSACK# DPWROK DDPC_CTRLDATA
@ LVDS_BCLK- AF40
<22> LVDS_BCLK- LVDSB_CLK#
<6> XDP_DBRESET# XDP_DBRESET# K3 B9 WAKE# 1 2 PCIE_WAKE# <24,28,32> <22> LVDS_BCLK+ LVDS_BCLK+ AF39 AP47
SYS_RESET# WAKE# RH103 0_0402_5% LVDSB_CLK DDPC_AUXN
AP49
LVDS_B0- DDPC_AUXP
<22> LVDS_B0- AH45 AT38
SYS_PWROK SYS_PWROK_R P12 PM_CLKRUN# LVDS_B1- LVDSB_DATA#0 DDPC_HPD
1 2 N3 <22> LVDS_B1- AH47
RH104 0_0402_5% SYS_PWROK CLKRUN# / GPIO32 LVDS_B2- LVDSB_DATA#1
<22> LVDS_B2- AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 AY49
SUS_STAT# T58 PAD~D LVDSB_DATA#3 DDPC_0P
1 2 L22 G8 AY43
C RH105 0_0402_5% PWROK SUS_STAT# / GPIO61 LVDS_B0+ DDPC_1N C
<22> LVDS_B0+ AH43 AY45
LVDS_B1+ LVDSB_DATA0 DDPC_1P
1 2 L10 N14 SUSCLK 2 1
<22> LVDS_B1+
LVDS_B2+
AH49
A