Question:
a) Design a 4-bit ripple carry adder using verilog. Also write the test bench for this and simulate it.
b) Design one CMOS inverter using Tanner tool. Take width of PMOS two times larger than NMOS.
Simulate the circuit and plot VTC curve.
KIIT University
School of Electronics Engineering
___________________________________________________________________________________
Spring End Semester Laboratory Examination 2017
VLSI LABORATORY (EC-3094)
Marks for performing experiment and associated answer: 20 Time: 1.5 hr
Question:
a) Design a 4-bit substractor using verilog. Also write the test bench for this and simulate it.
b) Design one CMOS inverter using Tanner tool. Take width of PMOS two times larger than NMOS.
Simulate the circuit for an input clock frequency of 10MHz and load capacitance of 2pF.Plot input
and output waveform.
Question:
a) Design a 4x1 multiplexer using verilog. Also write the test bench for this and simulate it.
b) Implement one half adder circuit using FPGA board and Vivado tools.
KIIT University
School of Electronics Engineering
___________________________________________________________________________________
Spring End Semester Laboratory Examination 2017
VLSI LABORATORY (EC-3094)
Marks for performing experiment and associated answer: 20 Time: 1.5 hr
Question:
a) Design one J-K flip flop using S-R flip flop in verilog. Also write the test bench for this and
simulate it.
b) Implement one 4bit up counter circuit using FPGA board and Vivado tools.
Question:
a) Design one J-K flip flop using D flip flop in verilog. Also write the test bench for this and
simulate it.
b) Implement one 4bit down counter circuit using FPGA board and Vivado tools.
KIIT University
School of Electronics Engineering
___________________________________________________________________________________
Spring End Semester Laboratory Examination 2017
VLSI LABORATORY (EC-3094)
Marks for performing experiment and associated answer: 20 Time: 1.5 hr
Question:
a) Design one S-R flip flop using T-flip flop in verilog. Also write the test bench for this and
simulate it.
b) Implement one full adder using FPGA board and Vivado tools.
Question:
a) Design one 4-bit up counter in verilog. Also write the test bench for this and simulate it.
b) Implement one clock divider circuit using FPGA board and Vivado tools.
KIIT University
School of Electronics Engineering
___________________________________________________________________________________
Spring End Semester Laboratory Examination 2017
VLSI LABORATORY (EC-3094)
Marks for performing experiment and associated answer: 20 Time: 1.5 hr
Question:
a) Design one 4-bit up down counter in verilog. Also write the test bench for this and simulate it.
b) Design one CMOS inverter using Tanner tool. Take width of PMOS two times larger than NMOS.
Simulate the circuit and plot VTC curve.
Question:
a) Detect the overlapping sequence 1010 using Mealy FSM. Design the logic circuit using verilog
and simulate its testbench.
KIIT University
School of Electronics Engineering
___________________________________________________________________________________
Spring End Semester Laboratory Examination 2017
VLSI LABORATORY (EC-3094)
Marks for performing experiment and associated answer: 20 Time: 1.5 hr
Question:
a) Detect the non-overlapping sequence 1110 using Mealy FSM. Design the logic circuit using
verilog and simulate its testbench.
Question:
a) Detect the overlapping sequence 1010 using Moore FSM. Design the logic circuit using verilog
and simulate its testbench.
KIIT University
School of Electronics Engineering
___________________________________________________________________________________
Spring End Semester Laboratory Examination 2017
VLSI LABORATORY (EC-3094)
Marks for performing experiment and associated answer: 20 Time: 1.5 hr
Question:
a) Detect the non-overlapping sequence 1011 using Moore FSM. Design the logic circuit using
verilog and simulate its testbench.
Question:
a) Design one 4-bit down counter in verilog. Also write the test bench for this and simulate it.
KIIT University
School of Electronics Engineering
___________________________________________________________________________________
Spring End Semester Laboratory Examination 2017
VLSI LABORATORY (EC-3094)
Marks for performing experiment and associated answer: 20 Time: 1.5 hr
Question:
a) Design one 4-bit up counter using J-K flip flop in verilog. Also write the test bench for this and
simulate it.
b) Design one CMOS inverter using Tanner tool. Take width of PMOS two times larger than NMOS.
Simulate the circuit for an input clock frequency of 10MHz and load capacitance of 2pF.Plot input
and output waveform.
Question:
a) Design one 4-bit down counter using J-K flip flop in verilog. Also write the test bench for this
and simulate it.
b) Design one CMOS inverter using Tanner tool. Take width of PMOS two times larger than NMOS.
Simulate the circuit and plot VTC curve.
KIIT University
School of Electronics Engineering
___________________________________________________________________________________
Spring End Semester Laboratory Examination 2017
VLSI LABORATORY (EC-3094)
Marks for performing experiment and associated answer: 20 Time: 1.5 hr
Question:
a) Design one 4-bit up counter using D flip flop in verilog. Also write the test bench for this and
simulate it.
b) Design one CMOS inverter using Tanner tool. Take width of PMOS two times larger than NMOS.
Simulate the circuit and plot VTC curve.