The 30th Annual Conference of the IEEE Industrial Electronlcs Society, November 2 - 6, 2004, Busen, Korea
Application of New PGA-based Top-Performance Digital Control
Techniques to PWM Power Converters.
A. Fratta, Member, IEEE, G.Griffero, P. Guglielmi, S. Nieddu and G.M. Pellegrino
A. Fratta, G. Griffero, P. Guglielmi, S. Nieddu G.M. Pellegrino, Dipartimento di Ingegneria Elettrica Industriale, Politecnico
di Torino, C.so Duca degli Abruzzi 24, 10129 Torino Italy, e-mail : (antonino.fratta, giuseppe.gricro, paolo.gugliemi,
stefano.nieddu, gianmario.pellegrino)@polito.it
Abstract- In the field of PWM power converters, the
newel low-cost FPGAs are investigated ~LSalternative digital
control devices. The paper would show how FPGAs allow for
unprecedented performances A comparative overview of DSP
and FPGA is camed-out on loop dynamics vs PWM ripple and
noise immunity. The FPGA-based topperformance solution is
defined and applied, based on oversampling and parallel
processing techniques. An FPGA-based development PCB has
been designed and realized accordingly suited to control three
merent inverters and two H-bridge converters. The new
control concepts are applied to coupled DUDC H-bridge boost
converters as the strongest test bench due to multiple PWM
properties. Experimental performancesare very satisfactory.
I. INTRODUCTION
In the last decade PWM power converters have been
increasingly applied together with digital control. The
general adoption of DSPs would have been settled for next
standardization. Flexibility, integration and cost have been
spent as the main key-points, at least with respect to
possible control analog implementations.
On the other hand, digital control is known to lose some
performance within PWM systems, in the balance between
controI dynamics and immunity to PWM environment. In
addition, flexibility and integration levels are not still
satisfactory, comparing the computation and WO resources
to the growing-up requirements of power converters.
A renewed interest is devoted to the latest FPGAs as an
alternative technology for digital control realization [ 11. It
appears more suited than DSPs for the realization of all the
key-points of digital control and it could be intermediate in
performance between analog and DSP solutions.
The novel performances of WGA-based digital control
are proposed in the paper and experimentally tested. A new
development confro1 board has been developed, where a
low-cost P G A is able to control and manage up to five
different PWM converters.
At first, the limit performances of different digital PWM
current loops are compared, among DSP solutions and
novel ones exploiting FPGA properties. Particular concern
is devoted to feedback sampling [2] and averaging
techniques [3], jointly realizing the best PWM ripple
immunity and improving control dynamics at the same time.
The H-Bridge DCDC converter is used as the strongest
experimental test bench because two different PWM current
ripple properties must controlled at the same time, as
already established and analysed in detail [4,5,6,7].
0-7803-8730-91041$20.00Q2004 I EEE
810
IL TOP-PERFORMANCE
FPGA-BASEDCURRENT
LOOP.
On the basis of one general digital current control loop
structure, different digital control solutions are defined
depending on feedback sampling and modulation index
refresh techniques.
I1.A. Reference current digital control loop.
A reference control structure is depicted in Fig. 1. In
PWM applications, U 0 timing is quite strictly imposed by
PWM requirements.
Tsw ;TswR
V
rt, -+ sm
WHJ
DIGITAL
Feedback samples must be accurately kept with respect
to modulating triangular PWM carrier, in order to
theoretically cancel any PWM ripple from the wanted mean
value. As known, in an ideal current loop the PWM ripple
current crosses zero at both triangular PWM carrier
vertexes: this would be true only without any PWM
command delay or load model parasitic parameter.
The digital loop part is strictly related to the control
algorithm and its computation time. However, in PWM
systems, the control output is the reference modulation
index, which must be refreshed only on the triangular PWM
carrier vertexes to prevent from duty errors and unwanted
commutations. The output S/H symbolizes the requirement.
As a result, at least two U 0 time rates are possible, one
and two times per PWM period, corresponding to the PWM
carrier vertexes. More complex oversampling and averaging
techniques could apply on feedback signal. This is why
several closed-loop dynamic properties arc possible.
In any case, the time-delay between the feedback mean
value sample and the index refresh dominates the limits of
closed-loop dynamic performance. Referring to Fig. 1, the
total loop delay time comprises also the PWM command
transfer, driving and execution delays of hardware parts.
Equivalently to time-delays, analog feedback filters are
disposed to improve the rejection to so called switching This effect is resulting also in acoustic noise, since it
noise and PWM ripple high-frequency content, thus depends on operating modulation index, as particularly
requiring further adjustment of feedback samples [Z]. highlighted in 3 D VSI inverters.
With reference to Fig.3, the highest DSP performances
1I.B. Ideal basic DSP loop {one sample and refresh). are practically achieved by averaging the two last feedback
The application of the general concepts are evidenced in samples, greatly improving the immunity to PWM errurs
Fig. 2 for the ideal basic DSP PWM current loop, that is and related limit cycling. Averaged equivalent feedback
without any parasitic delay and parameter. One current samples are reported in Fig. 3 as iik.3/Tand i ~ + ~ .
sample and one index refresh are provided in each PWM In the case, the regulator calculations must be operated
period: the feedback sample it.] is adopted to generate the twice per period, in order to perform valid double index
output index Dk.as input to the PWM comparator. refresh. Ideally, lo be compared with (2), the closed loop
In this case, the total loop delay would be the sum of the delay time becomes T , , sum of: 1/4Txwfor averaging and
digital regulator sampling-to-refresh rate (Tsw) and the S/H 1/2Tsw for computing, (3/4Tsw from equivaIent feedback
holding function effect. The SM function equals that of a sampling time to output SEI sample); l/4Tsw for SM
zero-order-hold according to ( I ): holding function, one-half the one related to ( I )
In Fig. 3 the current samples are slightly displaced with
ZOH(sTsw)=(l-e-sTw)/ STSW (1)
respect to PWM carrier vertexes, as in practice realized due
Its equivalent delay is one-half the period (7&7), so that
to PWM command delays d f p w ~and to phase lag of input
the total ideal closed loop delay time is (2):
analog filter. All these H W non idealities can be summed up
Tdel = ( 3 / 2 b S W . (2) in an equivalent HW delay AtHW. The total delay with
Triangular canier double index updating and double averaged sampling is (3):
\ / I
del = TSW 4- &HW (3)
d M * I
where the first term is for the ideal case and the second
4 1
t one synthesises all other (HW) effects.
1I.D. The perfect PWMfilter.
The perfect PWM ripple rejection is obtained by
averaging an analog variable over a complete PWM ripple
3
I
period. The transfer function of such perfect analog PWM
tk-i k filter is reported as (4):
Fig.2 Sampling and refresh in a ideal basic DSP conrro1 scheme. A V G ( ~=) (1 - e-sTsw )/STSR (4)
I1.C. Double sampling and PWM-ripple rejection. The related Bode diagrams in magnitude and phase of
AVG(s) are reported in Fig. 4, showing the filtering holes
With reference to Fig.3 sketch, several combinations of
for all P W M harmonics.
U 0 sampling appear possible, whenever the processor is
able to develop all the calculations in less than one half the
PWM period. The best dynamics could be theoretically
achieved in common microcontrollers or DSPs by sampling
and refreshing twice per PWM period.
As an example, with reference to Fig. 3 sketch:
- Dk is function only of the sample ;
- Dk.lnis function only of the sample ik.l .
Unfortunately, a peculiar drawback arises by increasing
the regulation gain to theoretically possible values. This is a
limit cycle on all variables at fundamental PWM frequency,
particularly pointed-out on reference modulation index,
which arises due to amplified propagation of even small
PWM current ripple errors on the feedback samples. Wg.4 Bode diagrams in magnitude and phase for perfect PWM filter.

II. E. Eflective oversampling and averaging techniques.

This perfect filter would require analog or continuous
implementation, which should be far from wanted
integration and cost levels.
On the other hand, very fast multiplexed AID converters
\ are available at low cost, which are able to provide several
$-I tk.I/Z 4 samples in common PWM period values. The related
Fig. 3 DSP techniquesby managing two U 0 samples per PWM period. managing procedure can be easily implemented in a FPGA,

81 1
exploiting its VO flexibility and inner capability of parallel
processing. A possible oversampling scheme is proposed in
Fig. 5, and actually realized in the development PCB. Each
n-bit (8-bit) sample is provided by the multiplexed AID
converter, each signal is oversampled m times (8 or 16)
within its own PWM ripple period, obtaining a p-bit (1 1 -bit
or 12-bit) output word for each digital signal output.
Incwmrud bus p bii
Ms Rc istff'
Conhd Imp
Fig. 5 h c t i c a l oversampling implementation scheme based on multi-
plexed A/D converter and FPGA management.
This oversampling strategy is effective only if the
number of samples (m) is high enough, since at
oversampling frequency no magnitude attenuation can be
realized without outer H.F. analog filter.
A practical limit condition is reported in Fig. 6, to be
compared with the perfect P W M filter in Fig. 4. The
oversampling rate is m=8 and the analog HF filter, designed
by three equal real poles, is placed to perform a phase
response equal to that in Fig. 4 below the PWM frequency.
Fig. 6 Bode diagrams of magnitude and phase in digital PWM fdter:
oversampling rate = 8; rhree-pole analog filter.
1I.F. Novel top-perfomnce PWM current-loop.
The adoption of FPGA allows for straightforward and
fast realisation of parallel processing. As an example, Fig. 5
reports the data bus structure avoiding any interference
between oversampling and closed-loop processes.
The oversampling stategy can be freely applied in order
to provide the "freshest" mean value just before the next
PWM carrier vertex, by the leading time strictly needed to
perform the few calculation steps of the current loop.
Thanks to the high FPGA clock frequency, the calculation
time is near to vanish with respect to PWM period (less
812
than 2 p at ''low'' clocks 35 and 70 MHz).
As a resuit, in the case of double output refresh of the
reference modulation index, the total closed loop delay time
is reported (5):
dei = (3/4)Tsw + Atcorc + ktpm (5)
The first "theoretical" part is obtained by summing up
the perfect PWM filter delay (T,J2) plus the output S/H
response (Tsd4 by double refresh). The second one
can be really lower than PWM period and it could be even
disregarded. The third one is not avoidable and it is part of
the HW equivalent delay characterizing DSP solutions.
The proposed current loop structure is presented in Fig.
7, where a simple PI regulator is adopted. The propofiional
gain K p would be as high as possible to reduce the
propagation of parameter uncertainty. The integrative term
should be limited to avoid any wind-up in large step
response and recovery from saturated operation. At the
purpose, a complete feed-forward strategy is adopted,
compensating for addictive disturbance and also for
dynamic response correction (up to achieve dead-beat
control performance).
This is why the integrative term is limited to what strictly
needed to cover only the load-voltage estimation error (6):
Hg.7 Topperformance current loop smcture.
HI. NEW FPGA CONTROL OF A N H-BRIDGECONVERTER.
The new FPGA-based control has been applied to a
DUDC H-Bridge converter, showing peculiar ripple
properties in the two differing controlled current modes.
iIi.A. Converter structure and control modes.
The H-Bridge converter structure is depicted in Fig. 8.
Two legs are coupled to the battery and to each other
through a single magnetic device ( T 4 reactor), performing
the wanted coupling to the battery (common mode) and
mutual leg decoupling (differential or magnetizing mode).
Then, the converter control can not be directly related to
phase variables because stored energies aren't [6,7].
 Proper phase-to-mode transformations must be realized -Mi ,A, ,A 7

for all the phase variables requested to control the current

common- and differential- modes.
This transformation matrix is expressed as U in (7),

(7)

and it is used in (8) for current vector transformation:

The -mode current components are related to LLpha~e

quantities, that is the common-mode current is one-half the
battery current while the differential-mode one is the reactor
magnetizing current.
The PWM properties are dramatically improved by
simply shifting to each other the H-Bridge legs commands
by one-half the modulation period, according to Fig. 9 plots
and the general (steady state) relationship (9):
mA (4 = mB (1- rs, / 2 ) (9)
lban
\.
As a result, the common-mode moduiation index m,, is a
time function showing a PWM ripple period equal to one-
half the PWM leg period, while the differential-mode
modutation index mdm holds the fundamental PWM
k %*I
frequency and it is an AC variable.
Common-mode inductance is set trading-off cost vs.
t t lit t t 11t It1
PWM ripple requirements, while differential-mode
inductance is set high enough to disregard (for design) the Idm

current circuIation between the H-Bridge legs. New core
structure and specialised materials (iron and ferrite) are
adopted by decoupling the two flux modes, thus exploiting
at best their properties. Very compact and efficient
solutions have been successfully tested accordingly [6,7].
On the DC-link capacitor side, the half-period shifting samples are summed up and the equivalent delay is TslJ4
dramatically reduces its rms ripple current requirement [4].
1II.B. Differentialmode current loop,
As depicted in Fig. 9, the differential-mode current holds considering the total loop delay (10) is reduced with respect
the fundamental PWM frequency. Therefore it must be
controlled accordingly with common PWM variables
requirements, as an example those of a 3CD VSI. The phase
current measurements are kept according to the
oversampling strategy over a whole PWM period.
In the experimental case, 16 samples are summed up for
each PWM carrier vertex as shown in Fig. 9. The equivalent
PWM filter delay is T& according to (4).
The cor~trolloop is realised as in Fig. 7, however a low
proportional gain Kp is adopted in order to assure the
Fig. 9 H-Bridge converter mode of operation @ Mcm<O (V+1/2 VmJ;
from top to bottom: PWM carrier and modulation indexes; legs com-
mands; common and differentialmode index functions; mode currents;
current samples distribution and summarion for the two control modes.
In the experimental case reported in Fig. 9, only 8
accordingly. The control loop is as in Fig. 7, executed over
a current ripple period (one-half a PWM period). The
closed-loop gain can be set to a maximum value,
to (5):
Tdel = TSW + ~ m l + c &PWM (10)
1II.D. Control tasks and time schedule.
According to H-Bridge properties, both mode control
loops contribute to leg commands generation [5]. The
reference leg indexes (MA*,MB*) are obtained as shown in
Fig. 10, by applying the inverse transformation matrix U- to
the mode indexes resulting from the two control loops.
I

system stability also in case of ferrite (differential-mode) ivb

saturation.
The loop is performed twice a PWM period, so the total
A+FW & 41
Regulator U-
delay is Tdp,= 3/4. T,, + + AIpwM according to (5).
IIIC. Common-mode k p d current loop.
As a peculiar property of the H-Bridge modulated
according 10 (9), common-mode P W M ripple frequency is
twice the PWM one, as in Fig. 9. Therefore its mean value T
TriangulmCarrier
can be cafculated over each one-half the PWM period. Fig. IO PWM leg commands resultiiig from -mode current regularon.

813
 The control tasks are scheduled as in Fig. 11: common
and differential-mode current loops are realised twice in the
PWM period, each adopting proper current samples in order
to keep the freshest mean value. The calculation time is
really short with respect to the PWM period, so that in the
same time slot the voltage regulation is performed as well.
Let us note the control loop data bus and ALU are busy
only for 2ps (voltage and currents) over 50ps (half PWM
period), so that other control tasks can be easily positioned
in time wi$out need of other parallel processing resources.
Fig. 11 H-Bridge convener control tasks schedule.
IV. FPGA-BASEDDEVELOPMENT CONTROL BOARD.
W.A. System specijkations and PCB description.
The PGA-based development PCB is shown in Fig. 12,
where different functions and their lay-out are evidenced. It
has been designed for an U 0 control capability of up to
three 3@ inverters and two H-Bridges. The PCB is
equipped accordingly providing 24 channels at wanted
oversampling rate (24x16 samples/period 100p.s) by
adopting three low-cost (half-flash) &bit 8channel ADCs.
Fig. 12 PGA-based development PCB with evidenced lay-out.
814
The P G A manages on-board Flash and SRAM
memories, position transducers (encoder, resolver) and
serial interfaces, PWM output buffers and all HW devices.
The FPGA performs all SW functions, however a small
outline DSP is embedded for monitoring and supervising
functions through serial communication.
W.B.Experimental setup.
A series of tests has been carried-out up to full power
ratings. The experimental set-up reported in Fig. 13 allows
for power circulation between equal DUDC converters
regulating common DC-link voltage without load.
Parameters for each H-Bridge Boost are: 600p.H;
Lh=3mH; c,,=2opF; Cp28pF.
----
1
--
%==)vc ;--]--q
I
1----
Boost I
+bat W I
----A
Fig. 13 Experimental sec-up.
According to Fig. 14, the DC-link voltage is regulated by
adjusting the current reference of both Boosts, which are
mainly set to opposite values by a feed-forwarded power set
point. The DC-link voltage feedback is kept applying the
oversampling strategy over a whole PWM period.
m samples
average
Fig. 14 Voltage loop structure.
The loops calculations are scheduled as in Fig. 15 and
executed twice the PWM period far each Boost. The
triangular carriers are shifted by a quarter of modulation
period for further improvement of the DC-link quality.
I -
Fig. 15 Conuol rasks schedule adopted for the tem,
v. EXPERIMENTAL RESULTS.
The tests have been carried out controlling the DC-link
voltage at 400V and circulating variable power from a small
variable voltage source simulating a battery pack.
Fig. 16 reports the two common-mode currents (nearly
opposite) by circulating 3kW at 250V input battery voltage.

Fig. 16 Common mode currenu Il.5NdivI and DC-link voltage
[SOV/div]: I = 20pddiv.
One -I-Bridge control response to circulating power
steps are reported in Fig. 17 and Fig. 18 (battery voltage
290V). The proportional gain is set to a practical maximum
value, achieving slightly underdamped step responses. The
differential-mode current loop response is completely not
affected by, obviously excluding the PWM ripple
waveform.
These very satisfactory responses are obtained even
without dynamic compensations or dead-beat control, which
can be superimposed to cancel any overshoot.
Ag.17 Convener P positive currenl step response; Lm {2.5Aldiv], &
[lAldivI, Vc [IOV/div], offset Vc = 400V; t = 1OOpJdiv.
Fig. 18 Converter P negadve current step response; i, [3A/div], i b
815
It can be noted each power step represents a voltage-loop
disturbance, due to magnetic energy variation with current.
However the DC-link voltage response is nicely good in
spite of a very low DC-link capacitance value.
VI. CONCLUSIONS.
The FPGA properties have been applied searching for
novel digital control concepts and performances.
A suitable comparative analysis points out how the DSP
PWM control constraints can be overcome.
New breakthrough concepts and performances have been
defined and implemented in a low-cost FPGA development
PCB, realized and presented for the first time.
A hard experimental test-bench has been adopted, based
on coupled H-Bridge D O C converters requiring different
PWM current-loop properties and small-capacitance DC-
link voltage control.
The experimental results are completely successful,
confirming the capabilities of the novel PWM control
concepts.
Their application to other power conversion structures is
under development, like for 3@ PWM VSI.
vn. REFERENCFS
E. Monmasson, and Y . A Chapuis, Contributions of FPGAs to the
Control of Electrical Systems, a Review, IES Newsletter, vol. 49,
no. 4, 2002, pages 8-15.
S-H.Song, J-W. Choi, and S-K. Sul, Current Measurements in
Digitally Controlled AC Drives, IEEE Indusrry Applications Mugu-
zine. luly/August 2000. pages 51-62.
A. de Casun, P. Zumel, 0. Garcia, T. Riesgo, and J. Uceda,
Concurrent and Simple Digital Controller of an AC/DC Converter
Wiih Power Fkctor Correction Based on an FPGA, IEEE Trunsac-
rims on Power Elecrronics, vol. 18, no. I , January 2003, pages 334-
343
[41 A Fratta, P. Gugtielmi, F. Villara, A. Vagati, Efficiency and EOSI-
effectiveness of AC drives for electric vehicles improved by a novel
boost DC-DC conversion structure, 1998 IEEE Workshop on
Power Electronics in Trunsportarion (WPET98), pages 11-19.
[51 A. Fratta, P. Gugliehi, G.M.Pellepo, E Scapino, F. Villa@
Efficient Modulation Tecnique and NL Control of H-bridge Boost
Converters for Battery-Supplied AC Motor Drives, IEEE Inremu-
fiond Symposium on Iduslnal E~ectronics(ISIE 99). 1999, pages
8068 12.
A. Fratta, G.Griffero, S. Nieddu, G.M.Pellegrino, F. Villata, New
Hybrid kon-Femte-Core Coupling Reactors Upgrade Effectiveness
of H-Bridge-Based Power Conversion Structures, 2002 Inrema-
tionaE Symposium on Industrial Electronics (IEEE-ISIE 20021, July
8-1I , 2002, LAquila, Italy,vo1.3, pages 8 8 4 8 8 9 .
A. Fratta, G, Griffem, S, Nieddu, G.M.Pellegino, E Villata,
Inductive Three-Level V.-Supplied conversion Cell by new Hybrid
Coupling Reactor Family , IEEE-IAS Annual Meeting, Pittsburgh
(USA) October 13-18. 2002. vol. 4, pages 2378-2385.
A. Fratta, G. Griffem, S. Nieddu. Comparative Analysis among
DSP and FPGA-based Control Capabilities in PWM Power
Conveners, The 30th A n n u l Conference of the IEEE Induslrial
Elecrronics Society (IECONWJ, Busan, Korea, November 2-6,
2004.