8085 Processor:
Introduction:
The 8085 has been one of the popular microprocessor of its time. Due to its unique
characteristics, this processor is still regarded as a standard by both industries and
academics for imparting skills sets on microprocessor basics.
8085 Introduction:
The salient features of 8085 p are:
a. It is a 8 bit microprocessor.
b. It is manufactured with N-MOS technology.
c. It has 16-bit address bus and hence can address up to 216 = 65536 bytes
(64KB) memory
d. Data bus is a group of 8 lines, D0 D7.
e. Address bus is a group of 16 lines, A0-A15.
f. The first 8 lines of address bus and 8 lines of data bus are multiplexed and
forming as AD0 AD7.
g. It has five hardware interrupts and eight software interrupts.
h. It supports serial communication
i. It has Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
j. It has four special purpose register naming as an 8-bit Accumulator, a 8-bit
Flag register, a 16 bit stack pointer (SP) and a 16 bit program counter (PC)
k. It requires a signal +5V power supply and operates at 3.2 MHZ single phase
clock.
l. It is enclosed with 40 pins DIP (Dual in line package).
8085 consists of various units and each unit performs its own functions. The
various units of a microprocessor are listed below
Accumulator:
It is a 8 bit general purpose register.
It is connected to ALU (Arithmetic Logic Unit)
So most of the operations are done in accumulator
Programmable Registers:
The general purpose registers are used to store the temporary information during
the execution of a program.
There are six other general purpose registers in 8085 namely B, C, D, E, H and L.
these are used for various data manipulators. Each is 8-bit registers.
A pair of register together can be used as a register pair to hold 16-bit. There are
BC, DE and HL register pair.
Program Counter:
It is a 16 bit register used to point the location from which the next instruction is to
be fetched
When a single byte instruction is executed PC is automatically incremented
by 1.
Upon reset PC contents are set to 0000H and next instruct is fetched
onwards.
Stack Pointer:
This is a temporary storage memory 16 bit register. Since there are only 6 general
purpose registers, there is a need to reuse them.
The 8085 maintains stack in memory
Whenever stack is to be used previous values are pushed on stack and then
after the program is over these values are popped back.
Flag register:
It is a group of 5 flip-flops used to know status of various operations done
The flag register along with the accumulator is called PSW
7 0
S Z X AC X P X CY
S : Sign flag is set when result of an operation is negative.
Z : Zero flag is set when result of an operation is zero.
AC: Auxiliary Carry flag is set when there is a carryout of lower nibble or lower four
bits of operation.
CY: Carry flag is set when there is a carry generated by an operation.
P : Parity flag is set when result contains even number of 1s rest are done care
Flip-flops.
Instruction Register:
When an instruction is fetched, it is executed in instruction register. This register
takes the op-code value only
Instruction Decoder:
It decodes the instruction from instruction register and then to control block.
Interrupt Control:
There are five interrupt request pins through which the 8085 may be interrupted.
These are 1) TRAP, 2) RST 5.5, 3) RST 6.5, 4) RST 7.5 and 5) INTR.
The serial communication can be performed by using SIM and RIM instructions.
Two signals are associated with Direct Memory Access naming as HOLD and
HLDA.
The HOLD is produced by the DMA controller for requesting the busses from the
Processor control.
It indicates that another master is requesting for the use of address and data buses
and control busses.
Then the HLDA is produced by the Processor to the DMA controller as the
acknowledgement of receiving the HOLD signal.
Now the CPU completes the current machine cycle and then relinquishes the use of
buses to the DMA controller.
The processor can regain the buses only after the HOLD is removed. i.e., after the
completion of data transmission between Memory and the IO device.
The PC (program counter) is set to zero, and interrupt enable and HLDA flip-flops
are reset. The program execution starts at zero location. The input signal need not
be synchronized with the clock.
The CPU outputs the RESETOUT signal which is synchronized with the clock. It
may be used to reset the other associated circuits.
THE 8085 PINOUT and Signals:
S0, S1 2 Output
The 8085A uses a multiplexed Data Bus. The address is split between the
higher 8bit Address Bus and the lower 8bit Address/Data Bus.
During the first cycle the address is sent out. The lower 8bits are latched into
the peripherals by the Address Latch Enable (ALE). During the rest of the
machine cycle the Data Bus is used for memory or l/O data.
The 8085A provides RD, WR, and lO/Memory signals for bus control.
An Interrupt Acknowledge signal (INTA) is also provided.
Hold, Ready, and all Interrupts are synchronized.
The 8085A also provides serial input data (SID) and serial output data
(SOD) lines for simple serial interface.
In addition to these features, the 8085A has three maskable, restart interrupts
and one non-maskable trap interrupt. The 8085A provides RD, WR and
IO/M signals for Bus control.
Status Information
Status information is directly available from the 8085A. ALE serves as a status
strobe. The status is partially encoded, and provides the user with advanced timing
of the type of bus transfer being done. IO/M cycle status signal is provided directly
also. Decoded So, S1 Carries the following status information:
HALT, WRITE, READ, FETCH
S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of
address are multiplexed with the data instead of status. The ALE line is used as a
strobe to enter the lower half of the address into the memory or peripheral address
latch. This also frees extra pins for expanded interrupt capability.
This priority scheme does not take into account the priority of a routine that was
started by a higher priority interrupt. RST 5.5 can interrupt a RST 7.5 routine if the
interrupts were re-enabled before the end of the RST 7.5 routine.
The TRAP interrupt is useful for infected errors such as power failure or bus error.
The TRAP input is recognized just as any other interrupt but has the highest
priority. It is not affected by any flag or mask. The TRAP input is both edge and
level sensitive.
Note that during the I/O write and read cycle that the I/O port address is copied on
both the upper and lower half of the address. As in the 8080, the READY line is
used to extend the read and write pulse lengths so that the 8085A can be used with
slow memory. Hold causes the CPU to hand over the bus when it is through with it
by floating the Address and Data Buses.
System Interface
8085A family includes memory components, which are directly compatible to the
8085A CPU. For example, a system consisting of the three chips, 8085A, 8156,
and 8355 will have the following features:
2K Bytes ROM
256 Bytes RAM
1 Timer/Counter
4 8bit I/O Ports
1 6bit I/O Port
4 Interrupt Levels
Serial In/Serial out Ports
In addition to standard l/O, the memory mapped I/O offers an efficient l/O
addressing technique. With this technique, an area of memory address space is
assigned for l/O address, thereby, using the memory address for I/O manipulation.
The 8085A CPU can also interface with the standard memory that does not have
the multiplexed address/data bus.
MEMORY ORGANIZATION
Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64 KB.
Program memory - program can be located anywhere in memory. Jump, branch
and call instructions use 16-bit addresses, i.e. they can be used to jump/branch
anywhere within 64 KB. All jump/branch instructions use absolute addressing.
Data memory - the processor always uses 16-bit addresses so that data can be
placed anywhere.
Stack memory is limited only by the size of memory. Stack grows downward.
First 64 bytes in a zero memory page should be reserved for vectors used by
RST instructions.
Memory Interfacing:
The main step in the design of microprocessor system is to interface the
microprocessor with memory.
The following logically clear points need to be kept in mind to interface 8085
microprocessor with memory.
The decoder is selected when G1: (. )=1. When selected the input signals at A, B, C
get translated to Y0 to Y7 in the following manner.
Consider that a 2 KB chip 2716/6116 is to be interfaced to the microprocessor for
address starting from 0000 to 07FFH. In this case A15, A14, A13, A12 and A11
are all equal to 0. Thus 2716/6116 can be interfaced to 8085 in the following
manner.
I/O PORTS:
Interfacing I/O devices:
Using I/O devices data can be transferred between microprocessor and the
outside world
This can be done in groups of 8 bits using the entire data bus. This is called
parallel I/O
The other method is serial I/O where one bit is transferred at a time using the
SID and SOD pins on the microprocessor
Since an I/O device is treated as memory location this interface is called memory
mapped I/O.
The I/O devices are identified by port number and memory locations are
identified by address. The memory read/write operations and I/O read/write
operations are being performed on different software instructions.
Whether the read/write operations are being performed on memory or I/O or in the
other words whether the information on address and data lines is meant for a
memory location or an I/O device this identification is done by separate signals.
This is called I/O mapped I/O interface since I/O devices are treated separately
from memory
When the I/O device speed and microprocessor speed do not match ie., when the
I/O device is slower than the microprocessor checks the status of the device. If the
device is not ready the microprocessor continuously checks the status of the device
till it becomes ready
Interrupted I/O:
The previous data transfer scheme is quite inefficient since the microprocessor is
kept being for the slower I/O device. The remedy to the problem is to allow the
microprocessor to do its job when the device is getting ready and when the device
is ready the microprocessor can transfer the data. This can be achieved through
interrupt.
Each memory or I/O operations require a particular time period called machine
cycles. Each machine cycle consists of 3 to 6 clock periods/cycles referred to as 7
states
Op-code fetch
Memory read
Memory write
I/O read
I/O write
INTR acknowledge
Bus idle
Representation of Signals:
Clock Signal:
Single Signal:
Group of Signals:
The machine cycles are the basic operations performed by the processor, while
instructions are executed. The time taken for performing each machine cycle is
expressed in terms of Tstates. One T-state is the time period of one clock cycle
of the microprocessor.
Representation of Signals:
Clock Signal:
Single Signal:
Group of Signals:
The operation during the first two clock cycles T1 and T2 is the same as that of the
op-code fetch machine cycle. However in this case in the T 1 clock cycle the
memory address of the data byte to be read is loaded to the address bus AD 0
AD7, A8 A15
T3:
goes high to indicate the end of the read operations
Data is transformed to the register mentioned
If memory is slow is if the data cannot be accessed in one clock cycle it will
pull the READY pin low indicating that memory is not ready to transfer the data.
The READY pin is sampled in the T2 clock cycles of each machine cycle. If
READY is low then wait states are entered between T2 and T3 clock cycles till the
READY pin become high.
The HOLD and HLDA signals are used for direct memory access. Using DMA
bulk data transfer can take place between the memory and the I/O device by
passing the microprocessor. DMA is initiated by the external logic. It requests for a
HOLD state by inputting the HOLD signal high. The microprocessor responds by
entering the HOLD state and outputting the HLDA signal high
The signal at the HOLD pin is sampled during T2 in each machine cycle
If HOLD is high at this time HLDA is output high during T3
As soon as high but is detected at HOLD a two clock period HOLD state
initiation sequence begin. HOLD state begins at T4
The HOLD state terminates two clock periods after the HOLD signal goes
low
The 8085 has five interrupt request pins. These are TRAP, RST 7.5, RST 6.5, RST
5.5 and INTR. The locations of Interrupt Service Routine (ISR) for all interrupts
except INTR are fixed. Interrupt requests on TRAP, RST 7.5, RST 6.5, RST 5.5
cause the 8085 A to generate its own internal interrupt acknowledge instruction
and branch to respective ISRs
The 8085A samples INTR during the second last clock period of each
instructions execution.
Even though memory is not being accessed PC contents are put on the
address bus during T1.
8085A makes S0, S1 and IO/ high. These can be decoded by the interrupting
device as advance acknowledgement.
Goes low during T2. The external logic must use both as device select
signal and as a strode signal to identify the time internal during which the
interrupt acknowledge instruction code must be placed on the data bus.
The external logic may respond to signal by replacing the restart (RST) or
call instruction object code on the data bus.
The instruction code is decoded in the subsequent clock cycles.
If the instruction code is for the call address instruction the interrupt
acknowledgement extends to two more machine cycles.
The second and third acknowledgement machine cycles are I/O read cycle
where IO/ and are output high and is pulsed low.
The external logic pulses two bytes of address (of ISR) on data bus in
synchronization with thus creating a call instruction.
INTERRUPTS
Interrupt is a process by which the external devices use microprocessor for
servicing by suspending the routine process served previously.
After completion of interrupt, the processor resumes its original operation.
The status of peripherals requesting service is checked frequently by the
processor and it is known as polling.
Types:
o Hardware Interrupt
o Software Interrupt
Hardware Interrupt:
When the interrupt is due to external peripheral devices then it is known as
hardware interrupts. There are 5 hardware interrupts are available in 8085 from
highest priority to lowest priority are given below.
o TRAP
o RST 7.5
o RST 6.5
o RST 5.5
o INTR
TRAP:
RST 7.5:
It is a vectored interrupt.
It has second highest priority.
Positive edge triggered and it is internally stored by DFF until it is cleared
by software interrupt.
It can be enabled or disabled by using SIM instruction
RST 6.5 & RST 5.5:
EI Enable Interrupt
DI Disable Interrupt
RIM Read Interrupt Mask
SIM Set Interrupt Mask
Software interrupts in 8085:
The 8085 has eight software interrupts from RST0 to RST7. The vector address for
these interrupts can be calculated as follows
Interrupt number x 8 = vector address
Therefore the vector address for interrupt RST 5 is 0028H
Pending Interrupt:
The RIM instruction loads the status of the interrupt mask the pending interrupts
and the contents of the serial input data line, SID into the accumulator.
Thus it is possible to monitor the status of interrupt mask, pending interrupt and
serial input.
There are number of interrupts. When one is being serviced other interrupt requests
may occur. If the interrupt requests are of higher priority, 8085 branches program
control to the requested interrupt service routine.
But when all the interrupt requests are of lower priority, 8085 stores the
information about these interrupt requests. Such interrupts are called pending
interrupts.