6496 IEEE SENSORS JOURNAL, VOL. 16, NO.

17, SEPTEMBER 1, 2016

ISFETs in CMOS and Emergent Trends

in Instrumentation: A Review
Nicolas Moser, Student Member, IEEE, Tor Sverre Lande, Fellow, IEEE, Christofer Toumazou, Fellow, IEEE,
and Pantelis Georgiou, Senior Member, IEEE

Abstract Over the past decade, ion-sensitive field-effect

transistors (ISFETs) have played a major role in enabling the
fabrication of fully integrated CMOS-based chemical sensing
systems. This has allowed several new application areas, with
the most promising being the fields of ion imaging and full
genome sequencing. This paper reviews the new trends in front-
end topologies toward the design of ISFET sensing arrays in
CMOS for these new applications. More than a decade after the
review of the ISFET by Bergveld which summarized the state of
the art in terms of device and early readout circuity, we describe
the evolution in terms of device macromodel and identify the
main sensor challenges for current designers. We analyze the
techniques that have been reported for both ISFET instrumenta-
tion and compensation, and conclude that topologies are focusing
on device adaptation for offset and drift cancellation, as opposed
to system compensation which are often not as robust. Guidelines
are provided to build a tailored CMOS ISFET array, emphasizing
that the needs in terms of applications are the keys to selecting
the right pixel architecture. Over the next few years, the race
for the largest and densest array is likely to be put on hold to
allow the research to focus on new pixel topologies, ultimately
leading to the development of reliable and scalable arrays. A wide Fig. 1. 3232 ISFET sensing array for applications such as chemical imaging
range of new applications are expected to motivate this paper or DNA sequencing [5].
for at least another decade.
applications such as electrolyte imaging or DNA sequencing,
Index Terms ISFET, review, chemical sensor, trapped charge,
drift, ISFET instrumentation. which have motivated the research over the past ten years.
ISFETs have allowed to carry out numerous projects, amongst
them the Human Genome Project, which has seen the price
I. I NTRODUCTION of genome sequencing dropping at a rate steadier than Moores
law since 2010 [3].
M ORE than 40 years have passed since the introduction
of the ISFET by Bergveld in 1972 [1]. Yet the prospects
of a CMOS-based chemical sensor are still numerous nowa-
Bergveld, who developed the idea of using a floating gate
transistor as a chemical sensor, shared his insights into the
days, including inherent scalability, low-power processing and first 30 years in a review paper [4] which has now become a
improved SNR [2]. Large-scale integration of these sensors reference in the field of Isfetology, cited more than a thousand
has been demonstrated since then by conceiving lab-on-chip times. The paper indeed provides essential information on the
platforms structured as microarrays with a high density of state of the art, summarising the theory behind the sensor
ISFET pixels, as illustrated in Fig. 1. Although the sensor was operation, listing common techniques used for its fabrication
first developed in the context of neurophysiological measure- or mentioning typical applications. However, there are two
ments, this biochip revolution has increased their popularity in main points that have proven to be essential for the future
development of Lab-on-Chip systems integrating such sensors.
Manuscript received April 4, 2016; revised June 8, 2016; accepted First, Bergveld presents the early ISFET readout configura-
June 13, 2016. Date of publication June 28, 2016; date of current version tions and identifies their benefits as well as limitations, usually
August 3, 2016. This work was supported by the Engineering and Physical
Sciences Research Council within the Centre for Doctoral Training in High including basic instrumentation extensively used with MOS
Performance Embedded and Distributed Systems under Grant EP/L016796/1. transistors. Then some of the issues related to the ISFET
The associate editor coordinating the review of this paper and approving it are mentioned, including drift and REFET fabrication for
for publication was Prof. Janice Limson.
The authors are with the Department of Electrical and Electronic differential measurements, but no viable solution is presented.
Engineering, Institute of Biomedical Engineering, Imperial College These have paved the way to a whole new area of ISFET
London, London SW7 2AZ, U.K. (e-mail: n.moser@imperial.ac.uk; research, focusing on improving robustness and resolution
t.lande@imperial.ac.uk; c.toumazou@imperial.ac.uk; pantelis@imperial.
ac.uk). of readout, as well as compensating for the major device
Digital Object Identifier 10.1109/JSEN.2016.2585920 challenges in efficient ways.
1558-1748 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
MOSER et al.: ISFETs IN CMOS AND EMERGENT TRENDS IN INSTRUMENTATION
Fig. 2. ISFET structure. (a) Schematic view [4]. (b) Extended gate for implementation in unmodified CMOS technology [2].
The overall divergence in sensing topologies reported in
papers published in the last decade have illustrated that more
and more groups are now giving up on classical configurations
in favour of novel implementations. In this context, the authors
have felt the need to review the progress carried out in the
field and identify the most promising directions to pursue in
the near future. However, due to the high number of papers
published each year on ISFETs, it has become difficult to write
an overview of the entire research area. Instead, it is now
necessary to specifically delimit the scope of the review, tar-
geting a certain sub-field e.g. chemical experimentation, device
physics and readout electronics, or an application such as DNA
sequencing and cellular imaging. This review paper focuses on
summarising the major advances in ISFET instrumentation,
which were mostly reported in the last 15 years. In particular,
it will focus on ISFET arrays, which the authors believe are the
most promising structure considering their numerous prospects
in terms of applications. We will set the emphasis on front-end
topologies introduced in the literature, along with their benefits
and limitations. These will not be presented historically, but
rather classified according to their topology and performance
in terms of sensitivity and compensation capabilities. This
falls in with the quest for conceiving a dense, reliable and
scalable ISFET array enabling massive parallelism and high
throughput.
In terms of device modelling, improvement brought to the
initial theory includes the derivation of a more intuitive ISFET
macromodel which will be presented in Sec. II. However, for
the past few years, the main contribution lies in the character-
isation of the common nonidealities in the ISFET behaviour
and the identification of the sensor challenges. These include
trapped charge in the device, leading to significant mismatch
between the pixels of the array in a similar fashion to Fixed-
Pattern Noise (FPN) which is a common issue for the design of
CMOS imagers [6]. Designers must also face temporal drift
of the sensor output and noise contributions from both the
chemical interface and the analogue front-end. We discuss all
these issues in Sec. III and define the criteria which must be
met by the readout topology. Various architectures have been
reported in the literature, and in Sec. IV we classify them
according to their instrumentation technique, measurement
6497
type and output encoding scheme. Their capabilities in terms
of compensation have also become essential over the past few
years to allow for integration as part of a full sensing platform.
This is highlighted in Sec. V, which enlists the achievements
carried out so far to answer for the challenges previously
described. These compensation strategies are diverse, as some
research groups focus on device adaptation while others prefer
to implement a solution on a system level. In Sec. VI, we
provide our own guidelines on the design of a custom ISFET
system, tailored for a certain set of specifications determined
by the application. In Sec. VII, building upon the work
described throughout this review, we make an attempt at
predicting the evolution of the research in the field of ISFET
instrumentation in the next few years. Finally, we provide a
discussion and a conclusion in Sec. VIII.
II. F UNDAMENTALS OF ISFET O PERATION
We describe the Ion-Sensitive Field-Effect Transis-
tor (ISFET) as a MOS transistor with the gate connection
separated from the device and tied to a reference electrode
(typically Ag/AgCl) in contact with the solution, and an
insulating membrane replacing the gate oxide. Its structure
is depicted as a schematic view in Fig. 2a [4].
The device operation as a chemical sensor consists in a
shift in its threshold voltage with the ion concentration of
the solution in which the electrode is immersed. The ISFET
characteristic can be derived using the site-binding model
for ions on the insulating membrane and considering the
capacitive double layer formed by the Helmholtz plane and the
Gouy-Chapman layer [7], [8]. The ISFET threshold voltage is
then expressed as the equivalent MOSFET threshold voltage
and a chemical contribution
Vth(ISFET) = Vth(MOSFET) + + SN pH (1)
where is a constant chemical term, SN is the ideal pH
sensitivity, designated as Nernstian sensitivity and typically
equal to 59 mV/pH, and is the sensitivity deviation due
to the double layer capacitance [2]. The dependency of the
ISFET I-V curve over pH is characterised in Fig. 4a. The
first implementation of ISFETs in CMOS was reported by
Wong and White [10] in 1988. Although studies have been
6498
Fig. 3. ISFET behavioral macromodel [2], [9].
Fig. 4. ISFET I-V curve [2]. (a) pH dependency. (b) Capacitive scaling
effect.
carried out to characterise the effect of various gate materials
on ion selectivity and device sensitivity [11][14], the ISFET
has been mainly used for its pH detection capabilities. For
that purpose, the initial ISFET fabrication procedure involved
post-processing steps on the floating gate of the ISFET to
make the device pH sensitive, such as the deposition of a
Ta2 O5 membrane [10]. In 1999, Bausells et al. [15] reported a
novel way of fabricating a pH-sensitive ISFET in unmodified
CMOS technology. This allowed the integration of ISFETs
with standard silicon System-on-Chips with no requirements
of extra fabrication step, providing major benefits such as
scalability and low cost [16]. This extended-gate technique
involves using the inherent top passivation material (Si3 N4 )
as the insulating layer, granting pH sensitivity to the device.
IEEE SENSORS JOURNAL, VOL. 16, NO. 17, SEPTEMBER 1, 2016
The structure of fabrication is shown in Fig. 2b. However,
ISFETs fabricated in a standard CMOS technology suffer
from a degradation in performance compared to when post-
processing of the gate material is allowed, as highlighted
in [17]. In particular, nonidealities include extra attenuation in
the chemical input signal through capacitive division, leading
to a reduction in sensitivity illustrated in Fig. 4b.
All the effects mentioned hereabove can now be summarised
in a simplified ISFET macromodel, first derived in 1999 [9]
and depicted in Fig. 3. In this model, we emulate the threshold
voltage shift as a change in the floating gate voltage of the
device, modulated by the pH through capacitive effects. The
dependence is as follows
VG = VG Vchem = VG ( + SN pH) (2)
The device can now be operated in the same regions as its
MOSFET counterpart. Originally, designers considered strong
inversion solely, yielding the typical quadratic expression
for the saturation region between the gate voltage and the
current
1 W
I D = Cox (VG  S Vt h )2 (3)
2 L
where Cox , , W and L are device parameters, Vt h is the
threshold voltage and VG  S is the chemically dependent term
determined by Eq. 2. As an alternative to this mode of
operation, Georgiou and Toumazou [2] have introduced the
use of weak inversion pH sensing i.e. at low VG S . In this
region, diffusion of carriers dominates over drift which yields
an exponential relationship
 
VG S S N
I D = I0 exp (4)
nUt
where we assume V D S > 4Ut , I0 is a characteristic current, n
is the subthreshold slope factor and Ut = kT /q is the thermal
voltage. This mode of operation provides benefits such as low
power processing and high intrinsic voltage gain, and, as will
be discussed in Sec. IV, has been used extensively in current
mode readout circuits.
This section has introduced the ISFET as a chemical sensor
and characterised its pH dependence. Integration in CMOS
technology has been presented to allow for inherent scalability
of silicon technology at low cost. The extended-gate technique
also removes the requirements for post-processing steps and
further promotes monolithic integration. Lastly, the typical
MOSER et al.: ISFETs IN CMOS AND EMERGENT TRENDS IN INSTRUMENTATION 6499

modes of operation have been described, including strong and

weak inversion, paving the way for the upcoming description
of ISFET readout methods. However, we have mostly con-
sidered ideal behaviour thus far, and must now introduce the
challenges specific to ISFETs.

III. C HALLENGES
A major contribution which the last decade has brought to
this field lies in the several nonidealities which the ISFET
suffers from. In this section, we highlight the challenges which
have often been ignored by designers at the time, but have now
become a greater priority for the conception of scalable and
reliable analogue front-ends for ISFET sensing. In particular,
we set the focus on the effects which cause a deviation from
the ISFET model described previously.
In this work, we focus on the use of inherent CMOS
passivation material for our systems, without any modifica-
tion, directly from fabrication. However, this layer is not a
perfect insulator which would typically be deposited using low
pressure chemical vapour deposition at high temperature [2],
and as a result can have defects. A CMOS passivation layer
tends to gradually degrade when in contact with the solution,
however has sufficient lifetime for short term use. This is
suitable for one time tests in which the chip is then disposed
of. Such usage makes sense at present due to the economies
of scale of CMOS which allows it to be made incredibly
cheap. Other groups have worked on post-processing to deposit
new insulating membranes which results in more reusable and
reliable devices [18], however this adds additional cost and
complexity on an already working unmodified solution which
we consider in this review.
As a consequence, we must deal with common issues Fig. 5. Non-ideal effects of CMOS based ISFETs [2]. (a) Offset and
including trapped charge and drift in the sensor. The former capacitive division. (b) Slow temporal drift.
induces an offset in the threshold voltage and hence mismatch
between devices, while the latter causes a slow variation of this
threshold with time due to surface effects on the passivation where Vt c is the offset due to trapped charge, whose value
layer. Furthermore, the incidence of temperature and noise on is different for each device. This is equivalent to a shift in
the sensor are well-known problems of MOS transistors and the I-V curve of the transistor, as demonstrated in Fig. 5a.
also affect the ISFET operation. The last nonideality consid- Provided that we use a common reference electrode for all
ered in this review has already been touched upon, and lies the sensors, this offset introduces mismatch between the pixels
within the capacitive attenuation also due to implementation as they now each exhibit a different behaviour. Therefore,
in unmodified CMOS technology. These challenges are now during signal quantisation, stringent requirements are set on
described in further details. the ADC as it must be given a high dynamic range to cover the
whole output range, with suitable resolution to cover the signal
A. Trapped Charge range. This highlights the need for an offset compensation
It is well-known that charge gets trapped on the float- scheme cancelling any discrepancy between the ISFETs and
ing gate of the ISFET, most likely due to charge transfer guaranteeing identical electrical responses for all the sensors.
during chip production, introducing an offset in its thresh-
old voltage. In 2008, Milgrew and Cumming [19] estimated B. Drift
the threshold voltage variation as standing between 4 V
and 1 V for standard AMS 0.35m, with significant Drift is exhibited through a slow monotonic change in the
discrepancies between processes, dies and throughout the threshold voltage of the ISFET and originates from a transport
array. phenomenon at the interface between the insulator and the
Trapped charge can be accommodated on the previous solution [20]. Its effects are shown experimentally in Fig. 5b,
model by considering an extra voltage source in Fig. 3 [2]. where the output voltage clearly increases with time without
The ISFET floating gate voltage is then expressed as any pH change.
The main challenge for drift compensation has always
VG = VG Vtc Vchem (5) lied in its unpredictable behaviour. In general, this effect is
6500
modelled as an exponential relationship of time. This is the
case for instance when the ISFET is operated in the feedback
mode with a constant current biasing, where the variation is
quantified as an average drift rate of 8.1 mV/min for the first
minute [21]. It has indeed been shown that drift depends on
several factors, such as the solution pH, the surface material
and the device size [22]. Hence compensation methods cannot
rely on mathematical dependencies and must be designed to
be robust to any temporal gate voltage variation.
C. Capacitive Attenuation
In the macromodel of Fig. 3, it was already mentioned
that the additional passivation capacitance due to the imple-
mentation in standard CMOS processes led to extra attenu-
ation of the signal. This can be computed as the capacitive
division [2]
C pass
VG  = VG 
C pass + (Cox Cd )/(Cox + Cd )
where Cox and Cd are the oxide and depletion capacitances
respectively. The passivation capacitance C pass can be approx-
imated by considering the two passivation dielectrics Si 3 N4
and Si O2 used for chip insulation, which yields
Si3 N4 Si O2
C pass = (W L)chem 0
Si3 N4 t Si O2 + Si O2 t Si3 N4
with W and L the dimensions of the sensing area, 0 , Si3 N4
and Si O2 the permittivities of free space, silicon nitride
and silicon dioxide respectively, and t Si3 N4 and t Si O2 the
passivation thicknesses. Further characterisation for the cou-
pling effects are provided through the introduction of the
parameter in [22].
It is obvious that this effect is present if the system is
to be designed in unmodified CMOS technology. Replacing
the Si 3 N4 layer with other pH-sensitive membranes might
improve the sensitivity of the ISFET, although the trade-off
would be to allow special technologies or extra processing.
This will not be further considered in this review.
D. Temperature Effect
As an electronic device, the ISFET is influenced by temper-
ature variations due to thermal agitation affecting the electron
flow, but also to a variation in the solution pH. A typical
temperature curve for the sensor is shown in Fig. 6 [23]. As a
rule of thumb, it has been reported that the ISFET undergoes
a significant output change equivalent to 1 pH every 7 K
around the ambient temperature [24]. Therefore, temperature
instability of the device can not be overlooked, although it
is far more complicated than for its MOSFET counterpart.
Several additional chemical contributions are indeed to be
considered [23], [25] : the reference electrode, the pH sensitive
electrolyte/insulator interface, which is usually predominant,
the semiconductor part and the solution pH. Similarly to drift,
it seems that the research focus has been set on developing
robust compensation methods, at the expense of deriving an
accurate analytical temperature dependence for the sensor.
IEEE SENSORS JOURNAL, VOL. 16, NO. 17, SEPTEMBER 1, 2016
Fig. 6. Temperature dependence of the ISFET (W/L = 30) [23].
E. Noise Corruption
The sensor noise sets the analogue readout resolution,
(6)
which makes its analysis essential. Additionally to the usual
MOSFET contribution, the chemical interface is also known
to add noise to the sensing system [26].
The predominance of chemical noise over electrical noise
is strongly dependent over the technology. In standard
0.35m CMOS technology, recent measurements taken by
Liu et al. [26] have revealed that the chemical noise exceeds
(7)
the corresponding MOSFET by one order of magnitude. In the
paper, the focus is set on flicker noise and the 1/f relationship is
clearly identified for both contributions. Similarly, Miscourides
and Georgiou [27], focusing on electrical noise, have con-
firmed better SNR in the case of small devices for a given
CVCC test structure. Their analysis was extended to deeper
technologies, as they have demonstrated that scaling down
the ISFET led to an increase in input-referred noise and gate
attenuation.
It is clear from this research that very few papers include
noise discussion. To this date, the field still requires a unified
model including both MOS and chemical contributions for the
flicker and thermal noise.
The aforementioned design challenges, all originating from
the physics of the ISFET, are the main factors to consider when
building systems for embedded chemical sensing. Although
the next sections will focus on ISFET analogue front-end
topologies, these nonidealities will be the conductive thread
throughout this review, as the authors strongly believe that
they must be addressed to conceive the autonomous sensing
platform which fields such as DNA sequencing require. One
can find surprising that most papers describe only a few of
these effects, which is the reason why this review has aimed
at describing them more extensively. Fortunately many tech-
niques have been reported to compensate, often independently,
for these effects. However, before describing these, we need
to take a step back and focus on the general instrumentation
used for ISFET readout.
IV. I NSTRUMENTATION FOR C HEMICAL R EADOUT
We have emphasised that the use of ISFETs as chemical
sensors has grown over the past few years. This has led
MOSER et al.: ISFETs IN CMOS AND EMERGENT TRENDS IN INSTRUMENTATION
researchers to move on from the early differential and source-
and-drain follower topologies, and develop novel front-end
architectures for pH readout. The main configurations are
presented in this Section, and their characteristics are identi-
fied. In particular, we will be classifying the implementations
according to two criteria : single or differential sensing, dis-
crete or continuous encoding. All of the mentioned techniques
and their main features are summarised in Table I.
A. Single Measurements
Most of the ISFET front-end configurations involve a single
device topology achieving continuous time sensing. Among
these, we distinguish two main categories of readout methods.
Firstly, the device can be operated in feedback mode i.e. it
is biased at a constant current and its output is fed back to
the reference electrode, whose voltage Vref varies with the
pH [4], [21]. This method is however not very convenient since
the non-constant biasing requires a distinct reference electrode
for each pixel, which leads to a rather complex experimental
setup. For that reason, it was generally left out by the research
area over the past few years and will not be further considered
in this review. A common alternative is to globally bias the
reference electrode, so that the threshold voltage directly varies
with the pH, as reflected by the ISFET theory. This technique
is widely used in current systems and typically consists of two
configurations.
1) Source and Drain Follower or Constant-Voltage,
Constant-Current (CVCC): In such configuration, already
introduced by Bergveld [4] and presented in Fig. 7(a), the
ISFET current I D and drain voltage V D S are fixed and the
source voltage VS reflects the change in pH. The main benefits
of this technique lie in its compactness, requiring only a device
and a switch for a pixel. Such a design is also immune to
capacitive scaling of the pH signal at the floating gate of the
ISFET.
2) Current-Mode Readout: More recently, current-mode
readout has gained in popularity as part of the new generation
of analogue ISFET front-ends. In such topology, it is the
ISFET output current I D S which is measured, allowing for
in-pixel current-mode processing and its well-known benefits,
including inherent compatibility with weak-inversion oper-
ation [2]. Reported topologies include a current feedback
readout for stable DC operation [33], an adapted current
conveyor using ISFETs as input transistors, which can be
arranged in numerous configurations [34], and a circuit based
on the translinear principle [28] to yield an output current
proportional to the pH, shown in Fig. 7(b). Although large
transistors dimensions might be required for matching pur-
poses, current mode also paves the way to new compensation
methods, as will be discussed in the next section.
Over the past decade, differential measurements and CVCC
readout have become, along with current mode configurations,
the foundations for more advanced architectures. In particular,
as the field started to grow the desire to implement ISFETs
as part of large and dense arrays, some papers have reported
pixel architectures with minimal readout and no compensation
methods for fast and efficient measurements. In that context,
6501
Nemeth et al. [29] introduced a pixel with an ISFET and two
switches, shown in Fig. 7(c). Although the resemblance of this
structure with simple CVCC is undeniable, they have paved
the way to the development of a reset scheme inside the pixel,
enabled through an in-pixel switch such as M2 .
Still in the context of pixel architectures, it is interesting
to see that the ISFET field has only recently started to find
inspiration in the imaging area, which has developed multiple
techniques for the design of robust and massively parallel
arrays. Several papers have started to focus on the integration
of Active Pixel Sensors (APS) using ISFETs, which happen to
similarly share the reset scheme previously mentioned. Ways
of implementing an ISFET APS include the replacement of
the photodiode by the ISFET [35], or the use of the ISFET as
the standard buffer [30], which is illustrated in Fig. 7(d).
In turns, this search for novel ISFET front-end architectures
paves the way to opportunities for encoding the pH value in
other domains than analogue, providing improved robustness
and additional benefits compared to traditional methods. In
particular, the integrate-and-fire topology, which encodes the
pH in frequency, is inherently compatible with event driven
readout [36], which grants new opportunity for conceiving
low-power array designs. However, this solution was aban-
doned probably due to the complexity of signal processing in
the spike domain, involving specific ADC topologies.
In the context of encoding the pH in digital domain, in-pixel
quantisation allows to grant robustness to the signal at device
level to minimise degradation due to noise or interference.
This represents an opportunity to push down the noise floor
of the system and hence improve the chemical SNR. A suitable
example of such topology is pH-to-time conversion, which has
been growing as a popular readout method. Its simplest and
most compact implementation relies solely on one inverter
with complementary ISFETs [31], [37] shown in Fig. 7(e).
The devices are capacitively coupled to a triangular wave
and the pH modulates their switching point, hence the output
pulse width is chemically-dependent. This PWM-based pixel
has the benefit of providing in-pixel quantisation of the pH
signal, protecting it against noise corruption and parasitics
degradation. It has been integrated as part of an array with
a fine on-chip Time-to-Digital Converter (TDC) as the ADC
with a delay line and a thermometer-to-binary coder [38].
More recently, the authors have reported a topology which
mixes several of the aforementioned techniques. The circuit
is adapted from the APS structure as shown in Fig. 7(f), and
based on the discharge of a capacitor through the ISFET as
well as a periodic reset scheme [32].
It is often the case that the need for compensation leads to
new readout architectures inherently compatible with certain
adaptation schemes. Feedback to the gate topologies are part
of this category, involving extra connections to the floating
gate of the ISFET through a capacitor (PG-ISFET) [39] or a
switch [5]. Since the reason for which they were developed
in the first place is to achieve trapped charge compensation,
these structures will be discussed in Sec. V.
There exists another type of readout which has not been
discussed so far. In 2009, Wong et al. [40] have introduced
discrete ISFET logic for applications where the exact value of
6502 IEEE SENSORS JOURNAL, VOL. 16, NO. 17, SEPTEMBER 1, 2016

TABLE I
R EADOUT M ETHODS FOR ISFET-BASED I ON D ETECTION
MOSER et al.: ISFETs IN CMOS AND EMERGENT TRENDS IN INSTRUMENTATION
Fig. 7. Overview of the main analogue front end topologies for single ISFET readout. (a) CVCC or source and drain follower readout [4]. (b) Current-mode
topology based on the translinear principle [28]. (c) Standard CVCC pixel readout [29]. (d) APS-based structure [30]. (e) ISFET inverter [31].
(f) pH-to-Time encoding [32].
pH does not need to be determined, such as detecting a specific
gene in a DNA sequence. Once again, this is based on the
pH variation of the switching threshold of an inverter, although
this time it is not quantified but rather used to offer a simple
yes/no answer due to small pH changes. The same principle
can then be applied to other components which can be used
as comparators, such as a NAND gate [40], a switch [41] or
a Schmitt trigger [42]. However, as far as the authors know,
a complete system has never been reported and tested for the
target application, hence the idea is still in need of validation.
B. Differential Measurements
Bergveld already reported several differential topologies in
his review paper [4], which makes it one of the first ISFET
readout configurations. Its attractiveness is apparent, since dif-
ferential sensing allows for cancellation of any common-mode
voltage between the two sensors, minimising the effects of
drift, noise and temperature on the measurements. Wong and
Whites ISFET-operational amplifier [43], shown in Fig. 8(a),
was the first reported differential sensing scheme. Its structure
is based on two ISFET/MOSFET differential pairs in a buffer
configuration, followed by a differential amplifier, causing any
change in pH between the two sensors to be reflected at
the output. This provides cancellation of temperature effects
6503
common to the input transistors as well as drift in both ISFETs.
In this early implementation, the sensors were processed
with special coating on the gate of the ISFETs to yield
different pH sensitivities, such that one of them was used as a
reference device, submerged in a buffer solution of known pH.
Indeed, since the ISFET is not suited for absolute pH readout,
it only makes sense to use a reference sensor to compare pH
variations with respect to another solution.
In that context, similar topologies have attempted to pair
the ISFET with an ion-insensitive sensor adopting the same
electrical behaviour and denoted as REFET. Bergveld [4]
devoted a major part of his review to the fabrication of
these REFETs, typically achieved once again by depositing
a polymer membrane on top of the floating gate of the ISFET,
which however inevitably leads to discrepancies in electrical
behaviour between the two FETs. Although a detailed descrip-
tion of the evolution of REFET fabrication methods over time
is beyond the scope of this review, the device is still popular
nowadays as it is still extensively described in the literature.
The ISFET-REFET sensing front-end is usually implemented
directly as part of an input pair [44], [47], in which case
the main challenges, as highlighted by Sohbati et al. [47],
include the unknown offset due to trapped charge and
the intrinsic high gain of the input pair. An example of
6504
Fig. 8. Overview of the main analogue front end topologies for differential ISFET readout. (a) ISFET-ISFET differential amplifier configuration [43].
(b) ISFET-REFET voltage-clamped configuration [44]. (c) ISFET and REFET pixels in sensing arrays [45]. (d) ISFET-ISFET chemical Gilbert cell [46].
ISFET-REFET input pair is illustrated in Fig. 8(b) in the form
of a differential voltage clamped circuit [44]. As opposed
to this direct pairing, other systems prefer the use of
a single device topology such as a source-drain-follower
configuration, followed by an instrumentation amplifier
between the outputs of the ISFET and REFET cells [45], as
shown in Fig. 8(c). Such a structure requires an additional
amplifying stage, which occupies more silicon area and does
not solve the unknown offset issue. Nevertheless, systems have
been reported for ISFET-REFET differential measurements in
the context of sensing arrays, especially in the case where the
pixel output is quantised as the values can be subtracted easily.
Milgrew et al. [45] have indeed characterised the above pixel
as part of a small array, and Garner et al. [48] have reported
the same concept of reference pixel as part of a full system.
Although we have already mentioned the use of
ISFET-ISFET differential measurements, so far one of the
sensors was always post-processed to reduce its pH sensi-
tivity. Instead, it may be desirable to yield the differential
output of two similar ISFETs measuring different ion con-
centrations. Such a system was presented in a conventional
way by Chodavarapu et al. [49], subtracting the outputs of
two pixels in a similar manner than described previously.
Nabovati et al. [50], on the other hand, have implemented
IEEE SENSORS JOURNAL, VOL. 16, NO. 17, SEPTEMBER 1, 2016
the two sensors directly as part of a differential configuration
which combines differential measurements with current mode
processing to yield an output proportional to the pH difference,
which they quantise using a sigma delta modulator. Similarly,
Kalofonou and Toumazou [46] presented a chemical Gilbert
cell (cf. Fig. 8(d)) where the differential pair consists of two
ISFETs, enabled by the aforementioned chemical translinear
principle [28]. Such ISFET pairs are essential for applications
where several chambers are needed. Indeed, it is often the case
that the application ultimately orients the decision between
differential and single architectures. As far as the literature is
concerned, it is still the case that most reported systems use
one device for sensing.
So far, we have focused on analogue front-end architectures,
in particular for ISFET pixels. We now need to review the
various compensation methods reported in the literature and
used in ion detection systems to ensure the best operation of
the ISFET as a chemical sensor.
V. I NSTRUMENTATION FOR C OMPENSATION
We have demonstrated that ISFETs in unmodified CMOS
technology suffered from significant non-idealities in their
electrical behaviour, including trapped charge, drift, tempera-
ture instability, capacitive scaling and noise corruption. When
MOSER et al.: ISFETs IN CMOS AND EMERGENT TRENDS IN INSTRUMENTATION
the first readout techniques were described in the Isfetology
review [4], it seems that compensating for these effects was
not part of the research objectives. Since then, it has become
clear that the robustness and efficiency of the system rely
on our effort to address these non-idealities through various
compensation techniques. As an illustration, let us consider the
shift in threshold voltage due to trapped charge. Such an offset
induces an uncertainty on the operating point of the device,
hence setting stringent requirements on the range of the ADC
for output quantisation, which can be relaxed by considering
compensation at device level.
Out of all these techniques, the most promising are gathered
in Table II and sorted accordingly. We will now look more
closely into these methods, introducing two categories, sensor
adaptation and system compensation.
A. Sensor Adaptation
In the first category, we incorporate the techniques which
affect the DC operating point of the ISFET to achieve sensor
compensation. These methods are performed at device-level
and as such, are usually the most efficient solutions in terms of
robustness and longevity of compensation. However, it should
be noted that most of these methods are combined with a
system-level compensation scheme, which handles the device
biasing accordingly.
Trapped charge is by far the most tackled ISFET non-
ideality in the literature, and a simple way of compensating for
this effect involves UV exposure. Milgrew and Cumming [19]
have shown in 2008 that exposing the ISFET to ultraviolet
light, through a small aperture directly above the device,
induces a gradual shift in the threshold voltage. The electrons
at the floating gate are indeed excited to overcome the potential
barrier at the sensor gate, allowing the threshold voltages to
converge with an accuracy of less than 10 mV after 10 hours of
exposure. However, this solution may not be convenient as it
involves post-processing for each die, which does not represent
a fast and scalable technique for large ISFET arrays.
Let us then focus on circuit-based methods, rather than
using extra processing on the dies. Most of the on-chip and
device-level techniques involve accessing the floating gate
of the ISFET. Although this is a straightforward solution, it
comes with major drawbacks, since it systematically reduces
the sensing performance of the device due to extra connectivity
at the floating node.
Let us consider for instance the Programmable
Gate-ISFET, or PG-ISFET, introduced in 2008 by
Georgiou and Toumazou [39] and seen as one of the
most promising techniques for trapped charge compensation
through gate voltage modulation. The floating gate is accessed
through a physical capacitor CC G , which allows to modulate
the trapped charge through a tuning voltage VC G , as illustrated
in Fig. 9(a). The trapped charge is thus cancelled provided
that
C pass Vt c = CC G VC G (8)
This technique is mainly beneficial because it sets the DC
operating point of the device in a robust manner, cancelling
6505
any offset, while guaranteeing through capacitive coupling that
the gate is kept a floating node. Also, it can be easily integrated
as part of an autonomous calibration scheme, to determine the
correct bias voltage. However, the extra capacitor results in a
reduction in chemical sensitivity, scaling down the chemical
C
voltage by CpassT
, where C T is the total capacitance at the
floating gate. Also, the addition of a component leads to extra
silicon area. Nevertheless, the prospects of additional control
on the ISFET for on-chip calibration may make up for its
drawbacks.
Along with the introduction of the device, several topologies
using PG-ISFETs were proposed for pH readout and device-
level compensation. The same authors have introduced an
adaptive readout with a feedback to the reference electrode
voltage to determine the pH value [52]. However, as explained
previously, reference electrode feedback is highly inconvenient
in the case of arrays, for issues related to a common refer-
ence electrode. Nevertheless, to compensate for the sensitivity
loss, architectures have been reported which apply capacitive
feedback from the floating gate to a source-and-drain follower
ISFET readout [51], [61]. In both cases, the scheme uses a
complex sequence of phases for its operation, including gate
offset reset and pH sensing. Alternatively, a unity-gain buffer
topology represented in Fig. 9(b) was also used to track the
chemical signal in-pixel [62], while biasing the programmable
gate through a DAC. This PG-ISFET technology is currently
not being used extensively for the design of large, scalable
and reliable ISFET arrays.
Similarly to the PG-ISFET, charge modulation at the float-
ing gate has been achieved using electron tunnelling. The
idea originates from an early paper reporting hot-electron
injection to cancel offset in p-ISFET [64]. By increasing
VS D to large voltages, the probability of impact ionisation
is increased and hence charges are able to cross the oxide
barrier and reach the floating gate. The work was then
pushed further by inducing electron tunnelling through the
gate oxide using an extra capacitance and diode connected
to the floating gate [65]. The solution was finally extended
for bidirectional use, to both add and remove electrons [63],
which is represented in Fig. 9(c). Although the architecture
looks similar to the PG-ISFET, it requires significantly higher
voltages to induce tunnelling, going as high as tenths of
Volts, as well as additional components. It was therefore
not pursued further in the literature or as part of a full
system.
As opposed to techniques which maintain a floating
gate for the ISFET, architectures have been reported which
connect a switch to the gate for offset reset [59], [66].
Hu and Georgiou [5] have reported a pixel configuration with a
direct feedback to the floating gate through a switch, illustrated
in Fig. 9(d). The readout involves two phases of operation.
In the reset phase, S0 is closed and the feedback fixes the
output voltage through the OTA to a constant value, indepen-
dent of the trapped charge. During the measurement phase,
S0 is open and the output tracks the pH change through the
capacitive division between the passivation capacitance and the
feedback capacitors. However, compensation is achieved at the
6506 IEEE SENSORS JOURNAL, VOL. 16, NO. 17, SEPTEMBER 1, 2016

TABLE II
C OMPENSATION T ECHNIQUES FOR OVERCOMING THE ISFET C HALLENGES
MOSER et al.: ISFETs IN CMOS AND EMERGENT TRENDS IN INSTRUMENTATION
Fig. 9. Architectures for ISFET sensor adaptation. (a) PG-ISFET [39]. (b) PG-ISFET Unity-Gain Buffer [62]. (c) Bidirectional Electron Tunnelling [63].
(d) Feedback to the Gate Topology through a Switch [5].
expense of leakage, which gradually corrupts the pH signal.
As a result, the measurement time is significantly reduced.
It should be noted that the scheme is also equipped with an
automatic gain calibration [67].
An alternative device-level method has been reported which
compensates for trapped charge using another terminal of
the ISFET. Using source voltage modulation and in-pixel time
encoding, the topology [32] implements an initial calibration
phase to drive the ISFET at a certain biasing point. Assuming
that the offset is smaller than 1.2 V, the method allows to
cancel the offset while not degrading the chemical signal
in terms of sensitivity or measurement time. This is still in
a research phase and must be further investigated through
experiments.
It is a fact that some of the aforementioned techniques for
offset cancellation can be used to compensate for slow drift
in the threshold voltage point of the device. The topologies
based on a reset phase may use periodic reset schemes for
drift cancellation, by resetting the device offset before each
measurement. In that sense, the readout time must be small
enough to guarantee proper operation of the sensing system.
As an example, Hu and Georgiou [5] have reported the use
6507
of their gate switch architecture for periodic drift reset, with
a period of roughly ten seconds.
As an alternative, Shah et al. [68], [69] have developed
a novel technique for periodic drift reset, which involves
modulating the reference electrode voltage. They have indeed
proven experimentally that cycling the vertical electric field of
the ISFET effectively resets the drift. Such a process is carried
out by cycling the reference electrode voltage Vre f between
the operating voltage and the source voltage of the ISFET.
By considering a period of around 15s, the drift was shown
to exhibit a repeatable pattern and hence its influence on the
measurements is attenuated. However, such variations in Vre f
will typically affect the readout. The feasibility of the cycling
of electric field will thus depend on the topology.
Both these techniques involve drift reset, which might com-
promise the measurement time if the resets are not performed
often enough. For that matter, it is often the case that software
processing is preferred to counteract drift. We will specify
these in further details in the next section.
In the case of temperature and noise compensation, device-
level adaptation techniques are not the most popular reported
solutions. In the former case, Aw and Cheung [70] have
6508
reported in 1988 the existence of an athermal point for the
ISFET, depending on the biasing condition of the device.
Almost two decades later, Chan and Chen [71], [72] presented
a system which dynamically biased the ISFET at this athermal
point, by varying the bias current as part of a simple source-
and-drain-follower readout. Their algorithm is computational
and based on external processing using a microcontroller, and
although it is considered as device adaptation, it is easy to
doubt its robustness due to a change in the athermal point with
pH and hence during the measurement. Laslty, Sohbati and
Toumazou [59] have proved that the aforementioned periodic
gate reset used to accurately set the DC operating point of the
device leads to a pH sensitivity independent of temperature,
for a current mode readout in weak inversion operation.
Although these conditions are restrictive, experimental con-
firmation of these results would grant the topology interesting
prospects for temperature compensation.
As for noise cancellation, only the aforementioned reset
transistor is able to reduce the flicker noise, in structures such
as APS [30], [35], [60] or pH-to-time pixel [32].
B. System Compensation
As opposed to device adaptation, system compensation does
not affect the sensor operation. Instead, the signal originating
from the analogue front-end is typically processed indepen-
dently through a digital method. As such, they are often useful
for more than one non-ideality of the ISFET.
Consider for instance differential measurements, which have
been presented in Sec. IV. Their capability for cancelling any
common variation in the two input devices grants them with
an improved drift, temperature and noise immunity, assuming
of course that these effects behave the same way in both
transistors. The technique has justified the large interest it was
given, although the requirement on two devices is stringent for
some applications.
The idea of differentiating the signal is definitely useful for
any type of small variations. Instead of differentiating in space,
let us now consider time difference. It should not come as a
surprise that most of the techniques for external signal process-
ing are once again borrowed from the imaging field. Amongst
the most popular, Correlated Double Sampling (CDS) comes
as a global solution for system compensation. Originally, CDS
is a switched-capacitor technique which cancels the undesired
offset in an amplifier, and requires two non-overlapping clocks.
Premanode et al. [73] have first applied it to ISFET sensing in
the context of drift cancellation. In such a system, the output
of the sampling phase indeed represents the difference of the
current and previous samples, considered drift free if the time
interval is short, and hence contains solely the information
on the pH variation. In a similar manner, flicker noise is
also attenuated. Later, Huang et al. [60], along with their
dual-mode APS structure, have added CDS for suppression of
Fixed Pattern Noise (FPN), demonstrating that the sampling
technique removed the dependence of the output over the
threshold volage, hence reducing any offset mismatch between
pixels. As such, at the cost of a clock and extra circuitry
to recover the signal, such as a low-pass filter, CDS is a
promising compensation technique.
IEEE SENSORS JOURNAL, VOL. 16, NO. 17, SEPTEMBER 1, 2016
Other differentiation techniques include baseline frame cali-
bration for trapped charge compensation, subtracting the mean
of the 99 captures at quiescence to the measurement, on a
pixel basis [74]. For drift cancellation, a software solution
was proposed which integrates the difference in consecutive
samples, assuming once again that the drift is slow compared
to the electrical change due to pH variation. The outcome is
an output with attenuated drift, even on a long time interval,
at the expense of external processing of the signal.
In the case of temperature, differentiation can be achieved
by summing the output with a signal of complementary
Temperature Coefficient (TC), such that the compensated
output exhibits a constant TC. This has been reported using
a diode [23], [70], but is also achieved with PTAT-CTAT
with ISFET [75] or imaging arrays [76]. For ISFETs specifi-
cally, this is typically unreliable since the temperature depen-
dence might depend on the pH value, hence the robustness
of the method is not guaranteed. Judging by the lack
of efficient schemes for temperature compensation, it is
likely that the best solution lies within on-chip temperature
regulators [48], [66], [77], [78], which also enable new
applications, such as on-chip PCR in the context on DNA
sequencing.
The last technique which the authors have considered
worth mentioning involves white noise cancellation through
averaging. Although this could be applied externally, several
topologies have reported embedded schemes to improve SNR
within the analogue front-end, including a global negative
current feedback [58], using current mode to perform simple
pixel averaging.
In this Section, we have reviewed a diverse range of
compensation techniques, offering design trade-off to the final
performance of the system. Several device adaptation solutions
might offer better robustness for trapped charge, whereas sys-
tem compensation still seems to be the most popular solution
for drift and noise. Despite several attempts, it is unsure
whether there is a technique allowing for robust temperature
compensation. Moving forward with this review, we will now
adopt a more critical view and provide further details on the
trade-off brought by each structure for the design of an ISFET
sensing system.
VI. D ESIGN OF A C USTOM ISFET S YSTEM
We now focus on guiding the reader towards the conception
of a tailored ISFET sensing system. In particular, we will
identify the main factors to be taken into account when
building the platform and which topologies provide the best
performance for given specification. We will base our study
on systems reported in the literature.
A. Application-Driven Requirements
An essential part of the specification for the readout is
application-driven. In that sense, the first step towards design-
ing an ISFET front-end is to identify the requirements from the
application. The range of applications has significantly grown
over the last ten years, as loads of novel ways of using the
technology were reported to motivate the research. We will
now provide a few examples for popular ISFET applications.
MOSER et al.: ISFETs IN CMOS AND EMERGENT TRENDS IN INSTRUMENTATION
1) Ion Imaging: Similarly to CMOS imaging, ion imaging
consists in mapping the ion concentration of the solution
onto the whole array, which is typically large and dense for
high chemical resolution. In particular, Nemeth et al. [29]
have carried out imaging of the diffusion phenomenon
when injecting citric acid into sodium hydroxide, map-
ping the progressive pH decrease throughout the array.
A large amount of these arrays were reported start-
ing from 2005, ultimately targeting imaging of simple
electrolytes [19], [29], [36], [74], [80] or extracellular
imaging [45], [53], [54]. In general, all have demonstrated
good performance as proton cameras. Desirable specification
for such arrays includes
compact pixel architecture and dense array for high
spatial resolution,
possibly high pH resolution,
varying measurement time,
high frame rate which may involve parallel processing.
2) DNA Sequencing: Without a doubt, DNA sequencing has
been the most popular and successful application of ISFETs as
part of massively parallel sensor arrays. Those so-called DNA
microarrays have appeared in the early 2000s as a massive
improvement compared to chemical techniques. In such a
configuration, each cell contains DNA strands of a particular
sequence, and the chain to be analysed is flushed, so that
hybridisations i.e. bondings between sequences occur inside
certain beads [78]. These reactions were tagged with fluores-
cent markers, such that they were detected locally using optical
methods [83], known to be bulky and expensive. A few solu-
tions were proposed for the detection of these hybridisation
processes on-chip, including electrochemical methods [84].
But nowadays, the ISFET has dominated the field due to its
integration in standard CMOS technology, causing inherent
sensitivity to pH and guaranteeing a scalability predicted by
Moores law. Along with the invention of Ion Torrent sequenc-
ing i.e. single nucleotide detection in a process denoted as
pyrosequencing, this has led to the development of fast, cheap
and dense CMOS DNA microarrays. This was successfully
demonstrated by Rothberg et al [18], who implemented more
than a million pixels and placed the beads at the top of
each ISFET, or Toumazou et al. [78], who demonstrated the
use of their recent chip sequencing platform for real-time
amplification and detection of DNA. A significant amount of
newly reported ISFET arrays are dedicated to DNA sequencing
applications [19], [48], [55], [56], [60], [81], although most
of those papers only mention the application as opposed
to demonstrating the performance of their system in a real
sequencing scenario. In fact, the quest for fast and cheap
sequencing has significantly contributed to the ISFET research,
providing motivation though scientific initiatives such as the
Human Genome Project, which aims at reducing the cost
of genome sequencing to $1,000. A more complete review
of DNA sequencing technologies is beyond the scope of this
paper, but interested readers will find an overview of the
evolution in sequencing platforms in [85].
DNA sequencing is a vast field, and while some are indeed
interested in sequencing the whole genome, others are focusing
on specific genes or on the detection on Single Nucleotide
6509
Polymorphisms (SNPs). In such cases, the requirements on
the size and the speed of the array are relaxed. We have
also touched upon the idea of ISFET logic in the case
where the system aims at solely identifying the presence
or absence of a gene. Overall, this leaves the following
requirements:
compact pixel architecture,
large array for faster sequencing,
pH resolution depending on the DNA concentration,
typically lower than imaging,
relatively short measurement time.
The frame rate represents the main difference between DNA
sequencing and ion imaging. Since the chemistry of hybridis-
ation tends to be slow, the detection does not typically require
high speed.
Additional functionality might be desired for a sequenc-
ing system. In order to perform on-chip DNA amplification
through Polymerase Chain Reaction (PCR), a temperature
regulation system must be embedded inside the system.
3) DNA Methylation Detection: One might wonder why yet
another section of this review is dedicated to DNA sequencing.
As a matter of fact, certain applications have been reported
using only several sensors, as opposed to the ISFET arrays
which this review has mostly focused on. For the sake of
covering a wider range of applications, we will mention the
detection of DNA methylation as a case study.
The context of the application lies within the detection
of methylation-based biomarkers in a particular gene, which
change its expression in the organism and may lead to an
early stage of cancer. The technology must therefore achieve
the sequencing of one methylated- and one non-methylated-
genes and compare their results to detect the presence of the
biomarkers, which is performed by developing chambers on
top of two ISFETs. Although early reports of the methodology
also include a third chamber for chemical reference [86], the
same authors have later realised that this comparison between
genes could be carried out easily through differential mea-
surements [46], more precisely the aforementioned chemical
Gilbert cell, whereby each ISFET is exposed to a gene. This
represents a perfect example of application-driven readout,
where the application allows the use of a certain topology,
here differential readout and hence provides direct advantages
such as attenuating all common nonidealities between the
sensors. This also significantly relaxes requirements of very
small sensor size and fast readout speed which are desired in
imaging arrays.
We have provided an example of specific requirements
which are typically not the ones of ISFET arrays. As such,
we will now return to the design of specific readout to achieve
the required specification of a sensing system.
B. Design Considerations
At this point, the authors would like to emphasise that
it is inconceivable to consider readout instrumentation and
compensation schemes independently. Although the early
review [4] has solely considered readout topologies for ISFET
sensing, these past 12 years have enabled the existence of cus-
tom readout circuitry, which integrates compensation methods
6510
Fig. 10. Simplified guidelines for the design of ISFET sensing system.
within their operation, as opposed to adding those techniques
to existing readout. This is the case for instance for the
PG-ISFET configurations [39], [51], [52], which has initiated
novel architectures including feedback to the reference elec-
trode or to the gate.
It is therefore difficult to present a golden rule to select the
best ISFET topology. Instead, we will be providing guidelines
regarding the specification to be considered when designing
the circuit. Fig. 10 represents a simplified schematic of these
guidelines and will be used to support our discussion.
1) Compensation Techniques: We start by focusing on
trapped charge and drift, which have been reported extensively
in the literature. In some situations, an embedded compen-
sation is not needed e.g. if the application allows for post-
processing of the dies through UV exposure, or if there
is no limitation on the range of the output ADC, with no
requirements on silicon area or power consumption. The same
holds for the drift, which tends to decrease significantly as the
reaction reaches equilibrium and hence some systems let some
time elapse before carrying out the measurements [29].
The lack of requirement for compensation methods allows
for high compactness of the array, at the expense of robustness.
CVCC readout or current-mode may involve a structure as
small as the combination of an ISFET and a switch per pixel.
In this particular situation, voltage-mode might be more ben-
eficial than current-mode, since it is immune to the capacitive
scaling effect at the floating gate and tends to involve smaller
transistors.
Increasing the size of the cell by adding the biasing circuit to
the simple two-device pixel offers several advantages, includ-
ing scalability, higher frame rate and larger ISFET chemical
sensing area, which in turns attenuates the capacitive scaling.
Should this be of interest, standard pixel structures such as
3-T or chemical APS are other candidates for a full sensing
array. This is the direction adopted by the imaging field.
Lastly, strong requirements on the minimisation of noise
degradation of the signal may lead to the use of in-
pixel quantisation. In particular, pH-to-time encoding can be
implemented easily in the form of an inverter [31] or an
IEEE SENSORS JOURNAL, VOL. 16, NO. 17, SEPTEMBER 1, 2016
APS-based discharging pixel [32]. As a drawback, correspond-
ing processing circuits need to be specific to PWM signals,
which differ from the general readout. Other encoding methods
such as spike processing [36] exhibit a large pixel size and
have yet to be improved to be considered in the design of
ISFET arrays.
It should be noted that although we are mentioning these
architectures without compensation, some baseline frame cali-
bration will need to be performed to estimate the initial trapped
charge and subtract it from the measurements, which can
be done externally. Overall, compensation techniques are
essential for robustness of the readout, and we now focus on
introducing these into the system.
2) Measurement Time: Should drift compensation be
desired additionally to offset cancellation, the time window
during which the measurement must be taken is essential to
determine whether a reset scheme can be used. For short
measurements, which the drift will not corrupt significantly,
any accumulated charge on the surface of the ISFET can
be cancelled between two readout phases. However, reset
schemes which involve a switch to the gate further reduce the
measurement time due to leakage. This effect has not been
quantified so far in the literature, but it is estimated that drift
will corrupt the signal after 5 to 10 seconds. As an alternative,
source voltage compensation is expected to offer a longer
readout time, but exhibits a limited trapped charge range. More
experimental tests need to be carried out on these structures
for further characterisation. Overall , this solution sums up to
using in-pixel device adaptation for both trapped charge and
drift which, as stated before, tend to lead to a more robust and
scalable array.
Longer measurements do not allow the use of reset and
therefore, drift compensation can only be achieved through
system compensation. These include CDS or software process-
ing, such as baseline frame calibration or other differentiation
techniques. Overall, they have shown good performance for
drift cancellation, although they involve external computa-
tional techniques which can sometimes be avoided by consid-
ering embedded schemes described previously. As for readout,
classical configurations such as CVCC and current-mode are
once again acceptable. The PG-ISFET is an alternative for
achieving trapped charge adaptation, although to avoid a
reduction in sensitivity, several phases of operation must be
considered which increases the complexity as well as the
silicon area.
3) Temperature Effect: We have demonstrated that temper-
ature was rarely tackled in ISFET sensing systems. As such,
on-chip temperature regulation appears to be the most efficient
scheme. In-pixel heaters and sensors can be used to embed
a temperature system as part of the ISFET array. It is of
course debatable whether this method can really be qualified
as system compensation, but the limitations of the athermal
point biasing or the temperature coefficient cancellation are too
important for the temperature-insensitivity requirements. For a
current mode readout in weak inversion operation, temperature
insensitivity of the current to the pH through periodic reset
might also be investigated.
MOSER et al.: ISFETs IN CMOS AND EMERGENT TRENDS IN INSTRUMENTATION
4) SNR: The main factor which influences the SNR of the
system is typically the front-end input-referred noise, and min-
imising this often comes down to minimising the uncorrelated
noise through averaging techniques. On the one hand, this
can be done spatially. Considering a current mode topology is
beneficial for the reader at this point, since current averaging
can be realised more effectively than voltage averaging, which
usually involves external signal processing. However, there is
a trade-off between spatial averaging and spatial resolution,
since computing over more pixels reduces the effective size of
the array. On the other hand, temporal averaging constitutes a
trade-off with the frame rate. It is typically not worth being
performed on-chip since it involves memory, and once again
external processing is a simple alternative. The preference
on either of the techniques is therefore dependent on the
requirements on spatial resolution and frame rate.
VII. T HE F UTURE OF ISFET R ESEARCH
We have now reviewed more than the last decade of the
research carried out in ISFET instrumentation. If the focus
of this review has been set on arrays, it is because the
authors strongly believe that they represent the future of ISFET
sensing. More and more arrays are currently being reported
in the literature, with an increasing number of pixels and
improved sensor density. However, the field has started to
look past building the biggest array and the smallest pixels,
instead dedicating more efforts to finding new topologies and
compensation schemes. It is expected that this will be carried
out over the next few years to ultimately come up with more
efficient and robust analogue front-end instrumentation.
In fact, the whole idea of a compact pixel is bound to
be revisited soon, since the ISFET chemical sensing area
should be made large enough to minimise both chemical
noise and capacitive scaling, enhancing SNR in the process.
This could be the opportunity to start introducing in-pixel
quantisation in the novel architectures, improving once again
the signal immunity against any sort of interference or noise.
For that reason, the authors are particularly keen on in-pixel
pH encoding in different domains than analogue, justifying
their work on time and spike domain processing. Additional
investigation might lead to a different perspective of the system
than analogue readout, paving the way to novel calibration
schemes specific to these types of signals.
More importantly, the recent tendency to turn towards
device adaptation as opposed to system compensation should
carry on for offset and drift. Additional circuitry could be
required to achieve adaptation at device level, and will be
implemented locally as part of the larger pixel. Once efficient
adaptation is achieved for these nonidealities, it is expected
that more strategies will be reported for factors such as
temperature stability, noise immunity or even light sensitivity.
Once again, these advances will be new requirements orig-
inating from new emerging applications for ISFET arrays.
We are indeed expecting that a functional ion sensing system
will not go unnoticed, and several applications will emerge
which will provide other purposes to the platforms than DNA
sequencing. If this indeed occurs, it is likely that the research
6511
will further split into branches with different requirements and
hence various structures of the arrays. On the other hand, it is
also possible that the field will come up with generic versions
of arrays which can easily be applied to a wide range of
applications, although such versatility will take more time and
effort to build.
Overall, the next generation of ISFET arrays should be
made scalable and reliable, with most of the functionalities
embedded on silicon. We are expecting a system which
performs initial calibration to cancel any unwanted effects,
and rectify any further issues during or between the measure-
ments. This way, data acquisition to the external controller is
straightforward and the user treats the SPI output to display
the array on a user-friendly interface.
We are closer to introducing such a system than most
researchers believe. In the next review of this kind, the
discussion will not tackle the various techniques implemented
for readout and compensation to put together a full system.
Instead, because each system will be closer to a finished
product, it will focus on the performance of each array in terms
of pH sensitivity, resolution, frame rate, density, parallelisation
and other criteria.
It is now up to the research groups to start orienting their
work towards the ultimate goal of the autonomous array, driven
by an application that they ought to identify out of all the
possibilities brought by a chemical sensing array.
VIII. C ONCLUSION
In this review, we have provided a general overview of
the state of the ISFET instrumentation research field, starting
with a general background on the sensor as a floating gate
transistor. We have emphasised that its integration in CMOS
technology has provided many advantages, including inherent
scalability, low power and low cost. Furthermore, we have
summarised the challenges related to common nonidealities of
the device i.e. trapped charge, drift, temperature instability and
noise corruption. We have stated that these deviations from the
ideal ISFET operation had only been thoroughly characterised
in the last decade, which has triggered an deep investigation
of compensation methods.
Classical readout topologies such as source and drain fol-
lower and differential measurements, already described by
Bergveld in his review [4], are still reported nowadays. How-
ever, their failure in conceiving a full sensing system has led
the new generation of researchers to innovate and develop
novel analogue front-end topologies. Each of them brings a
new concept, from embedded compensation to special encod-
ing of the signal. Despite these breakthroughs, several papers
still focus on stacking external schemes to existing readout,
although this involves a decreasing amount of publications, in
favour of more robust ISFET adaptation methods.
Using the technology and techniques accessible at the time
of writing, we have provided guidelines for the design of
an application-specific ISFET sensing array. These involve
identifying the requirements in details, and determining the
best topologies to match them. Additionally to the usual
analogue front-end, we have provided recommendations for
temperature compensation or improved pH resolution.
6512
In the last section, we have shared our predictions on
the evolution of the ISFET field in the years following this
review. In particular, we are expecting the research to focus
on the development of scalable and robust ISFET array for an
increasing amount of applications. This could come as soon
as in the next few years, and it is very likely that it will
trigger a race in system performance between all the reported
architectures.
When Bergveld reported the ISFET, he was aiming at
carrying out measurements where glass electrodes could not
be applied. 44 years later, it has become an essential device
in the field of CMOS sensing, with an evergrowing research
which will soon be integrating millions of these sensors for
massively parallel autonomous ion detection.
ACKNOWLEDGMENT
The authors would like to acknowledge the EPSRC Centre
for Doctoral Training in High Performance Embedded and
Distributed Systems (EP/L016796/1) for supporting this work.
R EFERENCES
[1] P. Bergveld, Development, operation, and application of the ion-
sensitive field-effect transistor as a tool for electrophysiology, IEEE
Trans. Biomed. Eng., vol. BME-19, no. 5, pp. 342351, Sep. 1972.
[2] P. Georgiou and C. Toumazou, ISFET characteristics in CMOS and
their application to weak inversion operation, Sens. Actuators B, Chem.,
vol. 143, no. 1, pp. 211217, 2009.
[3] E. C. Hayden, Technology: The $1,000 genome, Nature, vol. 507,
no. 7492, pp. 294295, 2014.
[4] P. Bergveld, Thirty years of ISFETOLOGY: What happened in the past
30 years and what may happen in the next 30 years, Sens. Actuators
B, Chem., vol. 88, no. 1, pp. 112, Jan. 2003.
[5] Y. Hu and P. Georgiou, A robust ISFET pH-measuring front-end for
chemical reaction monitoring, IEEE Trans. Biomed. Circuits Syst.,
vol. 8, no. 2, pp. 177185, Apr. 2014.
[6] J. Luk, J. Fridrich, and M. Goljan, Digital camera identification from
sensor pattern noise, IEEE Trans. Inf. Forensics Security, vol. 1, no. 2,
pp. 205214, Jun. 2006.
[7] L. Bousse, N. De Rooij, and P. Bergveld, Operation of chemi-
cally sensitive field-effect sensors as a function of the insulator-
electrolyte interface, IEEE Trans. Electron Devices, vol. 30, no. 10,
pp. 12631270, Oct. 1983.
[8] R. van Hal, J. Eijkel, and P. Bergveld, A novel description of ISFET
sensitivity with the buffer capacity and double-layer capacitance as
key parameters, Sens. Actuators B, Chem., vols. 2425, nos. 13,
pp. 201205, 1995.
[9] S. Martinoia and G. Massobrio, A behavioral macromodel of the ISFET
in SPICE, Sens. Actuators B, Chem., vol. 62, no. 3, pp. 182189, 2000.
[10] H.-S. Wong and M. H. White, A self-contained CMOS integrated pH
sensor, in Int. Electron Devices Meeting Tech. Dig. (IEDM), Dec. 1988,
pp. 658661.
[11] A. Sibbald, P. D. Whalley, and A. K. Covington, A miniature flow-
through cell with a four-function chemfet integrated circuit for simulta-
neous measurements of potassium, hydrogen, calcium and sodium ions,
Anal. Chim. Acta, vol. 159, pp. 4762, 1984.
[12] A. Bratov, N. Abramova, and C. Domnguez, Investigation of chloride
sensitive ISFETs with different membrane compositions suitable for
medical applications, Anal. Chim. Acta, vol. 514, pp. 99106, Jun. 2004.
[13] A. A. Shulga, A. C. Sandrovsky, V. I. Strikha, A. P. Soldatkin,
N. F. Starodub, and A. V. Elskaya, Overall characterization of ISFET-
based glucose biosensor, Sens. Actuators B, Chem., vol. 10, no. 1,
pp. 4146, 1992.
[14] W. Sant et al., Development of a creatinine-sensitive sensor for medical
analysis, Sens. Actuators B, Chem., vol. 103, nos. 12, pp. 260264,
2004.
[15] J. Bausells, J. Carrabina, A. Errachid, and A. Merlos, Ion-sensitive
field-effect transistors fabricated in a commercial CMOS technology,
Sens. Actuators B, Chem., vol. 57, nos. 13, pp. 5662, Sep. 1999.
IEEE SENSORS JOURNAL, VOL. 16, NO. 17, SEPTEMBER 1, 2016
[16] C. Toumazou, T. S. L. K. Thay, and P. Georgiou, A new era of
semiconductor genetics using ion-sensitive field-effect transistors: The
gene-sensitive integrated cell, Phil. Trans. Roy. Soc. A, Math. Phys.
Eng. Sci., vol. 372, p. 20130112, Feb. 2014.
[17] C. G. Jakobson, U. Dinnar, M. Feinsod, and Y. Nemirovsky, Ion-
sensitive field-effect transistors in standard CMOS fabricated by post
processing, IEEE Sensors J., vol. 2, no. 4, pp. 279287, Aug. 2002.
[18] J. M. Rothberg et al., An integrated semiconductor device enabling non-
optical genome sequencing, Nature, vol. 475, no. 7356, pp. 348352,
2011, doi: 10.1038/nature10242.
[19] M. J. Milgrew and D. R. S. Cumming, Matching the transconductance
characteristics of CMOS ISFET arrays by removing trapped charge,
IEEE Trans. Electron Devices, vol. 55, no. 4, pp. 10741079, Apr. 2008.
[20] S. Jamasb, S. Collins, and R. L. Smith, A physical model for drift in
pH ISFETs, Sens. Actuators B, Chem., vol. 49, nos. 12, pp. 146155,
1998.
[21] S. Jamasb, An analytical technique for counteracting drift in ion-
selective field effect transistors (ISFETs), IEEE Sensors J., vol. 4, no. 6,
pp. 795801, Dec. 2004.
[22] M. Sohbati and C. Toumazou, Dimension and shape effects on the
ISFE/T performance, IEEE Sensors J., vol. 15, no. 3, pp. 16701679,
Mar. 2015.
[23] Y.-L. Chin, J.-C. Chou, T.-P. Sun, W.-Y. Chung, and S.-K. Hsiung,
A novel pH sensitive ISFET with on chip temperature sensing using
CMOS standard process, Sens. Actuators B, Chem., vol. 76, nos. 13,
pp. 582593, 2001.
[24] M. Daniel, M. Janicki, and A. Napieralski, Simulation of ion sensitive
transistors using a SPICE compatible model, in Proc. IEEE Sensors,
vol. 1, Oct. 2003, pp. 543548.
[25] P. Barabash, R. Cobbold, and W. Wlodarski, Analysis of the thresh-
old voltage and its temperature dependence in electrolyte-insulator-
semiconductor field-effect transistors (EISFETs), IEEE Trans. Electron
Devices, vol. 34, no. 6, pp. 12711282, Jun. 1987.
[26] Y. Liu, P. Georgiou, T. Prodromakis, T. G. Constandinou, and
C. Toumazou, An extended CMOS ISFET model incorporating
the physical design geometry and the effects on performance and
offset variation, IEEE Trans. Electron Devices, vol. 58, no. 12,
pp. 44144422, Dec. 2011.
[27] N. Miscourides and P. Georgiou, Impact of technology scaling on
ISFET performance for genetic sequencing, IEEE Sensors J., vol. 15,
no. 4, pp. 22192226, Apr. 2015.
[28] L. M. Shepherd and C. Toumazou, A biochemical translinear principle
with weak inversion ISFETs, IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 52, no. 12, pp. 26142619, Dec. 2005.
[29] B. Nemeth, M. S. Piechocinski, and D. R. Cumming, High-resolution
real-time ion-camera system using a CMOS-based chemical sensor
array for proton imaging, Sens. Actuators B, Chem., vols. 171172,
pp. 747752, Aug./Sep. 2012.
[30] X. Huang, H. Yu, X. Liu, Y. Jiang, M. Yan, and D. Wu, A dual-mode
large-arrayed CMOS ISFET sensor for accurate and high-throughput pH
sensing in biomedical diagnosis, IEEE Trans. Biomed. Eng., vol. 62,
no. 9, pp. 22242233, Sep. 2015.
[31] Y. Liu, A. Al-Ahdal, P. Georgiou, and C. Toumazou, Minimal readout
scheme for ISFET sensing arrays based on pulse width modulation,
Electron. Lett., vol. 48, no. 10, pp. 548549, May 2012.
[32] N. Moser, T. S. Lande, and P. Georgiou, A novel pH-to-time ISFET
pixel architecture with offset compensation, in Proc. IEEE Int. Symp.
Circuits Syst. (ISCAS), May 2015, pp. 481484.
[33] B. Premanode, W. Chan, and C. Toumazou, Ultra-low power precision
ISFET readout using global current feedback, Electron. Lett., vol. 42,
no. 22, pp. 12641265, Oct. 2006.
[34] P. Pookaiyaudom, C. Toumazou, and F. Lidgey, The chemical current-
conveyor: A new microchip biosensor, in Proc. IEEE Int. Symp. Circuits
Syst. (ISCAS), May 2008, pp. 31663169.
[35] M. Futagawa, R. Otake, F. Dasai, M. Ishida, and K. Sawada, Realization
of 1 million pixel charge transfer type ion image sensor with 12 m pixel
pitch, in Proc. 18th Int. Conf. Solid-State Sens., Actuators Microsyst.
(TRANSDUCERS), Jun. 2015, pp. 236239.
[36] P. Georgiou and C. Toumazou, An adaptive ISFET chemical imager
chip, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2008,
pp. 20782081.
[37] A. Do, J. Minkyu, and K. Yeo, Improved inverter-based read-out
scheme for low-power ISFET sensing array, Electron. Lett., vol. 49,
no. 24, pp. 15171518, Nov. 2013.
[38] K. Wang, Y. Liu, C. Toumazou, and P. Georgiou, A TDC based
ISFET readout for large-scale chemical sensing systems, in Proc. IEEE
Biomed. Circuits Syst. Conf. (BioCAS), Nov. 2012, pp. 176179.
MOSER et al.: ISFETs IN CMOS AND EMERGENT TRENDS IN INSTRUMENTATION
[39] P. Georgiou and C. Toumazou, CMOS-based programmable gate
ISFET, Electron. Lett., vol. 44, no. 22, pp. 12891290, Oct. 2008.
[40] W. Wong, L. Shepherd, P. Georgiou, and C. Toumazou, Towards ISFET
based DNA logic for rapid nucleic acid detection, in Proc. IEEE
Sensors, Oct. 2009, pp. 14511454.
[41] A. Al-Ahdal and C. Toumazou, ISFET-based chemical switch, IEEE
Sensors J., vol. 12, no. 5, pp. 11401146, May 2012.
[42] A. Alahdal and C. Toumazou, ISFET-based chemical Schmitt trigger,
Electron. Lett., vol. 48, no. 10, pp. 549551, May 2012.
[43] H.-H. Wong and M. H. White, A CMOS-integrated ISFET-operational
amplifier chemical sensor employing differential sensing, IEEE Trans.
Electron Devices, vol. 36, no. 3, pp. 479487, Mar. 1989.
[44] L. Shepherd, P. Georgiou, and C. Toumazou, A novel voltage-clamped
CMOS ISFET sensor interface, in Proc. IEEE Int. Symp. Circuits
Syst. (ISCAS), May 2007, pp. 33313334.
[45] M. J. Milgrew, P. A. Hammond, and D. R. S. Cumming, The develop-
ment of scalable sensor arrays using standard CMOS technology, Sens.
Actuators B, Chem., vol. 103, nos. 12, pp. 3742, 2004.
[46] M. Kalofonou and C. Toumazou, A low power sub-w chemical Gilbert
cell for ISFET differential reaction monitoring, IEEE Trans. Biomed.
Circuits Syst., vol. 8, no. 4, pp. 565574, Aug. 2014.
[47] M. Sohbati, P. Georgiou, and C. Toumazou, REFET replication for
ISFET-based SNP detection arrays, in Proc. IEEE Int. Symp. Circuits
Syst. (ISCAS), May 2013, pp. 185188.
[48] D. M. Garner et al., A multichannel DNA SoC for rapid point-of-
care gene detection, in IEEE Int. Solid-State Circuits Conf. Dig. Tech.
Papers (ISSCC), Feb. 2010, pp. 492493.
[49] V. P. Chodavarapu, A. H. Titus, and A. N. Cartwright, Differential
read-out architecture for CMOS ISFET microsystems, Electron. Lett.,
vol. 41, no. 12, pp. 698699, Jun. 2005.
[50] G. Nabovati, E. Ghafarzadeh, F. Awwad, and M. Sawan, A sigma delta
ISFET readout circuit for Lab-on-Chip applications, in Proc. IEEE 11th
Int. New Circuits Syst. Conf. (NEWCAS), Jun. 2013, pp. 14.
[51] L. Yan, P. Georgiou, T. Constandinou, D. Garner, and C. Toumazou,
An auto-offset-removal circuit for chemical sensing based on the PG-
ISFET, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2009,
pp. 11651168.
[52] P. Georgiou and C. Toumazou, An adaptive CMOS-based PG-ISFET for
pH sensing, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2009,
pp. 557560.
[53] M. J. Milgrew, M. O. Riehle, and D. R. S. Cumming, A large
transistor-based sensor array chip for direct extracellular imaging, Sens.
Actuators B, Chem., vols. 111112, pp. 347353, Nov. 2005.
[54] M. J. Milgrew and D. R. S. Cumming, A proton camera array
technology for direct extracellular ion imaging, in Proc. IEEE Int.
Symp. Ind. Electron. (ISIE), Jun. 2008, pp. 20512055.
[55] K. Nakazato, An integrated ISFET sensor array, Sensors, vol. 9, no. 11,
pp. 88318851, Nov. 2009.
[56] M. M. Uzzal, P. Zarkesh-Ha, J. S. Edwards, E. Coelho, and P. Rawat,
A highly sensitive ISFET using pH-to-current conversion for real-time
DNA sequencing, in Proc. 27th IEEE Int. Syst.-Chip Conf. (SOCC),
Sep. 2014, pp. 410414.
[57] Y. Hu and P. Georgiou, 3-T ISFET front-end utilising parasitic device
capacitance, Electron. Lett., vol. 50, no. 21, pp. 15071509, Oct. 2014.
[58] W. Chan, B. Premanode, and C. Toumazou, 64 pH-ISFET averaging
array employing global negative current feedback, Electron. Lett.,
vol. 45, no. 11, pp. 536537, May 2009.
[59] M. Sohbati and C. Toumazou, A temperature insensitive continuous
time p H to digital converter, in Proc. IEEE Int. Symp. Circuits
Syst. (ISCAS), Jun. 2014, pp. 3740.
[60] X. Huang, F. Wang, J. Guo, M. Yan, Y. Hao, and K. S. Yeo, A 6464
1200 fps CMOS ion-image sensor with suppressed fixed-pattern-noise
for accurate high-throughput DNA sequencing, in Symp. VLSI Circuits
Dig. Tech. Papers, Jun. 2014, pp. 12.
[61] Y. Liu and C. Toumazou, An ISFET based sensing array with sensor
offset compensation and pH sensitivity enhancement, in Proc. IEEE
Int. Symp. Circuits Syst. (ISCAS), May 2010, pp. 22832286.
[62] T. G. Constandinou, P. Georgiou, T. Prodromakis, and C. Toumazou, A
CMOS-based lab-on-chip array for the combined magnetic stimulation
and opto-chemical sensing of neural tissue, in Proc. 12th Int. Workshop
Cellular Nanosc. Netw. Appl. (CNNA), Feb. 2010, pp. 16.
[63] A. Al-Ahdal, P. Georgiou, and C. Toumazou, ISFETs threshold voltage
control using bidirectional electron tunnelling, in Proc. IEEE Biomed.
Circuits Syst. Conf. (BioCAS), Nov. 2012, pp. 172175.
6513
[64] P. Georgiou and C. Toumazou, ISFET threshold voltage programming
in CMOS using hot-electron injection, Electron. Lett., vol. 45, no. 22,
pp. 11121113, Oct. 2009.
[65] A. G. Al-Ahdal and C. Toumazou, ISFET threshold voltage program-
ming in CMOS using electron tunnelling, Electron. Lett., vol. 47,
no. 25, pp. 13981399, Dec. 2011.
[66] Y. Yanagawa, N. Itabashi, S. Migitaka, T. Yokoi, M. Yoshida, and
T. Kawahara, On-chip base sequencing using a two-stage reaction-
control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-
based DNA sequencer, in Proc. IEEE Biomed. Circuits Syst.
Conf. (BioCAS), Oct. 2013, pp. 178181.
[67] Y. Hu, J. Li, and P. Georgiou, A SAR based calibration scheme for
ISFET sensing arrays, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS),
Jun. 2014, pp. 666669.
[68] D. Welch, S. Shah, S. Ozev, and J. B. Christen, Experimental and
simulated cycling of ISFET electric fields for drift reset, IEEE Electron
Device Lett., vol. 34, no. 3, pp. 456458, Mar. 2013.
[69] S. Shah and J. B. Christen, Pulse width modulation circuit for ISFET
drift reset, in Proc. IEEE SENSORS, Nov. 2013, pp. 14.
[70] C.-Y. Aw and P. W. Cheung, A pH-ISFET sensor with on-chip tem-
perature sensing, in Proc. Annu. Int. Conf. IEEE Eng. Med. Biol. Soc.,
vol. 2, Nov. 1988, pp. 772773.
[71] P. K. Chan and D. Y. Chen, A CMOS ISFET interface circuit with
dynamic current temperature compensation technique, IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 54, no. 1, pp. 119129, Jan. 2007.
[72] D. Y. Chen and P. K. Chan, An intelligent ISFET sensory system with
temperature and drift compensation for long-term monitoring, IEEE
Sensors J., vol. 8, no. 12, pp. 19481959, Dec. 2008.
[73] B. Premanode, N. Silawan, and C. Toumazou, Drift reduction in
ion-sensitive FETs using correlated double sampling, Electron. Lett.,
vol. 43, no. 16, pp. 857859, Aug. 2007.
[74] P. Shields, B. Nemeth, R. B. Green, M. O. Riehle, and D. Cumming,
High-speed imaging of 2-D ionic diffusion using a 16 16 pixel CMOS
ISFET array on the microfluidic scale, IEEE Sensors J., vol. 12, no. 9,
pp. 27442749, Sep. 2012.
[75] E. Guerrero, M. Sanz-Pascual, J. Molina-Reyes, N. Medrano, and
B. Calvo, A digitally programmable calibration circuit for smart sen-
sors, in Proc. IEEE 3rd Latin Amer. Symp. Circuits Syst. (LASCAS),
Feb. 2012, pp. 14.
[76] H. Zimouche, H. Amhazand, and G. Sicard, Temperature compensation
scheme for logarithmic CMOS image sensor, in Proc. Int. Image Sensor
Workshop (IISW), Jun. 2011, pp. 138141.
[77] E. Lauwers, J. Suls, W. Gumbrecht, D. Maes, G. Gielen, and W. Sansen,
A CMOS multiparameter biochemical microsensor with temperature
control and signal interfacing, IEEE J. Solid-State Circuits, vol. 36,
no. 12, pp. 20302038, Dec. 2001.
[78] C. Toumazou et al., Simultaneous DNA amplification and detection
using a pH-sensing semiconductor system, Nature Methods, vol. 10,
pp. 641646, Jun. 2013.
[79] W. K. Wong, Jr., P. Georgiou, C.-P. Ou, and C. Toumazou, PG-ISFET
based DNA-logic for reaction monitoring, Electron. Lett., vol. 46, no. 5,
pp. 330332, Mar. 2010.
[80] C. Z. D. Goh, P. Georgiou, T. G. Constandinou, T. Prodromakis, and
C. Toumazou, A CMOS-based ISFET chemical imager with auto-
calibration capability, IEEE Sensors J., vol. 11, no. 12, pp. 32533260,
Dec. 2011.
[81] A. Manickam, R. Singh, N. Wood, B. Li, A. Ellington, and A. Hassibi,
A fully-electronic charge-based DNA sequencing CMOS biochip, in
Proc. Symp. VLSI Circuits (VLSIC), Jun. 2012, pp. 126127.
[82] M. P. Das and M. Bhuyan, New ISFET interface circuits with noise
reduction capability, in Proc. Recent Adv. Innov. Eng. (ICRAIE),
May 2014, pp. 16.
[83] J. R. Epstein, I. Biran, and D. R. Walt, Fluorescence-based nucleic acid
detection and microarrays, Anal. Chim. Acta, vol. 469, no. 1, pp. 336,
2002.
[84] M. Schienle et al., A fully electronic DNA sensor with 128 positions
and in-pixel A/D conversion, IEEE J. Solid-State Circuits, vol. 39,
no. 12, pp. 24382445, Dec. 2004.
[85] D. M. Joh, A defining decade in DNA sequencing, Nature Methods,
vol. 11, no. 10, pp. 10031005, 2014.
[86] M. Kalofonou and C. Toumazou, Semiconductor technology for
early detection of DNA methylation for cancer: From concept
to practice, Sens. Actuators B, Chem., vol. 178, pp. 572580,
Mar. 2013.
6514
Nicolas Moser (S15) received the B.Sc. degree in
electronic and chemical engineering from the Uni-
versit Catholique de Louvain, Louvain-la-Neuve,
Belgium, in 2013, the M.Sc. degree in analogue and
digital integrated circuit design from the Department
of Electrical and Electronic Engineering, Imperial
College London, London, U.K., in 2014, and the
M.Res. degree in advanced computing from Imperial
College London, London, in 2015.
He is currently pursuing the Ph.D. degree with
the High Performance Embedded and Distributed
Systems EPSRC, Centre for Doctoral Training, with in the Centre for
Bio-Inspired Technology, Department of Electrical and Electronic Engineer-
ing, Imperial College London. He received the Hertha Ayrton Prize 2015 for
the best M.Sc. project with significant original contribution to the topic area
and the Outstanding Achievement prize for the analogue and digital integrated
circuit design M.Sc. His research interests include the design of mixed-signal
integrated circuits for Lab-on-Chip applications, with a specific focus on ion
imaging using ISFET arrays.
Tor Sverre Lande (M93SM06F10) is currently
a Professor of nanoelectronics with the Department
of Informatics, University of Oslo. He is a Visiting
Professor with the Institute of Biomedical Engi-
neering, Imperial College, London, U.K. He has
authored or co-authored over 100 scientific publi-
cations with chapters in two books. His primary
research is related to analogue and digital microelec-
tronics. Research fields are neuromorphic engineer-
ing, analogue signal processing, micropower circuit
and system design, biomedical circuits and systems
and impulse radio (IR-UWB) for wireless and radar. He is serving as an
Associate Editor of several scientific journals.
He has served as Guest Editor of special issues for the IEEE T RANS -
ACTIONS ON C IRCUITS AND S YSTEMS I AND II, and a Special Issue on
Biomedical Circuits and Systems. In 2006, he was appointed Distinguished
Lecturer of the IEEE Circuits and Systems Society and an elected member
of CAS Board of Governors. He was the Editor-in-Chief of the IEEE
T RANSACTIONS ON B IOMEDICAL C IRCUITS AND S YSTEMS from 2007 to
2010. He is also the Co-Founder of the spin-off company Novelda AS.
IEEE SENSORS JOURNAL, VOL. 16, NO. 17, SEPTEMBER 1, 2016
Christofer Toumazou (M87SM99F01) is cur-
rently the Founding Director and a Chief Scien-
tist with the Institute of Biomedical Engineering,
Impe rial College London, London, U.K., where
he is also the Research Director of the Centre for
Bio-Inspired Technology and the Winston Wong
Chair of Bio-medical Circuits with the Department
of Electrical and Electronic Engineering. He has
authored over 700 research papers and holds over
40 patents in the field of semiconductors and health-
care many of which are currently fully granted
PCT. He is distinguished for his groundbreaking innovations in silicon
technology and integrated circuit design. His career began with the invention
and development of the entirely novel concept of current-mode analog
circuitry for ultralow-power electronic devices. For this, he became one of
the youngest ever Professors at Imperial College London. However, it has
been his success in applying silicon chip technology to biomedical and life-
science applications, most recently to DNA analysis, that is leading to new
innovations in the field of genetics, molecular biology, and personalized
medicine. He is the Founder of three technology-based companies with
applications spanning ultralow-power mobile technology (Toumaz Technology
Ltd., U.K.), DNA sequencing (DNA Electronics Ltd., U.K.), and GeneOnyx, a
company applying the DNAe technology to retail cosmetics. He has received
many awards, including the Royal Society Clifford Patterson Prize Lecture,
entitled The Bionic Man, for which he received the Royal Society Clifford
Patterson Bronze Medal in 2003. He was a recipient of the 2005 IEEE
CAS Education Award for pioneering contributions in circuits and systems
for biomedical applications, and the Royal Academy of Engineering Silver
Medal in 2007 for pioneering contributions to the British industry. In 2008,
he was appointed as a Fellow of the Royal Academy of Engineering and
the Royal Society. He was a recipient of the World Technology Award from
Time Magazine for the Health and Medicine category in 2009, and the 2011
J. J. Thompson Medal of the Institution of Engineering and Technology (IET).
In 2013, he was a Fellow of the Academy of Medical Sciences and was
conferred the title of Regius Professor in the Queens 2012 Diamond Jubilee.
He was also a recipient of the European Inventor Award from the European
Patent Office and the Michael Faraday Award from the IET in 2014.
Pantelis Georgiou (AM05M08SM13) received
the M.Eng. degree in electrical and electronic engi-
neering and the Ph.D. degree from Imperial College
London (ICL), London, U.K., in 2004 and 2008,
respectively.
He is currently a Senior Lecturer with the
Department of Electrical and Electronic Engineer-
ing, ICL, where he is also the Head of the Bio-
Inspired Metabolic Technology Laboratory, Centre
for Bio-Inspired Technology. His research includes
bio-inspired circuits and systems, CMOS based
Lab-on-Chip technologies, and application of microelectronic technology to
create novel medical devices. He conducted pioneering work on the integration
of ISFET sensors in CMOS, which has enabled applications, such as point of
care diagnostics and semiconductor genetic sequencing and has also developed
the first bio-inspired artificial pancreas for treatment of Type I diabetes using
the silicon-beta cell. He received the IET Mike Sergeant Medal of Outstanding
Contribution to Engineering in 2013. He is a member of the IET and serves
on the BioCAS and Sensory Systems technical committees of the IEEE CAS
Society. He also serves on the IET Prizes and Awards committee.