SSB UPCONVERSION OF QUADRATURE DDS SIGNALS TO THE 800-TO-2500-MHz BAND (page 46)
Fundamentals of DSP-Based Control for AC Machines (page 3)
Transducer/Sensor Excitation and Measurement Techniques (page 33)
Complete contents on page 1
a
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About Analog Dialogue
Analog Dialogue is the free technical magazine of Analog Devices, Inc., published continuously
for thirty-four years, starting in 1967. It discusses products, applications, technology, and
techniques for analog, digital, and mixed-signal processing.
Volume 34, the current issue, incorporates all articles published during 2000 in the
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Welcome! Read and enjoy!
We encourage your feedback*!
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dan.sheingold@analog.com
Editor, Analog Dialogue
*Weve included a brief questionnaire in this issue (page 55); wed be most grateful if youd answer the
questions and fax it back to us at 781-329-1241.
Page
Editors Notes: New Fellow, Authors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Feedback Questionnaire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Cover: The cover illustration was designed and executed by Kristine Chmiel-Lafleur, of Communications Services, Analog Devices, Inc.
Editors Notes design. Once he met Professor Tim Trick, who was active in the
field of computer-aided design of circuits, Daves career direction
We are pleased to note the introduc-
was set. After receiving BS and MS degrees from the University of
tion of Dr. David Smart as new
Illinois, he worked on circuit simulation at GTE Communication
Fellow at our 2000 General Techni-
Systems for seven years. He returned to the University of Illinois,
cal Conference. Fellow, at Analog
researching parallel algorithms for circuit simulation with Professor
Devices, represents the highest level
Trick, and he obtained his PhD degree prior to joining ADI in 1988.
of achievement that a technical
contributor can achieve, on a par THE AUTHORS
with Vice President. The criteria Rick Blessington (page 7) rejoined
for promotion to Fellow are very ADI as a Business Development
demanding. Fellows will have Manager in April of 1999, after 15
earned universal respect and recognition from the technical com- years in the sales and marketing of
munity for unusual talent and identifiable innovation at the state communication products for major
of the art. Their creative technical contributions in product or electronics companies. At present,
process technology will have led to commercial success with a he is involved in development of
major impact on the companys net revenues. inventive new products under a
Attributes include roles as mentor, consultant, entrepreneur, contract collaboration between
organizational bridge, teacher, and ambassador. Fellows must also Sierra Telecom (So. Lake Tahoe) and
be effective leaders and members of teams and in perceiving Analog Devices. Rick holds BA and MA degrees in Technology
customer needs. Daves technical abilities, accomplishments, and from California State University at Long Beach. In the early years
personal qualities well qualify him to join Bob Adams (1999), of his career, Rick taught electronics in Southern California. He
Woody Beckford (1997), Derek Bowers (1991), Paul Brokaw and his family now live in Walpole, MA; his hobbies include sailing
(1979), Lew Counts (1983), Barrie Gilbert (1979), Roy Gosser and skiing.
(1998), Bill Hunt (1998), Jody Lapham (1988), Chris Mangelsdorf Kevin Buckley (page 40) is a Senior
(1998), Fred Mapplebeck (1989), Jack Memishian (1980), Doug Applications Engineer in the High-
Mercer (1995), Frank Murden (1999), Mohammad Nasser (1993), Speed Converter Division, in
Wyn Palmer (1991), Carl Roberts (1992), Paul Ruggerio (1994), Wilmington, MA, working on analog
Brad Scharf (1993), Jake Steigerwald (1999), Mike Timko (1982), front ends for imaging applications.
Bob Tsang (1988), Mike Tuthill (1988), Jim Wilson (1993), and He joined Analog Devices in 1990 as
Scott Wurcer (1996) as Fellow. a technician for the Microelectronics
Division and received a BSEE in
NEW FELLOW
1997 from Merrimack College,
Dave Smart is the chief technolo-
North Andover, MA. In his spare
gist behind ADICE, our highly
time he plays hockey and soccer, coaches his sons soccer team, and
successful analog and mixed-signal
enjoys chasing his baby daughter around the house.
circuit simulator, which is widely
used by chip designers in Analog Paschal Minogue (page 10) is the
Devices. Dave joined ADI in 1988, Engineering Manager of the Digital
assuming responsibility for ADICE. Audio Group in Limerick, Ireland.
He made numerous contributions to He graduated from University
the robustness, accuracy, and features College Dublin, with a B.E.
of the simulator, winning the praise Electronic Engineering degree (First
of Analog Devices demanding analog IC designers. To meet the Class Honors) and joined the
challenges of designing large mixed-signal chips in the 1990s, Dave Design Department at Analog
led a small team in the development and deployment of a com- Devices in Limerick, Ireland, in
pletely new version of ADICE with innovative techniques for the 1981. Since then, he has worked on
effective simulation of mixed-signal circuits using mixed levels of standard converters, noise cancellation, communication products,
modeling abstraction. He is currently working on tools and meth- and most recently audio-band and voice-band products.
ods for the design of RF and high-speed ICs. The work of Dave and Reza Moghimi (page 28) is an
his team has been a key element of the design of nearly every ana- Applications Engineer for the
log and mixed-signal product developed by Analog Devices in the Precision Amplifier product line in
past decade. Santa Clara, CA. He is responsible
Dave developed an interest in analog circuits as a teenager growing for amplifiers, comparators,
up in Skokie, Illinois. Before receiving any formal education in temperature sensors, and the SSM
electronics, he and a friend designed and built an audio mixing audio product line. He holds a BS
board for their high school auditorium to be used in theatrical from San Jose State University and
productions.While pursuing his study of circuits as an undergraduate an MBA from National University
at the University of Illinois at Urbana-Champaign in the early 1970s, (Sunnyvale, CA). His leisure
he became aware of the power of digital computers and imagined interests include playing soccer and
their use to take some of the tedium and guesswork out of circuit traveling with his family. [more authors on Page 53]
PID
I*QS
+ PARK SVM
NON- FWM
VOLTAGE je GENERATION PWM
DECOUPLING e IDEALITY OUTPUTS
CORRECTION UNIT
PID
I*DS
3>2 MOTOR
ADC
TRANSFORM CURRENT
je SYSTEM
e FEEDBACK
PARK
ROTOR
POSITION, e ENCODER ENCODER
d
INTERFACE FEEDBACK
dt UNIT SIGNALS
DSP SOFTWARE
MOTOR CONTROL
PERIPHERALS
INTERFACE RESOLVER-TO-DIGITAL
R5-232, R5-485 CONVERTER
SPEED/DIRECTION/POSITION
COMMAND BUFFER
COMPUTER
HOST OSCILLATOR
NOTE:
SELECT THE BLUE SIGNAL CHAINSM BLOCKS OR THE
BLUE TEXT TO SEE A LISTING OF AVAILABLE PRODUCTS.
to Communicate with arrangement), and modem code. They may or may not include a
controller, Internet protocol stack, and SDRAM. The number of
chips depends on the application requirements, including the need
Distant Hosts via the for any additional functions. They connect to telephone lines, and
include all the necessary hardware and software.
Internet A data pump includes a processor (DSP) that translates data to a
standard protocol (fax or Internet), at a specific bit rate, such as
by Rick Blessington V.32, V.34, V.90, employing modem code. A DAA provides the
Software & Systems Technology Division* physical and software interface to a POTS (plain old telephone
service) line. A silicon DAA performs this function without external
INTRODUCTION codecs, relays, optocouplers, and transformers. An Internet protocol
Todays smart appliances do much more than shut off the dryer (IP) stack implements the Internet protocols (such as PPP, TCP,
when the clothes are dry or display a new photograph when one HTTP, POP3, FTP, etc.) on the modems DSP. This permits file
has been shot. For example: they provide status information downloads, standard Web-page hosting, and email capability for
indicating when a vending machine needs to be filled or a drop the device to which the modem is connected without the use of a PC,
box emptied; they run remote diagnostics when needed, and microcontroller, or other processor. Thus the DSP executes both the
automatically upgrade their settings and download software modem code and the IP stack.
upgrades to stay current; they schedule and request maintenance
Modem Architecture Trade-Offs
to avoid malfunctions; they add intelligence to the appliances that
Embedded modems may be either controller-based (parallel) or
harbor them.
operate without a controller. In both cases they need a fixed-point
Any equipment that does not require an embedded PC, but relies DSP data pump and DAA. The modem code can either run on
on data or fax to communicate with a remote host, is likely to the DSP data pump, or on a Pentium or RISC processor (for
require an embedded modem. Internet appliances designed solely host-based or software modems), or on a multifunction
to provide information via email or the Web need embedded programmable DSP (such as an ADSP-218x). For comparison,
modems to provide the communications link to the Internet. Set- modem architectures may be divided into two host-based classes
top boxes for interactive cable and satellite television require (with and without on-board processing), and two standalone classes
embedded modems to communicate billing information, (microcontroller- and DSP-based). Their characteristics and
interactive programming, pay-per-view, and home shopping orders. advantages/disadvantages are compared in Table I.
Appliances and handheld computers (or PDAs) become much
The controller-based designs work without hosts, so they dont care
more useful when they can link to remote hosts.
about operating systems or whether the host has crashed. This
The Handspring Visor, for example, can maintain schedules and standalone approach assures greater redundancy, since the modem
calendars, contact lists and telephone directories, expense logs and operates independently of the host computer and its operating
time sheets, stock portfolios, and sports team statistics. To be system. Their downside is they need a microcontroller and its
completely useful, however, the information must be both current memory, as well as DSP memory, to run the supervisory code.
and identical to the information in the users computer, company This entails additional parts count, real estate and power, and
database, and administrative assistants office tools and paper files. consequently added cost and risk. Also, their modem software is
With its Springboard modem, from card access, which uses an usually hard-coded and consequently not upgradeable.
Analog Devices embedded modem chipset, the Visor can be
connected to a telephone line and automatically update both itself
and its users host computer. In this way, the Visor becomes the MICRO- TELCO
DTE DATA PUMP DAA
accurate, timely, and functional information appliance its users CONTROLLER
need. Its embedded modem makes all of these capabilities possible
by linking it to a remote host without loading the PDA, because of
the Analog Devices DSP used in the embedded modem.
MEMORY SRAM
The Visor required its modem to have low power, small size, high
reliability, standalone form factor, and ease of Internet interfacing.
SUPERVISORY MODULATION
The resulting Springboard modem fits entirely inside the Visor CODE CODE
Controllerless (software-controlled, or win-) modems, offer lower cost, and cost-per-MIPS for a Pentium is much higher than for a DSP-
real estate, and power since the memory resides on the PC and no based design, so the power used by the board must be taken into
microcontroller (nor memory for it) is needed. However, they account, even if the cost is not. The cost of modem IP must still be
require a PC to run the supervisory code, so these winmodems paid, so the concept of free is not accurate.
are heavily dependent on the PC operating system. Consequently, A multifunction DSP-based embedded modem incorporates a
uptime of the PC host is important to their operation, and they programmable DSP, such as an ADSP-218x. By integrating the
are affected by the typical PC install/support issues. Their controller, memory, and data pump on a single chip, real estate
performance suffers when the host is heavily loaded with other (board space), cost, and power are reduced. No separate
jobs. They still require a data pump with memory. Code upgrades microcontroller or associated memory is required. A software-based
and diagnostics are dependent on the reliability of the PC host, UART is used, further reducing the hardware cost, real estate,
with no redundancy. Software upgrades are limited by the modems and power. The standalone design operates independently of the
fixed amount of memory. host and operating system, offering redundancy and remote
software upgradeability via the included FLASH memory. The
codec adds international capabilities, accommodating country-
TELCO
PERSONAL
DATA PUMP DAA specific parameters. Three modulation speeds are possible, each
COMPUTER
using the same components but a different Internet protocol (IP):
up to 14.4 kbps, up to 33.6 kbps and up to 56 kbps.
DRAM
The Analog Devices programmable DSP-based embedded
SRAM modems capture the advantages of all the above approaches with
few of their disadvantages. Even as PC prices fall while host PC
performance increases, embedded DSP MIPS will always remain
SUPERVISORY MODULATION ISOLATION
less expensive, more reliable, and independent of host processing.
Figure 2. Controllerless modem (ISA and PCI).
RS232/TTL
ADDST DIGITAL LINE
Software, host-based or soft-modems operate without a DSP or SERIAL OR
IDMA 218x ISOLATION SIDE
RJ11
TELCO
microcontroller, since their supervisory and data pump code runs PARALLEL
PROGRAM DATA
SIDE
on the PC host.This approach has been promoted by PC processor SRAM SRAM SILICON DAA
ISOLATION
TOP VIEW
ONLY
DSP
1 INCH!
RS-232
TRANSCEIVER
when the server is located near the user. Usually, greater server
computing power means higher power dissipation, calling for
bigger/faster fans, which produce louder fan noise. With effective REFERENCE ANTINOISE
ERROR
fan noise cancellation, bigger cooling fans could be used, permitting +
MICROPHONE SPEAKER
MICROPHONE
FIXED
more power dissipation and a greater concentration of computer FIR
(FEEDBACK)
power in a given area.
PROGRAMMABLE
DESCRIPTION OF PROBLEM FIR
(FEEDFORWARD)
Typically, server cooling-fan noise has both a random and a
repetitive component. A spectrum plot of the fan noise of the Dell LMS
Poweredge 2200 server illustrates this (Figure 1). Also, the prole UPDATE
ALGORITHM
of the fan noise can change with time and conditions; for example,
an obstruction close to the fan will affect its speed and thus the Figure 2. Basic duct ANC system.
noise that it generates.
0
THE IMPORTANCE OF GROUP DELAY
To provide an unobtrusive and viable solution in terms of size and
cost, the smaller the duct is made the better; ideally, it should t
inside the server boxwhich would result in a very short acoustic
AMPLITUDE dB
ff ap (1)
imaging lter; and nally the delay through the secondary speaker.
e = mic + adc + dsp + dac + spkr (3)
REFERENCE ANTINOISE
Therefore, from causality: MICROPHONE SPEAKER ERROR
MICROPHONE
mic + adc + dsp + dac + spkr + as ap (4) ADC
DAC ADC
DEC
INT DEC
To minimize ap, and thereby the length of the duct, ff (and all its + FIXED
various components) should be made as small as possible. Lets FIR
(FEEDBACK)
assume that delays through the microphone, speaker and secondary
duct path have already been minimized. Then, the remaining PROGRAMMABLE
quantity to be minimized is adc + dsp + dac. FIR
(FEEDFORWARD)
POWER-DOWN
CONTROL
MEMORY
DATA ADDRESS
ADC1 GENERATORS PROGRAMMABLE
PROGRAM 18K PM 18K DM I/O
SEQUENCER (OPTIONAL 8K) (OPTIONAL 8K) AND FLAGS
DAG 1 DAG 2 FULL MEMORY
REF
MODE
EXTERNAL
PROGRAM MEMORY ADDRESS ADDRESS
DAC1
BUS
DATA MEMORY ADDRESS
SERIAL EXTERNAL
PORT DATA
PROGRAM MEMORY DATA BUS
SIGMA-DELTA ADC AND DAC ARCHITECTURE avoid this inherent group delay at the expense of reduced out-
The conversion technique adopted in the AFE is of the sigma- of-band rejection.
delta type. An analog sigma-delta modulator is used in the ADC The z-transform of both the sinc-cubed decimator and interpolator
channel and a digital sigma-delta modulator is employed in the is given by:
DAC channel. A sigma-delta modulator is a heavily oversampled
system that uses a low-resolution converter in a noise-shaping loop. 3
1 z M
The quantization noise of the low-resolution, high-speed converter 1 (8)
is inherently high-pass filtered and shaped out of band. The 1 z
output of the modulator or noise shaper is then low-pass filtered
to reduce the sample rate and remove the out-of-band noise. The group delay through the analog section of the DAC is
approximately 22.7 s.
The AFE conversion channels used in the AD73522 are shown in
Figure 6. The ADC section consists of an analog second-order, Notice that with sample rates of only 8 ksps the inherent group
32 to 256 oversampling, 1-bit sigma-delta modulator, followed delays through both the decimator and interpolator increase to
by a digital sinc-cubed decimator (divide-by-32 to divide-by-256). 186.8 s. Therefore, it is very important to run the converters at
The DAC section contains a digital sinc-cubed interpolator, a as high a rate as possible to reduce the inherent group delay.
digital, second-order, 32 to 256 oversampling, 1-bit sigma-delta The AFE features high-speed analog and digital feedforward paths
modulator, followed by an analog third-order switched-capacitor from ADC input to DAC output via the AGT and DGT
LPF and a second-order continuous-time LPF. respectively. The AGT is configured as a differential amplifier with
The group delay through the ADC channel is dominated by the gain programmable from 1 to +1 in 32 steps and a separate mute
group delay through the sinc-cubed decimator and is given by the control. The gain increment per step is 0.0625. The group delay
following relationship: through the AGT feedforward path is only 0.5 s. The DGT is a
programmable gain block whose input is tapped off from the bit-
M 1 stream output of the ADCs analog sigma-delta modulator. This
dec = Order ds (6) single-bit input is used to add or subtract the digital gain tap setting,
2
a 16-bit programmable value, to the output of the DACs
where Order is the order of the decimator (= 3), M is the decimation interpolator. The group delay through the DGT feedforward path
factor (= 32 for 64-ksps output sample rate) and ds is the is only 25 s.
decimation sample interval (= 1/2.048E6 s)
The loading of the DAC is normally internally synchronized with
32 1 1 the unloading of the ADC data in each sampling interval. However,
dec = 3 (7) this DAC load position can be advanced in time by up to 15 s in
2 2.048E 6
0.5-s steps. This facility can be used to further minimize the
dec = 22.7 s feedforward delay from analog input to analog output via the DSP.
for a 64-ksps output sample rate. AD73522 PACKAGING
The group delay through the DAC channel is primarily determined The three main processing elements (AFE, DSP and Flash
by the group delay through the sinc-cubed interpolator and the memory) are combined in a single package to give a cost-effective,
group delay through the third-order switched-capacitor LPF. The self-contained solution. This single package is a 119-ball plastic
inherent group delay through the interpolator is identical to that ball grid array (PBGA), as shown in Figure 7. It measures 14 mm
through the decimator and equals 22.7 s for 64-ksps input sample 22 mm 2.1 mm, and the solder balls are arranged in a 7 17
rate. However, the interpolator can be optionally bypassed to array with a 1.27-mm (50 mil) pitch.
22 mm
a.
BOTTOM VIEW
EXPERIMENTAL SETUP
7 ROWS 17 COLUMNS OF SOLDER BALLS The experimental setup (Figure 10) consists of a server box
b. (containing just a fan and power supply), a plastic duct (with
Figure 7. AD73522 plastic ball grid array (PBGA) packaging. reference and error microphones and secondary loudspeaker), and
the AD73522 evaluation board. The server fan was 5 inches (about
AD73522 EVALUATION BOARD 13 cm) in diameter. The T-shaped duct and the speaker measured
The AD73522 dspConverter evaluation board (Figures 8 and 9) 6 inches (about 15) cm in diameter. The duct length was adjustable
combines all of the front-end analog signal conditioning with a down to a minimum of 12 inches (30.5 cm).
SWITCHES
512k 8 EZ-ICE J1
FLASH
AVCC
PF4
3.2V
J7 8
CH1 CH2 CH1 CH2 POWER SPEAKER
AMP OUT
J9
MIC
INPUT OUTPUT J5 OUTPUT
INPUT J8 CONDITIONING CONDITIONING (1)
(1) CIRCUITRY CIRCUITRY
INPUT J4 J6 OUTPUT
(2) (2)
dspCONVERTER EVALUATION BOARD
AMPLITUDE dB
to allow testing with programmable tones and broadband signals.
ANC
60
0.2 0.6
FREQUENCY kHz
CONCLUSIONS
An approach combining an analog gain tap (AGT) and digital
gain tap (DGT) allows the use of sigma-delta techniques in low-
Figure 10. Server fan experimental setup. group-delay ANC applications. A single-package embodiment
combining analog and digital functions, like the AD73522
RESULTS dspConverter, should provide an ANC solution that is both flexible
The performance of the experimental setup with a single-tone and cost-effective.
disturbance from the primary speaker is shown in Figure 11. The
main tone is reduced by a factor of 30 dB. When the primary
speaker delivers a broadband disturbance, the reduction factor is
about 20 dB, as illustrated in Figure 12. ACKNOWLEDGEMENTS
Dell Computer, Limerick, Ireland, for the Poweredge 2200 server
0
box used in the experimental setup.
NO ANC Cork Institute of Technology, Cork, Ireland, for the duct
construction used in the experimental setup and a kick-start in
the code development.
AMPLITUDE dB
ANC REFERENCES
1. S.M. Kuo & D.R. Morgan, Active Noise Control Systems:
80
0
FREQUENCY kHz
1 Algorithms and DSP Implementations (Wiley, New York, 1996)
a. 136-Hz performance, with and without ANC. 2. A Primer on Active Sound and Vibration Control, L.J.
Eriksson, Digisonix brochure
0
3. Application of Active Noise Control for Small-Sized Electronic
Equipments, T. Hoshino, K. Fujii, T. Ohashi, A. Yamaguchi,
H. Furuya, J. Ohga, Inter-noise 94, 1409-1412 (1994)
NO ANC
AMPLITUDE dB
35 35
*ACPI DEFAULT CONTROL METHODS
30 30 ADJUST TEMPERATURE LIMIT VALUES
25 25
20 20 Figure 3. Tracking temperature changes by moving limits and
15 15 generating interrupts.
10 10
5 POLICY 5 POLICY The intelligent platform management interface (IPMI) specification
SCI EVENT SCI EVENT (Ref. 3) brings similar thermal management features to servers.
IPMI is aimed at reducing the total cost of ownership (TCO) of a
server by monitoring the critical heartbeat parameters of the
system: temperature, voltages, fan speeds, and PSUs (power-supply
1 2 units). Another motivation for IPMI is the need for interoperability
Figure 1. Performance preferred. Active mode (_ACx, fan on) between servers, to facilitate communication between baseboards
is entered at 50, passive mode (_PSV, throttle back) is en- and chassis. IPMI is based on the use of a 5-V I2C bus, with
tered at 60. Shutdown occurs at the critical temperature messages sent in packet form. Further information on IPMI is
(_CRT) 90. Fan speed may increase at levels above ACx. available from the Intel website at <http://developer.intel.com/
Figure 2. Silence and battery economy preferred. Passive mode design/servers/ipmi/>
is first entered at 45, and fan is not turned on until 60. All members of the Analog Devices Temperature and Systems-
Figures 1 and 2 are examples of temperature scales that illustrate Monitoring (TSM) family are ACPI- and IPMI-compliant.
the respective trade-offs between performance, fan acoustic noise,
and power consumption/dissipation. In order for a system- TEMPERATURE MONITORING
management device to be ACPI-compliant, it should be capable The prerequisite for intelligent fan-speed control within PCs is the
of signaling limit crossings at, say, 5C intervals, or SCI (system- ability to measure both system and processor temperature
control interrupt) events, that a new out-of-limit temperature accurately. The temperature monitoring technique used has been
increment has occurred. These events provide a mechanism by the subject of many articles (for example, see Analog Dialogue 33-4)
which the OS can track the system temperature and make informed and will only be briefly visited here. All Analog Devices system-
decisions as to whether to throttle the CPU clock, increase/decrease monitoring devices use a temperature monitoring technique known
the speed of the cooling fan, or take more drastic action. Once the as thermal diode monitoring (TDM). The technique makes use of
temperature exceeds the _CRT (critical temperature) policy setting, the fact that the forward voltage of a diode-connected transistor,
the system will be shut down as a fail-safe to protect the CPU. The operated at a constant current, exhibits a negative temperature
other two policy settings shown in Figures 1 and 2 are _PSV coefficient, about 2 mV/C. Since the absolute value of VBE
(passive cooling, or CPU clock throttling) and _ACx (active varies from device to device, this feature by itself is unsuitable
cooling, when the fan switches on). for use in mass-produced devices because each one would require
In Figure 1 (performance mode), the cooling fan is switched on at individual calibration. In the TDM technique, two different
50C. Should the temperature continue to rise beyond 60C, clock currents are successively passed through the transistor, and the
throttling is initiated. This behavior will maximize system voltage change is measured. The temperature is related to the
performance, since the system is only being slowed down at a higher difference in VBE by:
temperature. In Figure 2 (silent mode), the CPU clock is first
throttled at 45C. If the temperature continues to rise, a cooling VBE = kT/q ln(N)
fan may be switched on at 60C. This reduced-performance mode
will also tend to increase battery life, since throttling back the where: k = Boltzmanns constant
clock reduces power consumption.
q = electron charge magnitude
Figure 3 shows how the limits of the temperature measurement
bands track the temperature measurement. Each limit crossing T = absolute temperature in kelvins
produces an interrupt. N = ratio of the two currents
ADM1031
FAN SPEED R2
R1 39k
TACH/AIN1 10k
HYSTERESIS
MIN 7A 7B
SPEED
Figures 7A and 7B. PWM drive circuit compared with a linear
drive circuit.
TMIN TMAX
How is the fan speed measured? A 3-wire fan has a tach output
TEMPERATURE
that usually outputs 1, 2, or 4 tach pulses per revolution, depending
on the fan model. This digital tach signal is then directly applied to
Figure 6. Fan speed programmed as an automatic function of the tach input on the systems-monitoring device. The tach pulses
temperature. are not countedbecause a fan runs relatively slowly, and it would
take an appreciable amount of time to accumulate a large number
PWM vs. LINEAR FAN-SPEED CONTROL of tach pulses for a reliable fan speed measurement. Instead, the
One might ask why pulsewidth modulation is desirable if linear tach pulses are used to gate an on-chip oscillator running at
fan-speed control is already in widespread use. 22.5 kHz through to a counter (see Figure 8). In effect, the tach
Consider a 12-V fan being driven using linear fan-speed control. period is being measured to determine fan speed. A high count in
As the voltage applied to the fan is slowly increased from 0 V to the tach value register indicates a fan running at low speed (and
about 8 V, the fan will start to spin. As the voltage to the fan is vice versa). A limit register is used to detect sticking or stalled fans.
ADD
NC SLAVE
SERIAL BUS
ADM1030 ADDRESS
INTERFACE
SDA
REGISTER
SCL
NC
FAN
ADDRESS POINTER
CHARACTERISTICS NC
REGISTER
REGISTER
INTERRUPT
PWM FAN SPEED
PWM_OUT MASK INT/NTO
CONTROLLER CONFIG REGISTER
REGISTER
INTERRUPT THERM
TMIN/TRANGE
STATUS
REGISTER FAN_FAULT
REGISTER
VDD VCC
DC DC
VDD UNI/BIP PD
GAIN
COM
AD7742 POWER-DOWN
VIN1
LOGIC
ISHUNT RSHUNT OPTOCOUPLER
VIN2 R
VOLTAGE-TO-
INPUT FREQUENCY
VIN3 MUX X1/X2
MODULATOR fOUT
COM
VIN4
COM
ISOLATION
A1 CLOCK 2.5V BARRIER
VDD GENERATION REFERENCE
A0
VDD
COM
Figure 4. AD7742 used in application requiring galvanic isolation and digital outputs.
*These Figures are illustrative examples; they are not detailed schematics of
tested applications. Please consult product data sheets for more information.
You will also nd the online seminar notes, Practical Analog Design Tech-
niques, and the book, Practical Design Techniques for Sensor Signal Conditioning
(available from ADI), to be useful sources of design information. Use extreme
caution when working with high-voltage circuits.
AVDD DVDD
AD7715
MCLK IN
CLOCK
GENERATION
SERIAL INTERFACE MCLK OUT
VIN
REF IN (+)
REF VOUT REGISTER BANK RESET
192
REF IN ()
GND DRDY
AGND
Figure 5. AD7715/AD260 used in application requiring galvanic isolation and digital outputs.
fault condition in the motor could destroy the control electronics. network protects the inputs of the op amp, even though its power
The AD7742 synchronous voltage-to-frequency converter could supply voltage is much lower than the common-mode voltage.
be used, together with an opto-coupler and a dc-to-dc converter, Figure 6 shows the AD629 measuring the voltage of a 1.2-V cell
as shown in Figure 4. A remote AD7742 can be interfaced with that is part of a 120-V battery.
a system microprocessor or microcontroller to complete the A/D
conversion. For stand-alone applications the serial-output AD7715 +VS
3V TO 18V
analog front end, a 16-bit sigma-delta A/D converter, could be REF() 21.1k AD629
1 8 NC
used, but it has ve digital lines to isolate, rather than the single
IN 380k 380k
digital output from the V/F converter. However, instead of ve 2 7
(SEE
+VS 0.1F
opto-couplers and a dc-to-dc converter, an AD260 ve-channel TEXT)
+IN 380k
high-speed logic isolator with its own on-board transformer could 3 6 VOUT = VCELL
15V
REF() 21.1k AD629
1 8 NC
IN 380k 380k
2 7
VX +VS 0.1F
ISHUNT RSHUNT
1 +IN 380k 2.5V TO 5V AIN0 AD7887
2.5A 3 6
TO I/P
VY MUX T/H
5A VS 20k VREF/
REF(+)
4 5 AIN1
OUTPUT = VOUT VREF
2.5V COMP
NC = NO CONNECT REF
VREF/AIN1
VREF 2.5V VDD SOFTWARE
5V BUF
CONTROL
LATCH
GND
CHARGE
REDISTRIBUTION
DAC
SAR + ADC
CONTROL LOGIC
SPORT
Figure 7. AD629/AD7887 used in digital application where galvanic isolation is not required.
0.1F
0.1F
0.1F
0.1F 0.1F
0.1F 0.1F
Optimal Grounding Practice for a Bipolar Supply Environ- Optimal Grounding Practice in a Single Supply
ment with Separate Analog and Digital Supplies Environment
CM1 CM2
Chopper AmplifiersHow They Work
The first chopper amplifiers were invented more than 50 years
a. Auto-Zero Phase A: null amplifier nulls its own offset.
ago to combat the drift of dc amplifiers by converting the dc voltage
to an ac signal. Initial implementations used switched ac coupling VOSB EXTERNAL
of the input signal and synchronous demodulation of the ac signal VI+ FEEDBACK
VO
to re-establish the dc signal at the output. These amplifiers had AB
designs were only capable of inverting operation, since the CM1 CM2
stabilizing amplifiers output was connected directly to the non-
inverting input of the wide-band differential amplifier. Modern
IC chopper amplifiers actually employ an auto-zero approach b. Output Phase B: null amplifier nulls the main amplifier
offset.
using a two-or-more-stage composite amplifier structure similar
to the chopper-stabilized scheme. The difference is that the Figure 1. Switch settings in the auto-zero amplifier.
stabilizing amplifier signals are connected to the wide-band or main Both amplifiers use the trimmable op-amp model (Figure 2), with
amplifier through an additional nulling input terminal, rather differential inputs and an offset-trim input.
than one of the differential inputs. Higher-frequency signals bypass
the nulling stage by direct connection to the main amplifier or VI+
through the use of feed-forward techniques, maintaining a stable A VO
VI
zero in wide-bandwidth operation. B
VO = A(VI+ VI) +BVN
A = DIFFERENTIAL GAIN
This technique thus combines dc stability and good frequency VN B = TRIM GAIN
response with the accessibility of both inverting and noninverting
configurations. However, it may produce interfering signals Figure 2. Trimmable op amp model.
consisting of high levels of digital switching noise that limit the In the nulling phase (Phase AFigure 1a), the inputs of the nulling
usefulness of the wider available bandwidth. It also causes amp are shorted together and to the inverting input terminal
intermodulation distortion (IMD), which looks like aliasing between (common-mode input voltage). The nulling amplifier nulls its own
the clock signal and the input signal, producing error signals at inherent offset voltage by feeding back to its nulling terminal
the sum and difference frequencies. More about that later. whatever opposing voltage is required to make the product of that
In such applications, it is desirable to use a shunt with very low 20k 8k
sources are not critical. However, at low measured current values AD8554B
in the 1-mA range, the 100-V output voltage of the shunt demands 10.1k 1M
a very low offset voltage and drift to maintain absolute accuracy.
Low input bias currents are also needed, so that injected bias 10.1k
1M
current does not become a signicant percentage of the measured
current. High open-loop gain, CMR, and PSR all help to maintain
the overall circuit accuracy. As long as the rate of change of the Figure 2. Single-supply strain-gauge bridge amplifier.
excitation current also minimizes errors due to bridge self-heating. 10F 0.1F
0.1F
Most strain-gauge bridge applications are low-frequency by nature,
5k 4k
so the limited useful bandwidth of xed-frequency auto-zero 0.01% 3.9
0.01%
ampliers is not an issue. The use of bridges with higher frequency
outputs or with ac excitation can be accommodated through the a. Regulated 4.5 V from a supply as low as 4.7 V.
use of randomly clocked auto-zero ampliers.
5V
INFRARED (IR) SENSORS
Infrared (IR) sensors, particularly thermopiles, are increasingly
(1)
being used in temperature measurement for applications as wide- 2.5V AD8551
REFERENCE
ranging as automotive climate controls, human ear thermometers, 2.5V
the temperature measurement has been calibrated. The low 1/f ADR290 10k
10k
noise improves SNR for dc measurements taken over periods often
4 +2.5V
exceeding 1/5 second. Figure 3 shows an amplier that can bring
2.048V
ac signals from 100 to 300 microvolts up to the 1 to 3-V level.
AD8551
10k 100k 2.5V
100 100k
5V TIGHT-TOLERANCEMATCHED
5V RESISTORS NEEDED
This absence of negative feedback means that, unlike that of op SET HYSTERESIS
amp circuits, the input impedance is not multiplied by the loop
R4
gain. As a result, the input current varies as the comparator
switches. Therefore the driving impedance, along with parasitic 6 2 1
HEATING R3 V+
feedbacks, can play a key role in affecting circuit stability. While 7
ELEMENT REF-02 (9.2k) AD8561
SEE 3 3 6
negative feedback tends to keep amplifiers within their linear NOTE 1 5
R1 4
region, positive feedback forces them into saturation. (1.3k)
R2
Whats the Role of Hysteresis? (1.5k)
R5
Even without actual feedback circuitry, capacitive strays from the 2.2k
2N2222
output to an input (usually the noninverting input), or coupling
of output currents into ground (to which the noninverting input NOTES:
is often connected) may cause the comparator circuit to become 1. REF-02 SHOULD BE THERMALLY CONNECTED
TO SUBSTANCE BEING HEATED.
unstable. Guarding high-impedance nodes and paying careful 2. NUMBERS IN PARENTHESES ARE FOR A
SETPOINT TEMPERATURE OF 60 C.
attention to layout and grounding can help to minimize these 3. R1 = R2||R3||R4
coupling effects. Latching is also helpful.
Figure 2. Temperature-control circuit with REF02 reference/
But it is not always possible to prevent instability by these measures. sensor and AD8561 comparator. Hysteresis is introduced
An often-effective solution is to use positive feedback to introduce as needed via positive-feedback resistor, R4.
VCC VOH
R2 VPULL-UP
RPULL-UP R4
R1 VTL VT VTH VOUT
10 4 VIN
VREF
V+ 2
VOH
V VOL R3 RPULL-UP
9 10
18 VIN 4
INVERTING HYSTERESIS: V+ 2
VIN VTL = (R2*VREF + R1*VOL)/(R1 + R2) VOL
VEE 9 V
VTH = (R2*VREF + R1*VOH)/(R1 + R2) VREF 18 VIN
HYST = V TH V TL VTL VTH
R1
HYST = R1*(VOH VOL)(R1 + R2)
VPULL-UP (b)
R2 VOUT
VOH
Figure 5. Comparators in single-supply operation.
VCC
RPULL-UP VTL VT VTH
Placing a capacitor across the feedback resistor in the above
R1 10
VIN 4 VIN configurations will introduce a pole into the feedback network.
V+ 2
This has the triggering effect of increasing the amount of
9 V VOL
18 hysteresis at high frequencies. This can be very useful when the
NONINVERTING HYSTERESIS:
VREF VTH = ((R1 + R2)*VREF (R1*VOL))/R2 input is a relatively slowly varying signal in the presence of high-
VEE VTL = ((R1 + R2)*VREF (R1*VOH))/R2 frequency noise. At frequencies greater than f(p) = 1/(2CfRf),
HYST = V TH V TL
HYST = R1*(VOH VOL)/R2
the hysteresis approaches VTH = VCC and VTL = 0 V. At frequencies
less than f(p), the threshold voltages remain as shown in the
Figure 4. Comparator using noninverting input, dual supplies. equations.
R3 3 V VOL
Figure 8. Precision clamp circuit.
OUT 8
VIN
VTL VTH CONCLUSION
R4 Designers can use hysteresis to rid comparator circuits of
instabilities due to noise. Hysteresis is reliable and can be applied
Figure 7. Single-supply comparator with bipolar input. predictably using small amounts of positive feedback. b
EXCITATION
AC DC
TEMPERATURE
PRESSURE SIGNAL A/D
TRANSDUCER CONDITIONING CONVERTER
DISPLACEMENT VOLTAGE
LIGHT INTENSITY CURRENT
RESISTANCE
VDD
Figure 4. Typical wiring configurations for resistance based
sensors.
VDD
REF REF() The 2-wire configuration is the least accurate of the three systems
IN()
AIN
shown above, because the lead wire resistance, 2RL, and its variation
AIN() DOUT =
AIN DOUT VREF with temperature contribute significant measurement errors. For
OUT()
OUT() VREF
AIN()
example, if the lead resistance of each wire is 0.5 in each wire,
ADC RL adds a 1- error to the resistance measurement. Using a 100-
IN() REF()
RTD with = 0.00385/C, the resistance represents an initial
GND
error of 1 /(0.385 /C) or 2.6C, and variation of the lead
resistance with ambient temperature contributes further errors.
Figure 3. Non-ratiometric operation in a bridge-transducer The 3-wire configuration in Figure 4 offers significant
application. improvements over the 2-wire configuration due to the elimination
In the design of high-resolution data-acquisition systems, designers of one current-carrying lead wire. If the measurement wire
should always keep in mind the cost-effectiveness of ratiometric returning to V(+) feeds into a high impedance node, no current
operation wherever its use is feasible. flows in this wire and no wiring error is introduced. However, the
lead resistance and thermal characteristics of the RTD return wire
WIRING CONFIGURATIONS to V() and I() still introduces errors, so the errors have been
There are a variety of wiring configurations that can be employed reduced to one-half the error in a 2-wire system.
when connecting to resistive sensors such as RTDs and thermistors The 4-wire configuration in Figure 4 offers the best performance,
in temperature-measurement applications. The basic 2-, 3- and 4- in terms of accuracy and simplicity, compared to the 2- and 3-
wire connections are shown in Figure 4. Why are these formats wire configurations. In this application, the errors due to the lead-
available, with their various complexities and costs? Lead-wire wire resistance and thermal heating effects are removed by
resistance can introduce significant measurement errors if adequate measuring the temperature right at the RTD. The return wires
The AD7711, a high-resolution sigma-delta ADC, converts the ACX Q2, Q3 ON Q2, Q3 ON
voltage from the RTD to digital. The AD7711 is an ideal choice of
converter for this application; it offers 24-bit resolution, an on- Figure 7. Typical bridge configuration employing ac excitation.
chip programmable gain amplifier and a pair of matched RTD Figure 7 shows how a bridge can be configured for ac-excitation.
excitation current sources. As is evident from the example, a The polarity of the excitation voltage to the bridge is reversed on
complete solution can be built without the need for extra signal alternate cycles, using transistors Q1 to Q4 to perform the
conditioning components. switching. All the induced dc and low-frequency errors have been
lumped together as EOS. During phase 1, Q1 and Q4 are on while
AC EXCITATION
Q2 and Q3 are off; the output,VOUT, is given by (VA + EOS). During
Figure 6 shows some of the system error sources associated with
phase 2, Q2 and Q3 are on while Q1 and Q4 are off, with the
dc-excitation and measurement in a bridge sensor application. In
output, VOUT, represented by (VA + EOS). The actual output is
this bridge circuit, it is not possible to distinguish how much of
the sum of the two phases, giving VOUT = 2 VA.The control signals
the amplifiers dc (and low-frequency) output is actually from the
for the ac-excitation must be non-overlapping clock signals. This
bridge and how much is due to error signals. Errors introduced by
scheme removes the errors associated with dc excitation at the
1/f noise, parasitic thermocouples, and amplifier offsets cannot be
dealt with unless some method is used to differentiate the actual expense of a more complex design.
signal from these error sources. AC excitation is a good solution Figure 8 shows a bridge-transducer application using the AD7730
to this problem. bridge-transducer ADC, which includes on-chip all the necessary
circuitry to implement ac excitation and produce the computed
VDD
output result following the switching of the excitation.
T1
T2 AMP
The AD7730 sigma-delta ADC is a complete analog front-end for
weigh-scale and pressure-measurement applications. Operating
THERMOCOUPLE OFFSET
ERROR ERROR from a single +5-V supply, it accepts low-level signals directly from
a transducer and outputs a serial digital word. The input signal is
Figure 6. Error sources associated with dc-excitation in a bridge applied to a proprietary programmable gain front end, based on
transducer measurement system. an analog modulator. A low-pass programmable digital filter with
Q4 Q2 AVDD DVDD
REF IN(+)
AD7730
REF IN()
PLL
27MHz
AND
CLOCK
54MHz
CHROMA 10-BIT
DEMUX LPF DAC
ITUR.BT COLOR CONTROL
AND 2 10-BIT
656/601 DNR
OVERSAMPLING DAC
YCrCb- GAMMA COMPOSITE VIDEO
10-BIT YCrCb TO- CORRECTION SSAF 10-BIT Y [S-VIDEO] TV SCREEN
IN 4:2:2 FORMAT LPF DAC C [S-VIDEO] OR
YUV OR
MATRIX 10-BIT RGB PROGRESSIVE
DAC YUV SCAN DISPLAY
YPrPb
VBI 4 10-BIT
LUMA DAC
TELETEXT OVERSAMPLING
LPF
CLOSED CAPTION 10-BIT
CGMS/WSS DAC
I2C INTERFACE
ADV7194
GAMMA-CORRECTED AMPLITUDE
250
in improved picture quality. Depending upon the noise SIGNAL OUTPUTS
requirements, the user can program a threshold value that 200
determines the amount of noise attenuation applied. 0.3
0.5
Additionally, programming allows high-frequency signals to be 150
enhanced. When received, high-frequency signals with high
UT
amplitudes are assumed to be valid data. Applying a programmable NP
100
ALI
1.5
gain to these signals and adding them to the original signal results GN
SI
1.8
in an improvement in picture sharpness. 50
160
output to 10-bit DACs. With Xtended-10 technology, the ADV7194
allows data to be input in 10-bit format, processed at 10 bits, and
140
output to six 10-bit DACs. The 10-bit processing available in the
120 ADV7194 is of especial value in professional video applications.
100
THE ADV719x FAMILY
80 The ADV719x image processing facilities are unsurpassed. The
60
user has control over brightness, color, contrast, chroma, and luma,
0 20 40 60 80 100 120 140 160 as well as delay and programmable adjustment of sync pulsewidth
SAMPLES
and position. There are seven programmable luma filters, seven
Figure 3. Effect of digital noise reduction. Heavy trace is programmable chroma filters, and an extended SSAF filter with
output waveform. 12 programmable responses.
Gamma Correction: Gamma is the exponent applied to a signal The ADV719x also provides features such as TTX, CGMS,
voltage in an approximation of the nonlinear transfer function of a Macrovision, master/slave timing modes, VBI (vertical blanking
display device (e.g., a cathode-ray tube screen). Gamma = 1.0 interval) programming, and closed captioning.
would produce a perfectly linear plot, i.e., the output as a linear The technical performance of the ADV719x is outstanding,
function of the input. In CRTs the intensity of light produced on resulting in excellent signal quality. Errors in differential gain and
the screen of a CRT is a nonlinear function of the voltage applied phase are 0.2% and 0.4, respectively. SNR of up to 75 dB can
at the input, with a typical gamma value of 2.3 to 2.6. be achieved.
Gamma correction, a process of compensating for this nonlinearity, The AD719x runs on a single +5-V, +3.3-V, or +3-V supply. The
is necessary for reproducing good color with the correct intensity ADV7190 is packaged in a 64-lead LQFP. The ADV7192 and
in order to meet standards for picture appearance on a given screen. ADV7194 are packaged in 80-lead LQFPs.
The nonlinearity of the CRT should also be considered if an image Evaluation boards are available.The user simply connects the board
is to be coded in such a way as to make maximum perceptual use to the TV monitor when used with internal color bars, or a YCrCb
of a limited number of bits per pixel and to minimize the visibility signal source can be used. A PC running Windows 95/98 is
of noise. If uncompensated, the nonlinearity would create errors required. User-friendly software is provided. b
ANALOG
FRONT
END
AREA
CCD + CDS VGA ADC VIDEO LCD
IMAGE DAC DISPLAY
ARRAY 10/12 PROCESSING
UNIT
CLP HOST
COMPRESSION
VERTICAL INTERFACE
DC BIAS
DRIVE
TIMING
GENERATION
HD VD
PBLK AVDD AVSS CLPOB
6
BANDGAP VRT
CLPDM
OFFSET REFERENCE VRB
10 DAC
AUX1IN
2:1
MUX BUF INTERNAL
BIAS CML
AUX2IN
8
CONTROL
CLP REGISTERS
DVDD
DIGITAL INTERNAL
AD9841/AD9842 INTERFACE TIMING DVSS
9-BIT
DAC CONFIGURATION
REGISTER
MUX
VINB CDS PGA REGISTER SCLK
DIGITAL
RED CONTROL SLOAD
6 INTERFACE
9-BIT GREEN
DAC BLUE GAIN SDATA
REGISTERS
INPUT RED
CLAMP 9
OFFSET GREEN
BIAS OFFSET
BLUE
REGISTERS
Low Frequencies to 2
VPOS
FLTR
2.5 GHz
RFIN
AD8361
ERROR
Whatever the waveform, the 2
AMP
5
SREF
The AD8361 is a root mean-square (rms)-responding true-power- Figure 1. Functional block diagram.
detector analog IC for use in high-frequency receiver and How it works: The signal to be measured is applied to the input of
transmitter signal chains. Computing the rms value of simple and the rst squaring cell, which presents a nominal resistance of
complex waveforms containing frequencies up to 2.5 GHz, it is 225 ohms between the input pin (RFIN) and COMM (connected to
particularly useful for measuring the rms level of high-crest-factor the ground plane). Since the input pin is at a bias voltage of about
(peak-to-rms-ratio) signals, such as occur in systems employing 0.8 V above ground, a coupling capacitor is required. Because this
ordinary and wideband code-division multiple-access (CDMA and capacitor is an external component, it can be chosen to permit the
W-CDMA). Fabricated on a proprietary high-fT silicon bipolar measurement range to be extended to arbitrarily low frequencies.
process, it is housed in an 8-lead SOIC package and specied for
The squaring cell generates a current proportional to VIN2 and
operation from 40 to +85C.
applies it to a parallel R-C. Because of the low-pass ltering, the
The AD8361 is the newest development in a line of dedicated voltage developed across the resistor is proportional to the average
rms-to-dc conversion integrated circuits that started in 1977 with value of VIN2 (and the power dissipated in the devices input
the advent of the AD536 (Analog Dialogue 11-2). Prior to that time, resistance). Additional capacitance can be connected externally
large dedicated rms modules, such as Model 440, existed, but the to increase the ltering time constant as desired.
only ICs available in that class were analog multipliers, which can
This mean-square voltage is applied to one input of a high-gain
be used for rms in cumbersome, expensive circuits employing
error-sensing amplier. The ampliers other input is the output
squaring and division.
of a second squaring cell, which computes the square of the (fed-
The AD8361 can convert a modulated RF signal with a complex back) output of the amplier. At equilibrium then, the ampliers
waveform, containing frequencies up to 2.5 GHz, into a varying output is required to be proportional to the square root of the
dc voltage representing the rms level of the signal. Highly average value of VIN2 (i.e., the rms value of the input). A buffered
linear and stable with temperature, it is useful for the detection version of this amplier output becomes the device output.
of signals using CDMA, quadrature amplitude modulation
The squaring cells have very wide bandwidth and are capable of
(QAM), and other complex modulation schemes, with a 30-dB
responding to frequencies from dc to microwave. Because they
dynamic range. Measurement accuracy is to within 0.25 dB
are essentially identical and tend to track with temperature, the
over a 14-dB range, and 1 dB over a 23-dB range. It requires
conversion gain is pretty much independent of their individual
only 4 mA from a 2.7-V to 5.5-V power supply (and has a 1-A
gains and is stable with temperature.
power-down mode for conserving battery power when not in
use). An evaluation board is available (AD8361-EVAL). The The AD8361 responds to inputs of up to 390 mV rms with a 3-V
AD8361 is priced at $3.75 in 1,000s. supply and 660 mV rms with a 5-V supply. It has a nominal
conversion gain of 7.5 V/Vrms. Three operating offset modes are
WHY AN RMS IC available, to accommodate a variety of A/D converter requirements:
RMS ICs compute the true rms value of a waveform, performing Ground-referenced mode, with zero offset;
a running solution of the equation,
Internal reference mode, offsetting the output 350 mV
above ground;
1 t2
( )
2
T t 1 IN
VRMS = V dt Supply reference mode, offsetting the output to VS /7.5.
PLL/DDS MULTIPLICATION 10
PLL multiplication of a DDS signal to UHF and microwave
20
frequencies is easily and economically accomplished, but at a cost:
30
the advantages provided by DDS will be degraded in practically
every desirable attribute, including the phase-noise specication, 40
100
LMX1501A PLL CENTER 896MHz 30kHz/DIV SPAN 300kHz
DIVIDE-
Figure 4. 896 MHz PLL output signal.
14MHz DDS LPF
BY-64 LPF VCO 896MHz
PHASE 0
COMPARATOR DIVIDE-
BY-4096 10
20
Figure 2. Example of a DDS and PLL integration using an
30
LMX1501A PLL evaluation board and an AD9851 DDS.
40
PLL output phase noise is an obvious and easily observed
50
phenomenon; its magnication will degrade performance in
60
proportion to the multiplication factor of the PLL (expressed in
dB, 20 log fOUT/fIN). For example, if the frequency of a DDS signal 70
Spectral plots easily show how the phase noise of a DDS signal 10
these spurs within the 30 kHz loop bandwidth of the PLL have 90
been magnied. Note that >60 kHz away from the carrier, spur 100
CENTER 896.0135812MHz 30kHz/DIV SPAN 300kHz
amplitudes are not affected. The phase noise has not been altered
nor have any other parameters been changed. Figure 6. 896 MHz PLL output signal.
SILICON
Figure 7, showing a 200-MHz region of spectrum of a suppressed SWITCHING
DIODES
carrier (LO), single-upconversion mixer output, demonstrates this
problem with upconversion. The two sidebands are 50 MHz apart,
with LO feedthrough at a frequency midway between the two at Figure 8. Hookup and modification of Analog Devices evalu-
1.04 GHz This 50-MHz spread is only 5% of the 1-GHz output ation boards for lab evaluation.
frequency. Filtering the signals to remove the unwanted sideband Tests of this setup veried the performance expectations conveyed
and LO feedthrough will be extremely difcult. If the output in the AD8346 data sheet when the quadrature input signals from
frequency is increased to 2 GHz, it may complicate matters to the the AD9854 were properly adjusted to compensate for quadrature
point where ltering is impractical. To overcome this problem, phase error and I & Q amplitude imbalance. See Figures 9 and 10.
designers traditionally incorporate multiple stages of mixing and
Errors in the I & Q quadrature phase relationship are introduced
ltering to produce a DSB signal with larger sideband spacing at
after the signals exit the AD9854 ICby the lters, unequal cable
UHF/microwave that will be more easily ltered but at far greater
and PCB trace lengths, transformer differences, etc. System phase
expense and complexity.
errors cannot be corrected through programming changes of the
10 AD9854. Its outputs are fixed in accurate quadrature. Phase errors
20
can be corrected by adjusting cable lengths from the AD9854 to
the AD8346 evaluation board. Amplitude inequalities can be
30
corrected using the AD9854s 12-bit, independent sine and cosine
40 (I & Q), digital amplitude multiplier stages.
50
Figure 9 shows a 200-MHz segment of the output spectrum of
60
the AD8346 centered around 1.05 GHz. The DDS modulating
70 upper and lower sideband signals are seen 25 MHz away on either
80 side of the LO at 1.04 GHz. A difference of 40 dB is indicated
90
between the suppressed upper sideband (USB) and the favored
lower sideband (LSB) amplitudes. The 40-dB differential equates
100
to a power ratio of about ten-thousand to one.This level of sideband
110
CENTER 1.05GHz 20MHz/DIV SPAN 200MHz
suppression is indicative of approximately 1 degree of input-signal
phase mismatch.
Figure 7. DSB output from typical mixer.
0.8GHz TO
DIVIDE-BY-N 2.5GHz LO
REF CLK LO IN
IN IBBN
I
FILTERING, DC OFFSET IBBP
AD9854 AD8346
AND VOLTAGE STEP-UP VOUT
DDS QBBN
PARALLEL Q RF AMP
FSK/PSK PROGRAMMING QBBP
INPUT PORT
FSK/PSK 8
SERIAL DATA AM/FM FROM ANALOG AM OR FM
A/D
SOURCE CONTROLLER MODULATING SOURCE
Figure 11. Block diagram depicting the stages needed for an RF exciter producing
AM, FM, FSK, PSK modulated signals in the 800 to 2500 MHz frequency band.
Tx1DS
NEXT
Tx2US
FEXT
Tx3US
FEXT
Tx4US
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