Datasheetarchive 9404

S3C9404/P9404/C9414/P9414 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung's SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9404/C9414 MICROCONTROLLER
The S3C9404/C9414 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM87Ri CPU core. The S3C9404/C9414 is a versatile microcontroller, with its A/D
converter and a zero-crossing detection capability it can be used in a wide range of general purpose applications.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9404/C9414 has 4-Kbytes of program
memory on-chip (ROM) and 208-bytes of general purpose register area RAM.
Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core:
Four configurable I/O ports (S3C9404: 22 pins, S3C9414: 16 pins)

Six interrupt sources with one vector and one interrupt level
Two 8-bit timer/counter with various operating modes
Analog to digital converter (S3C9404: 8-bit, 8-channel, S3C9414: 10-bit, 5-channel)
One zero cross detection module
The S3C9404/C9414 microcontroller is ideal for use in a wide range of electronic applications requiring simple
timer/counter, PWM, ADC, ZCD and capture functions. S3C9404 is available in a 30-pin SDIP and a 32-pin SOP
package. S3C9414 is available in a 24-pin SDIP and a 24-pin SOP package.
OTP
The S3P9404/P9414 is an OTP (one time programmable) version of the S3C9404/C9414 microcontroller. The
S3P9404/P9414 has on-chip 4-Kbyte one-time programmable EEPROM instead of masked ROM. The
S3P9404/P9414 is fully compatible with the S3C9404/C9414, in function, in D.C. electrical characteristics and in
pin configuration.
1-1
PRODUCT OVERVIEW S3C9404/P9404/C9414/P9414
FEATURES
CPU Timer/Counter
SAM87Ri CPU core One 8-bit basic timer for watchdog function
One 8-bit timer/counter with three operating
Memory modes (10-bit PWM 1ch)
4-Kbyte internal program memory (ROM) One 8-bit timer/counter for the zero-crossing
208-byte general purpose register area (RAM) detection circuit
Instruction Set Zero-Crossing Detection Circuit
41 instructions Zero-crossing detection circuit that generates a

digital signal in synchronism with an AC signal
IDLE and STOP instructions added for input
power-down modes.
Buzzer Frequency Range
Instruction Execution Time
200 Hz to 20 kHz signal can be generated
600 ns at 10 MHz fOSC (minimum)
Operating Temperature Range
Interrupts
40C to + 85C
6 interrupt sources with one vector and one level
interrupt structure
Operating Voltage Range
Oscillation Frequency 2.7 V to 5.5 V
1 MHz to 10 MHz external crystal oscillator OTP Interface Protocol Spec

Maximum 10 MHz CPU clock Serial OTP
4 MHz RC oscillator
Package Types
General I/O 30-pin SDIP, 32-pin SOP for S3C9404/P9404
Four I/O ports (22 pins for S3C9404, 24-pin SDIP, 24-pin SOP for S3C9414/P9414
16 pins for S3C9414)
Bit programmable ports
A/D Converter
Eight analog input pins
8-bit conversion resolution (S3C9404)
10-bit conversion resolution (S3C9414)
1-2
BLOCK DIAGRAM
P1.0-P1.3
P0.0-P0.7 /ZCD,BUZ,T0,CLO
PORT 0 PORT 1
BASIC
TIMER
XIN
OSC
XOUT
I/O PORT I/O and P2.0-P2.3
INTERRUPT CONTROL /INT0-INT1
T0(PWM) TIMER 0 PORT 2
/ADC6-ADC7
P1.1/BUZ TIMER 1
SAM87RI CPU
ADC0 P3.0-P3.5
ADC PORT 3 /ADC0-ADC5
-ADC7
P1.0/ ZCD
ZCD
208-BYTE
4-KB ROM
REGISTER FILE
Figure 1-1. Block Diagram
1-3
PIN ASSIGNMENTS
VSS 1 30 VDD
XIN 2 29 P0.2
XOUT 3 28 P0.3
TEST 4 27 P0.4
P0.1 5 26 P0.5
P0.0 6 25 P0.6
RESET 7 S3C9404 24 P0.7
P3.5/ADC5 8 23 P1.0 / ZCD
P3.4/ADC4 9
30-SDIP 22 P1.1 / BUZ
P3.3/ADC3 10 (Top View) 21 P1.2 / T0(PWM)
P3.2/ADC2 11 20 P1.3 / CLO
P3.1/ADC1 12 19 P2.0 / INT0
P3.0/ADC0 13 18 P2.1 / INT1
AVSS 14 17 P2.2 / ADC6
AVref 15 16 P2.3 / ADC7
Figure 1-2. Pin Assignment Diagram (30-Pin SDIP Package)
VSS 1 32 VDD
XIN 2 31 P0.2
XOUT 3 30 P0.3
TEST 4 29 P0.4
P0.1 5 28 P0.5
P0.0 6 S3C9404 27 P0.6
RESET 7 32-SOP 26 P0.7
NC 8 (Top View) 25 NC
P3.5/ADC5 9 24 P1.0 / ZCD
P3.4/ADC4 10 23 P1.1 / BUZ
P3.3/ADC3 11 22 P1.2 / T0(PWM)
P3.2/ADC2 12 21 P1.3 / CLO
P3.1/ADC1 13 20 P2.0 / INT0
P3.0/ADC0 14 19 P2.1 / INT1
AVSS 15 18 P2.2 / ADC6
AVref 16 17 P2.3 / ADC7
Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package)
1-4
VSS 1 24 VDD
XIN 2 23 P0.2
XOUT 3 22 P0.3
TEST 4 21 P0.4
P0.1 5 S3C9414 20 P0.5
P0.0 6 19 P0.6
24-SDIP
RESET 7 18 P1.0 / ZCD
P3.4/ADC4 8
(Top View) 17 P1.1 / BUZ
P3.3/ADC3 9 16 P1.2 / T0(PWM)
P3.2/ADC2 10 15 P2.0 / INT0
P3.1/ADC1 11 14 AVref
P3.0/ADC0 12 13 AVSS
VSS 1 24 VDD
XIN 2 23 P0.2
XOUT 3 22 P0.3
TEST 4 21 P0.4
P0.1 5 KS86C4104 20 P0.5
P0.0 6 19 P0.6
24-SOP
RESET 7 18 P1.0 / ZCD
P3.4/ADC4 8 (Top View) 17 P1.1 / BUZ
P3.3/ADC3 9 16 P1.2 / T0(PWM)
P3.2/ADC2 10 15 P2.0 / INT0
1-5
PIN DESCRIPTIONS
Table 1-1. S3C9404/C9414 Pin Descriptions

Pin Pin Pin Circuit Share
Names Type Description Type Pins
P0.0-P0.7 I/O Bit-programmable I/O port for normal input or E-2
push-pull, open-drain output. Pull-up resistors are
assignable by software.
P1.0-P1.3 I/O Bit-programmable I/O port for Schmitt trigger F ZCD
input or push-pull output. Pull-up resistors are D BUZ
assignable by software. Port 1 pins can also be D T0(PWM)
used as alternative functions. D CLO
P2.0-P2.3 I/O Bit-programmable I/O port for Schmitt trigger E INT0INT1
input or push-pull, open drain output. Pull up E-1 ADC6ADC7
resistors are assignable by software. Port 2 can
also be used as external interrupt, A/D input.
P3.0-P3.5 I/O Bit-programmable I/O port for Schmitt trigger F ADC0ADC5
input or push-pull output. Pull-up resistors are
assignable by software. Port 3 pins can also be
used as A/D converter input.
XIN, XOUT Crystal/ceramic, or RC oscillator signal for system
clock.
INT0INT1 I External interrupt input. E P2.0P2.1
RESET I System RESET signal input pin. B
TEST I Test signal input pin (for factory use only: must be
connected to VSS)
VDD, VSS Voltage input pin and ground
AVREF, AVSS A/D converter reference voltage input and ground
ZCD I Zero crossing detector input F P1.0
BUZ O 200 Hz20 kHz frequency output for buzzer D P1.1
sound
T0 I/O Timer 0 capture input or 10-bit PWM output D P1.2
CLO O System clock output port D P1.3
ADC0ADC7 I A/D converter input F P3.0P3.5
E-1 P2.2P2.3
NOTE: Port 0.7, P1.3, P2.1P2.3 and P3.5 is not available in S3C9414/P4104 .
1-6
PIN CIRCUITS
VDD
VDD
P-CHANNEL P-CHANNEL
DATA
IN OUT
N-CHANNEL N-CHANNEL
OUTPUT
DISABLE
Figure 1-6. Pin Circuit Type A Figure 1-8. Pin Circuit Type C
VDD
VDD PULL-UP
RESISTOR
PULL-UP RESISTOR
RESISTOR P-CHANNEL
ENABLE
DATA
CIRCUIT
IN/OUT
IN OUTPUT TYPE C
DISABLE
DATA
Figure 1-7. Pin Circuit Type B Figure 1-9. Pin Circuit Type D
1-7
VDD VDD
VDD VDD
PULL-UP PULL-UP
PNE RESISTOR PNE RESISTOR
P-CH PULL-UP P-CH PULL-UP

ENABLE ENABLE
DATA IN/OUT DATA IN/OUT

N-CH N-CH
OUTPUT OUTPUT
DISABLE DISABLE
INPUT INPUT
Figure 1-10. Pin Circuit Type E Figure 1-10. Pin Circuit Type E-2
VDD
VDD VDD
PULL-UP
PNE RESISTOR PULL-UP
RESISTOR
PULL-UP
P-CH PULL-UP ENABLE
ENABLE VDD
DATA
DATA IN/OUT CIRCUIT
IN/OUT
N-CH OUTPUT TYPE C
DISABLE
OUTPUT
DISABLE
DIGITAL
INPUT
DIGITAL INPUT ANALOG

INPUT
ANALOG INPUT
Figure 1-11. Pin Circuit Type E-1 Figure 1-12. Pin Circuit Type F
1-8
S3C9404/P9404/C9414/P9414 ELECTRICAL DATA
13 ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9404/C9414 electrical characteristics are presented in tables and graphs:
Absolute maximum ratings

D.C. electrical characteristics
A.C. electrical characteristics
Oscillator characteristics
Oscillation stabilization time
Operating Voltage Range
Schmitt trigger input characteristics
Data retention supply voltage in Stop mode
Stop mode release timing when initiated by a RESET
A/D converter electrical characteristics
Zero-crossing detector
Zero Crossing Waveform Diagram
13-1
ELECTRICAL DATA S3C9404/P9404/C9414/P9414
Table 13-1. Absolute Maximum Ratings
(TA = 25C)
Parameter Symbol Conditions Rating Unit
Supply voltage VDD 0.3 to + 6.5 V
Input voltage VI All input ports 0.3 to VDD + 0.3 V
Output voltage VO All output ports 0.3 to VDD + 0.3 V
Output current I OH One I/O pin active 18 mA
high All I/O pins active 60
Output current I OL One I/O pin active + 30 mA
low Total pin current for ports 1, 2, 3 + 100
Total pin current for ports 0 + 200
Operating TA 40 to + 85 C
temperature
Storage TSTG 65 to + 150 C
temperature
Table 13-2. DC Electrical Characteristics
(TA = 40C to + 85C, VDD = 2.7 V to 5.5 V)

Parameter Symbol Conditions Min Typ Max Unit
Input high VIH1 Ports 1,2,3, and VDD= 2.7 to 5.5 V 0.8 VDD VDD V
voltage RESET
VIH2 Port 0 0.7 VDD
VIH3 XIN and XOUT VDD 0.1
Input low VIL1 Ports 1,2,3, and VDD= 2.7 to 5.5 V 0.2 VDD V
voltage RESET
VIL2 Port 0 0.3 VDD
VIL3 XIN and XOUT 0.1
Output high VOH IOH = 1 mA VDD= 4.5 to 5.5 V VDD 1.0 V

voltage ports 0, 1, 2, 3
Output low VOL1 IOL = 15 mA VDD= 4.5 to 5.5 V 0.4 2.0 V
voltage port 0
VOL2 IOL = 4 mA VDD= 4.5 to 5.5 V 0.4 2.0
port 1,2,3
13-2
Table 13-2. DC Electrical Characteristics (Continued)
(TA = 40C to + 85C, VDD = 2.7 V to 5.5 V)

Input high leakage ILIH1 All inputs except ILIH2 VIN = VDD 1 A
current
ILIH2 XIN, XOUT VIN = VDD 20
Input low leakage ILIL1 All inputs except VIN = 0 V 1 A
current ILIL2 and RESET
ILIL2 XIN, XOUT VIN = 0 V 20
Output high ILOH All outputs VOUT = VDD 2 A
leakage current
Output low ILOL All outputs VOUT = 0 V 2 A
leakage current
Pull-up resistors RP VIN = 0 V VDD = 5 V 30 47 70 k
Ports 03 and
RESET VDD = 3 V 30 280 350
Supply current IDD1 Run mode VDD = 5 V 10% 7.5 15 mA
10 MHz CPU clock
8 MHz CPU clock VDD = 3 V 10% 3 6
IDD2 Idle mode VDD = 5 V 10% 2 5
10 MHz CPU clock
8 MHz CPU clock VDD = 3 V 10% 0.7 2.5
IDD3 Stop mode VDD = 5 V 10% 0.1 5 A
VDD = 3 V 10%
NOTE: D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up
resisters, output port drive current, ZCD and ADC.
13-3
Table 13-3. AC Electrical Characteristics
(TA = 20C to + 85C, VDD = 2.7 V to 5.5 V)

Interrupt input tINTH, Port 2 200 ns
high, low width tINTL VDD = 5V 10%
RESET input tRSL Input 1 s

low width VDD = 5V 10%
ZCD noise filter
1 tCPU
tNF1L t NF1H
tRSL tNF2
0.8 VDD
0.2 VDD
NOTE: The unit tCPU means one CPU clock period.
Figure 13-1. Input Timing Measurement Points
13-4
Table 13-4. Oscillator Characteristics
(TA = 40C to + 85C)

Oscillator Clock Circuit Test Condition Min Typ Max Unit
Main crystal or VDD = 4.5 to 5.5 V 1 10 MHz
ceramic XIN VDD = 2.7 to 4.5 V 1 8
C1
XOUT
C2
External clock VDD = 4.5 to 5.5 V 1 10

XIN 1 8
VDD = 2.7 to 4.5 V
XOUT
RC oscillator VDD = 4.75 to 5.25 V 4

XIN
R = 8.2K (P1.3/
R CLO)
XOUT
Table 13-5. Oscillation Stabilization Time
(TA = 40C to + 85C, VDD = 2.7 V to 5.5 V)

Oscillator Test Condition Min Typ Max Unit
Main crystal f OSC > 1.0 MHz 20 ms
Main ceramic Oscillation stabilization occurs when VDD is equal 10
to the minimum oscillator voltage range.
External clock XIN input high and low width (tXH, tXL) 25 500 ns
(main system)
Oscillator tWAIT when released by a reset (1) 216/fOSC ms
stabilization
wait time tWAIT when released by an interrupt (2)
NOTES:
1. fOSC is the oscillator frequency.
2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the
settings in the basic timer control register, BTCON.
13-5
CPU CLOCK
10 MHz
8 MHz
4 MHz
3 MHz
2 MHz
1 MHz
1 2 2.7 3 4 5 5.5 6 7
SUPPLY VOLTAGE (V)
Figure 13-2. Operating Voltage Range
Vout
VDD
A = 0.2 V DD
B = 0.4 VDD
C = 0.6 VDD
D = 0.8 VDD
VSS
A B C D Vin
0.3 V DD 0.7 V DD
Figure 13-3. Schmitt Trigger Input Characteristics Diagram
13-6
Table 13-6. Data Retention Supply Voltage in Stop Mode
(TA = 40C to + 85C, VDD = 2.7 V to 5.5V)

Data retention VDDDR Stop mode 2.0 5.5 V
supply voltage
Data retention IDDDR Stop mode; VDDDR = 2.0 V 0.1 5 A
supply current
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
INTERNAL
IDLE MODE
RESET
(BASIC TIMER
ACTIVE)

STOP MODE
DATA RETENTION

VDD MODE
VDDDR NORMAL
EXECUTION OF OPERATING
STOP MODE
RESET
0.8 V DD
0.2 V DD
t WAIT
NOTE: tWAIT is the same as 4096 x 16 x 1/f OSC
Figure 13-4. Stop Mode Release Timing When Initiated by a RESET
13-7
Table 13-7. A/D Converter Electrical Characteristics (S3C9404)
(TA = 40C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) S3C9404: 8-bit ADC
Parameter Symbol Test Conditions Min Typ Max Unit
Total accuracy VDD = 5.12 V 2 LSB
Integral linearity ILE CPU clock = 10 MHz 1.5

error AVREF = 5.12 V
Differential DLE AVSS = 0 V 1

linearity error
Offset error of EOT 1 2

top
Offset error of EOB 1 2

bottom
Conversion tCON fcpu = 10 MHz 5 s

time(1)
Analog input VIAN AVSS AVREF V

voltage
Analog input RAN 2 M

impedance
ADC reference AVREF 2.5 VDD V

voltage
ADC reference AVSS VSS VSS + 0.3 V

ground
Analog input IADIN AVREF = VDD = 5 V 10 A

current conversion time = 5 s
ADC block IADC AVREF = VDD = 5 V 1 3 mA

current (2) conversion time = 5 s
AVREF = VDD = 3 V 0.5 1.5
conversion time = 5 s
AVREF = VDD = 5 V 100 500 nA
Power down mode
NOTES:
1. Conversion time is the time required from the moment a conversion operation starts until it ends.
2. IADC is operating current during A/D conversion.
13-8
Table 13-8. A/D Converter Electrical Characteristics (S3C9414)
(TA = 40C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) S3C9414: 10-bit ADC
Resolution 10 bit
Total accuracy VDD = 5.12 V 3 LSB
Integral linearity ILE CPU clock = 10 MHz 2

error AVREF = 5.12 V
Differential DLE AVSS = 0 V 1

linearity error
Offset error of EOT 1 3

top
Offset error of EOB 0.5 2

bottom
Conversion time tCON 10-bit conversion 20 s

(1) 50 x 4/ fOSC (3)
Analog input VIAN AVSS AVREF V

voltage
Analog input RAN 2 M

impedance
Analog AVREF 2.5 VDD V

reference
voltage
Analog ground AVSS VSS VSS + 0.3 V
Analog input IADIN AVREF = VDD = 5 V 10 A

current conversion time = 20 s
Analog block IADC AVREF = VDD = 5 V 1 3 mA

current (2) conversion time = 20 s
AVREF = VDD = 3 V 0.5 1.5 mA
conversion time = 20 s
AVREF = VDD = 5 V 100 500 nA
when power down mode
NOTES:
1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.
2. IADC is operating current during A/D conversion.
3. fOSC is the main oscillator clock.
13-9
Table 13-9. Zero Crossing Detector
(TA = 40C to + 85C, VDD = 4.5 V to 5.5 V, VSS = 0 V)

Zero-crossing VZC AC connection 1.0 3.0 Vp-p
detection input c = 0.1 F
voltage
Zero-crossing VAZC f ZC = 60 Hz 150 mV
detection accuracy (sine wave)
VDD = 5 V
f OSC = 10 MHz
Zero-crossing f ZC 40 200 Hz
detection input
frequency
1/fZC
AC Input VAZC VAZ(P-P)
ZCINT
Figure 13-5. Zero Crossing Waveform Diagram
13-10
70
VDD = 5.5 V
60
VDD = 5.0 V
50 VDD = 4.5 V
40
I OL (mA)
30
20
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VOL (V)
Figure 13-6. IOL vs. VOL (P0, TA = 25 C)
13-11
50
VDD = 5.5 V
40
VDD = 5.0 V
I OL (mA)
VDD = 4.5 V
30
20
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VOL (V)
Figure 13-7. IOL vs. VOL (P1P3, TA = 25 C)
13-12
36
32
28
24
I OH
20
(mA)
16
VDD = 5.5 V
12
VDD = 5.0 V
8
VDD = 4.5 V
4
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VOH (V)
Figure 13-8. IOH vs. VOH (P0, TA = 25 C)
13-13
24
I OH
20
(mA)
16
12
VDD = 5.5 V
8
VDD = 5.0 V
4
VDD = 4.5 V
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VOH (V)
Figure 13-9. IOH vs. VOH (P1P3, TA = 25 C)
13-14
S3C9404/P9404/C9414/P9414 MECHANICAL DATA
14 MECHANICAL DATA
OVERVIEW
The S3C9404/C9414 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package
(32-SOP-450A), a 24-pin SDIP package (24-SDIP-300) and a 24-pin SOP package (24-SOP-375). Package
dimensions are shown in Figures 14-1, 14-2, 14-3, and 14-4.
#30 #16
0-15
8.94 0.2
10.16
0.05
30-SDIP-400
0.25 +0.1
#1 #15
3.81 0.2
27.88 MAX
5.08MAX
27.48 0.2
0.56 0.1
3.30 0.3
0.51MIN
(1.30) 1.12 0.1 1.778
NOTE: Dimensions are in millimeters.
Figure 14-1. 30-Pin SDIP Package Dimensions
14-1
MECHANICAL DATA S3C9404/P9404/C9414/P9414
0~8
#32 #17
8.34 0.2
12.00 0.3
0.2
11.43
32-SOP-450A
0.78
#1 #16 +0.10
0.20 - 0.05
2.00 0.2
2.40MAX
19.90 0.2
0.10 MAX
0.0MIN
(0.43) 0.40 0.1 1.27
Figure 14-2. 32-SOP-450A Package Dimensions
14-2
S3C9404/P9404/C9414/P9414 MECHANICAL DATA
#24 #13
0-15
6.40 0.2
0.05
7.62
0.25 +0.1
24-SDIP-300
#1 #12
23.35 MAX
3.25 0.2
5.08MAX
22.95 0.2
3.30 0.3
0.51MIN
0.46 0.1
(1.69) 0.89 0.1 1.778
Figure 14-3. 24-SDIP-300 Package Dimensions
14-3
MECHANICAL DATA S3C9404/P9404/C9414/P9414
0-8
#24 #13
10.30 0.3
7.50 0.2
9.53
0.85 0.20
24-SOP-375
#1 #12 +0.10
0.15 - 0.05
2.30 0.2
15.74 MAX
2.70MAX
15.34 0.2
0.10 MAX
0.05MIN
(0.69) 0.38 0.1 1.27
Figure 14-4. 24-SOP-375 Package Dimensions
14-4
S3C9404/P9404/C9414/P9414 S3P9404/P9414 OTP
15 S3P9404/P9414 OTP
OVERVIEW
The S3P9404/P9414 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C9404/C9414 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P9404/P9414 is fully compatible with the S3C9404/C9414 , both in function and in pin configuration.
Because of its simple programming requirements, the S3P9404/P9414 is ideal for use as an evaluation chip for
the S3C9404/C9414 .
VSS/VSS 1 30 VDD/ VDD

XIN 2 29 P0.2/SCLK
XOUT 3 28 P0.3/SDAT
VPP/TEST 4 27 P0.4
P0.1 5 26 P0.5
P0.0 6 25 P0.6
RESET/RESET 7 S3P9404 24 P0.7
P3.5/ADC5 8 23 P1.0/ZCD
P3.4/ADC4 9
30-SDIP 22 P1.1/BUZ
P3.3/ADC3 10
(Top View) 21 P1.2/T0(PWM)
P3.2/ADC2 11 20 P1.3/CLO
P3.1/ADC1 12 19 P2.0/INT0
P3.0/ADC0 13 18 P2.1/INT1
AVSS 14 17 P2.2/ADC6
AVref 15 16 P2.3/ADC7
NOTE: The bolds indicate an OTP pin name.
15-1
S3P9404/P9414 OTP S3C9404/P9404/C9414/P9414
VSS/VSS 1 32 VDD/ VDD

XIN 2 31 P0.2/SCLK
XOUT 3 30 P0.3/SDAT
VPP/TEST 4 29 P0.4
P0.1 5 28 P0.5
P0.0 6 S3P9404 27 P0.6
RESET/RESET 7 32-SOP 26 P0.7
NC 8 (Top View) 25 NC
P3.5/ADC5 9 24 P1.0/ZCD
P3.4/ADC4 10 23 P1.1/BUZ
P3.3/ADC3 11 22 P1.2/T0(PWM)
P3.2/ADC2 12 21 P1.3/CLO
P3.1/ADC1 13 20 P2.0/INT0
P3.0/ADC0 14 19 P2.1/INT1
AVSS 15 18 P2.2/ADC6
AVref 16 17 P2.3/ADC7
15-2
S3C9404/P9404/C9414/P9414 S3P9404/P9414 OTP
VSS/V SS 1 24 VDD/ VDD

XIN 2 23 P0.2/ SCLK
XOUT 3 22 P0.3/ SDAT
VPP/TEST 4 21 P0.4
P0.1 5 S3P9414 20 P0.5
P0.0 6 19 P0.6
24-SDIP
RESET/RESET 7 18 P1.0/ZCD
P3.4/ADC4 8
(Top View) 17 P1.1/BUZ
P3.3/ADC3 9 16 P1.2/T0(PWM)
P3.2/ADC2 10 15 P2.0/INT0
15-3
S3P9404/P9414 OTP S3C9404/P9404/C9414/P9414
VSS/V SS 1 24 VDD/ VDD

XIN 2 23 P0.2/ SCLK
XOUT 3 22 P0.3/ SDAT
VPP/TEST 4 21 P0.4
P0.1 5 S3P9414 20 P0.5
P0.0 6 19 P0.6
RESET/RESET 7
24-SOP 18 P1.0/ZCD
P3.4/ADC4 8 (Top View) 17 P1.1/BUZ
P3.3/ADC3 9 16 P1.2/T0(PWM)
P3.2/ADC2 10 15 P2.0/INT0
15-4
S3C9404/P9404/C9414/P9414 S3P9404/P9414 OTP
Table 15-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming
Pin Name Pin Name Pin No. I/O Function
P0.3 SDAT S3P9404: 28 (30) I/O Serial data pin (output when reading, Input
S3P9414: 22 (22) when writing) Input and push-pull output
port can be assigned
P0.2 SCLK S3P9404: 29 (31) I/O Serial clock pin (input only pin)
S3P9414: 23 (23)
TEST VPP (TEST) 4 I Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. (Option)
RESET RESET 7 I Chip Initialization

VDD/VSS VDD/VSS S3P9404: 30 (32) / 1 I Logic power supply pin.
S3P9414: 24 (24) / 1
NOTE: ( ) means the SOP OTP pin number.
Table 15-2. Comparison of S3P9404/P9414and S3C9404/C9414 Features

Characteristic S3P9404/P9414 S3C9404/C9414
Program Memory 4-Kbyte EPROM 4-Kbyte mask ROM
Operating Voltage (VDD) 2.7 V to 5.5 V 2.7 V to 5.5 V
OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V
Pin Configuration 30 SDIP/32 SOP/24 SDIP/24 SOP
EPROM Programmability User Program 1 time Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P9404/P9414, the EPROM programming mode is
entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins
listed in Table 15-3 below.
Table 15-3. Operating Mode Selection Criteria
VDD VPP MEM

REG/MEM ADDRESS R/W MODE
(TEST) (A15-A0)
5V 5V 0 0000H 1 EPROM read
12.5 V 0 0000H 0 EPROM program
12.5 V 0 0000H 1 EPROM verify
12.5 V 1 0E3FH 0 EPROM read protection
NOTE: "0" means Low level; "1" means High level.
15-5
S3P9404/P9414 OTP S3C9404/P9404/C9414/P9414
NOTES
15-6

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S3C9404/P9404/C9414/P9414 PRODUCT OVERVIEW

SAM87RI PRODUCT FAMILY

Four configurable I/O ports (S3C9404: 22 pins, S3C9414: 16 pins)

Instruction Set Zero-Crossing Detection Circuit

41 instructions Zero-crossing detection circuit that generates a

1 MHz to 10 MHz external crystal oscillator OTP Interface Protocol Spec

Figure 1-1. Block Diagram

Figure 1-2. Pin Assignment Diagram (30-Pin SDIP Package)

Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package)

Figure 1-4. Pin Assignment Diagram (24-Pin SDIP Package)

Figure 1-5. Pin Assignment Diagram (24-Pin SOP Package)

Table 1-1. S3C9404/C9414 Pin Descriptions

P-CH PULL-UP P-CH PULL-UP

DATA IN/OUT DATA IN/OUT

DIGITAL INPUT ANALOG

Absolute maximum ratings

Table 13-1. Absolute Maximum Ratings

Table 13-2. DC Electrical Characteristics

(TA = 40C to + 85C, VDD = 2.7 V to 5.5 V)

VIH3 XIN and XOUT VDD 0.1

VIL3 XIN and XOUT 0.1

Output high VOH IOH = 1 mA VDD= 4.5 to 5.5 V VDD 1.0 V

Table 13-2. DC Electrical Characteristics (Continued)

(TA = 40C to + 85C, VDD = 2.7 V to 5.5 V)

Table 13-3. AC Electrical Characteristics

(TA = 20C to + 85C, VDD = 2.7 V to 5.5 V)

RESET input tRSL Input 1 s

NOTE: The unit tCPU means one CPU clock period.

Figure 13-1. Input Timing Measurement Points

Table 13-4. Oscillator Characteristics

(TA = 40C to + 85C)

External clock VDD = 4.5 to 5.5 V 1 10

RC oscillator VDD = 4.75 to 5.25 V 4

Table 13-5. Oscillation Stabilization Time

(TA = 40C to + 85C, VDD = 2.7 V to 5.5 V)

Figure 13-2. Operating Voltage Range

Figure 13-3. Schmitt Trigger Input Characteristics Diagram

Table 13-6. Data Retention Supply Voltage in Stop Mode

(TA = 40C to + 85C, VDD = 2.7 V to 5.5V)

NOTE: tWAIT is the same as 4096 x 16 x 1/f OSC

Figure 13-4. Stop Mode Release Timing When Initiated by a RESET

Table 13-7. A/D Converter Electrical Characteristics (S3C9404)

Integral linearity ILE CPU clock = 10 MHz 1.5

Differential DLE AVSS = 0 V 1

Offset error of EOT 1 2

Offset error of EOB 1 2

Conversion tCON fcpu = 10 MHz 5 s

Analog input VIAN AVSS AVREF V

Analog input RAN 2 M

ADC reference AVREF 2.5 VDD V

ADC reference AVSS VSS VSS + 0.3 V

Analog input IADIN AVREF = VDD = 5 V 10 A

ADC block IADC AVREF = VDD = 5 V 1 3 mA

Table 13-8. A/D Converter Electrical Characteristics (S3C9414)

Integral linearity ILE CPU clock = 10 MHz 2

Differential DLE AVSS = 0 V 1

Offset error of EOT 1 3

Offset error of EOB 0.5 2

Conversion time tCON 10-bit conversion 20 s

Analog input VIAN AVSS AVREF V

Analog input RAN 2 M

Analog AVREF 2.5 VDD V

Analog ground AVSS VSS VSS + 0.3 V