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2014 19th IEEE European Test Symposium (ETS)

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Cell-aware Experiences in a High-Quality
Automotive Test Suite
F.Hapke1, R.Arnold2, M.Beck2, M.Baby2, S.Straehle2, J.F.Goncalves2, A.Panait2, R.Behr2, G.Maugard2, A.Prashanthi2,
J.Schloeffel1, W.Redemund1, A.Glowatz1, A.Fast1, J.Rajski3
1 2 3
Mentor Graphics Infineon Technologies Mentor Graphics
Hamburg, Germany Munich, Germany Wilsonville, Oregon, USA

AbstractHigh quality is an absolute necessity for automotive CA library characterization flow consisting of a layout
designs. This paper describes an approach to improve the overall extraction step, an analog fault simulation step of all CI bridges
defect coverage for CMOS-based high quality automotive designs. and opens and the CA synthesis step to create the new CA
We present results from a cell-aware (CA) characterization flow for ATPG library views. These finally can be used in a normal
216 cells, the pattern generation flow for a 130nm smart power chip design flow to generate production test patterns, which
design, and high-volume production test results achieved after had a significantly higher quality than state-of-the-art patterns.
testing multimillion parts. The idea behind CA tests is to detect cell- Achieving a high percentage of defect coverage is desirable for
internal (CI) bridges, opens, leaking and high resistive transistor integrated circuit chips manufactured for automotive
defects which are undetected with state-of-the-art tests. The
applications. Hence the purpose of test generation has been to
production test results have shown that the CA tests detect various
failing parts during a first wafer sort test which still resulted into
create a set of test patterns that detect as many manufacturing
unique failing parts after a second wafer sort test done at a
defects as possible.
different temperature and with additional tests. The obtained results First production test results for a 32nm technology have
encouraged us to continue this work beyond this paper to run been presented in [12] and [14]. In this paper we now focus on
further experiments with the final goal to eliminate the stuck-at a full application of the CA methodology, which includes slow-
(SA) and transition delay (TR) test by simultaneously improving the speed and at-speed CA tests for bridges and opens as well as
quality with CA tests which are a superset of SA and TR tests. transistor defects for a mature 130nm automotive technology.
1 INTRODUCTION Production test results from multimillion tested ICs of a high
quality automotive design and test flow are shown. Also
Todays demands for high quality automotive devices are included is an extensive outlook to the next steps with the final
extremely challenging. Higher performance of the integrated target to eliminate the state-of-the-art SA and TR tests by
circuit has to be combined with higher density on chip and applying CA tests to all automotive ICs, with the clear goal of
Zero-PPM fail rates. This can be managed only if all possible improving the quality and carefully reducing the test costs. A
defects in an integrated design can be addressed. Such physical physical failure analysis (PFA) needs to be done to check if the
defects can be shorts and opens external to library cells, but CA tests really find field quality relevant defects. In the
also inside of library cells, e.g. defects like leaking and following sections of the paper the potential defects found by
resistive transistors. One accepted method to deal with these the CA tests are called CA defects to differentiate from the
kinds of defects is fault-modeling. Such models can be used to field quality.
describe a specific faulty behavior in a sophisticated model.
2 VALIDATION FLOW 130NM DESIGN
This has been done since decades using well-known fault-
models like stuck-at [1], gate- and transition-delay [2], bridge- The investigation as shown in Fig. 1 incorporates the
[3] and gate-exhaustive [4] models as well as N-detect [5] and comparison of the CA with the traditional SA model and the
embedded-multi-detect [6] methods. In addition, as well TR fault model for an industrial design in a 130nm technology.
timing-aware [7] and layout-aware [8] fault modeling is state- The validation flow starts with the generation of state-of-
of-the-art. All of those models cover design structures like the-art SA and TR patterns. The second step in the flow is the
metal lines and interconnects between standard cells in an verification of the SA and TR patterns with respect to the CA
integrated circuit design. None of the mentioned fault models fault model. This evaluation is accomplished by a fault-
cover CI defects explicitly.
simulation of the SA and TR patterns considering the CI
One approach to deal with CI defects is the CA defects. The third step is the generation of the CA patterns
methodology [9], [10], [13]. Numerous publications about the which do achieve the highest possible defect coverage also
CA approach showed that the classical SA, TR, N-detect (ND) detecting all CI defects. As described in [14], a library
and gate-exhaustive (GE) approaches [11] do not target all real characterization is performed in advance once per technology
defects inside library cells or are too expensive for production node to create the needed CA view for each cell of the standard
tests. library. The results of this library characterization for the
130nm technology used in this design are presented in the
An overview of the latest state-of-the-art of the CA following two sub-chapters.
methodology was given in [14]. The tutorial covered the whole

978-1-4799-3415-7/14/$31.00 2014 IEEE


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2.2 The Cell Pattern Graph


This section presents results with respect to the number of
! test patterns generated for each stand-alone library cell in
isolation without instantiating the cell in a design. Fig. 3 shows
the number of test patterns generated for each library cell.

Fig. 1. Validation Flow

2.1 The Defect Coverage Graph


In total 216 high voltage threshold (HVT) cells from a
130nm technology have been analyzed. Fig. 2 shows the
deficiency of the state-of-the-art SA and TR patterns to detect
all testable CA-related defects calculated by the CA flow.
The horizontal axis represents the library cells numbered
from 0 to 215. The vertical axis represents three defect Fig. 3. Pattern Graph on Standard Cell Level
coverage rates in percent. The green line is the defect coverage
rate of the testable CA defects (always at 100%) for CA slow- The horizontal axis represents the individual library cells
speed and at-speed patterns. The blue line is the defect (from cell 0 to cell 215). The vertical axis represents the
coverage rate for the CA static defects achieved with state-of- number of patterns for each cell. The cells are sorted in
the-art SA patterns. The red line is the defect coverage rate for descending order of their pattern count from left to right. The
the CA dynamic defects achieved with state-of-the-art TR blue line is the sum of SA and TR patterns for each cell, and
patterns. the green line is the sum of CA slow-speed and at-speed
patterns.
As can be seen, for about 40% of the cells, the CA defect
coverage of SA patterns is less than 100%; some cells just The 216 analyzed cells include buffers and inverters and as
reach a CA defect coverage of 50%. The cell types with the such at the right side of the pattern graph the cells with 4
worst CA defect coverage figure from SA patterns are adder, patterns can be seen. In this case the number of SA+TR
xor, and-or, flip-flops and mux cells. The situation is patterns is equal to the number of CA patterns so that the blue
worse for TR patterns: only about 21% of the cells reach 100% line is hidden and only a green line is visible.
CA defect coverage. In fact, many cells (about 30) have a CA The left side of the pattern graph shows and-or-type of cells
defect coverage of less than 50%, while some cells reach just with 4 to 6 inputs, followed by scan flip-flops up to cell
20%. The cells with the lowest CA defect coverage are adder number 20. The peak in the graph at the x-axis position around
and and-or cells. We also included buffers (buf) and inverters cell number 70 is from full adder cells. At position 120 to 130
(inv). Therefore, the graph in Fig. 2 shows just a green line at the half adder and xor gates with 3 inputs can be found.
the right side from cell number 169 to 215, i.e. nothing can be
gained for buffers and inverters. The pattern graph in Fig. 3 clearly shows that state-of-the-
art SA and TR patterns are insufficient to detect all detectable
CI defects. Nearly all cells require more patterns to detect all
CI defects and the CA ATPG is forced to generate those
patterns.
2.3 Defect Coverage Gain
To calculate the CA defect coverage gain for the selected
130nm automotive design (shown in Fig. 10) we generated SA,
TR and CA pattern as shown in Fig. 1. The overall CA
coverage gain for the chip is 0.63% for slow-speed CA versus
SA patterns and 3.83% for CA at-speed versus TR patterns. We
also reported the individual coverage gain figures per cell type
as used in the automotive design which is shown for the
additional CA at-speed detected defects in Fig. 4.

Fig. 2. Defect Coverage Graph


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To further investigate the large CA only detected CA


defects in the SFD cell types, we analyzed the cell input
! patterns that are applied during the SA and TR tests and
noticed that all possible input combinations for D and TI are
used in the huge pattern set, but each time when the required
input combination was applied the clock was gated preventing
capture. Due to low-power requirements there are multiple
stages of clock gating for nearly all flip-flops. In some cases
the enable condition is that complex that capture happens in
only very few patterns. The ATPG tool has enabled the clock
gates only when needed to test the traditional faults at the D
input of the flip-flops.
2.5 Cell-aware Detections in SANR2 Cells
To further investigate the large CA only detected CA
defects in the and-nor cell types, we selected the SANR2 cell
Fig. 4. At-speed Defect Coverage Gain
with four inputs. The test pattern count achieved with a
The blue line shows the number of CA-only detected at- traditional ATPG tool for this cell is 10, but CA requires 17
speed CA defects per cell type. The red line displays the patterns.
relative CA defect coverage gain, again with respect to the Fig. 6 shows the layout of this SANR2 cell and one of the
related cell type. It can be seen from the graph that the SFD CA defects that is not guaranteed to be detected with state-of-
cells (scan flip-flops) contribute most to the additional detected the-art test patterns. Shown is a CA bridge defect D1 (in red)
CA defects (8009) in this design. The relative coverage gain for on metal1 between the cell input A and C. It is obvious
the SFD cell type is 4.08%. The second biggest impact to the that this bridge defect is likely to occur during the production
additional detected CA defects (5802) is from the SANR2 cell process.
type (and-nor cell), the relative coverage gain for this cell type
is 5.43%. The third biggest impact is from SFA cell types (full
adder cells) with 5198 defects and a relative coverage gain of
10.14%. The cell SOAN2 (or-and cell) shows a very high
relative coverage gain (of about 12.7%), but only 980
additional CA defects are detected overall due to the small
number of instances in this design.
In the following three sub-chapters we will present our
findings for the first three cell types that contributed most to
the additional CA only detected defects.
2.4 Cell-aware Detections in SFD Cells
In this 130nm automotive design the undetected at-speed
CA defects in scan flip-flops cells contributed most to the
additional CA only detected CA defects as shown in Fig. 4.
Fig. 6. Layout of the SANR2 Cell
Fig. 5 shows a basic scan flip-flop. The undetected CA
defects in SFD cells are present when the test enable input (TE) Fig. 7 shows the possible location of that CA bridge defect
is low (0). In that situation state-of-the-art ATPG tools will D1 between the cell inputs A and C. To detect this defect
assign the needed states at the data inputs of the SFD, but the safely there are two static test patterns out of the 16 possible
tool is not forced to also assign the needed state at the test input CA slow-speed input patterns that will detect that bridge. One
(TI) of the SFD. input pattern is A=1, B=0, C=0 and D=1 for A dominant
over C, the other one is A=0, B=1, C=1 and D=0 for C
dominant over A. A state-of-the-art SA ATPG is not forced
to generate one of those two input patterns, but the CA ATPG
is forced deterministically to generate one of the two required
patterns to safely detect the bridge CA defect D1.
The total number of all CA defects not detected with SA
and TR patterns is 26. This means there are 26 defects that are
not covered with state-of-the-art SA and TR patterns even if CI
faults are considered on all instantiated gates within the
SANR2 cell. The majority, i.e. 13 of the undetected CA defects
are open defects followed by four Ton (leaking transistor), six
Fig. 5. Undetected Defects in SFD Cells Toff (none switching transistor) and three bridge defects.
!

The CA defect D1 is an open from the drain of M9 to the


source of M10, i.e. an open between the cell-internal nets
! M9:d and M10:s as listed in Fig. 8. The involved layer for
this D1 defect is metal1 (M1). Another CA defect D3 is an
open between the nets named B:51 and M12:g, which is an
open in the poly line from the B input of the adder to the gate
of the transistor M12. The defects D5, D6, D7 are CA
transistor-off defects of the transistors M10, M11 and M12. It
is obvious that those CA defects are likely to occur during the
production process. All 7 listed and highlighted defects have in
common that they only can be detected when the test patterns
contain the needed initial time (IT) and final time (FT) frame
states at the cell inputs. The CA ATPG is forced to generate the
needed IT and FT conditions at the cell input and as such also
those cell-internal open defects are detected deterministically
Fig. 7. Transistor Schematic of the SANR2 Cell
by CA patterns.
2.6 Cell-aware Detections in SFA Cells 3 PRODUCTION TEST OF A 130-NM DESIGN
To investigate the large CA only detected defects in adder For evaluating the effectiveness of the CA slow-speed and
cell types, we selected the SFA1 cell. This cell is a full-adder
at-speed patterns in relation to the automotive production test,
cell with three inputs (A, B, CI) and two outputs (S, CO). The
we chose a novel all on one chip 130nm high quality
state-of-the-art test pattern count for this cell is eight (4 SA + 4
automotive design where a lot of circuit blocks are
TR), but CA requires 21 patterns. When using a full gate-level
monolithically integrated which used to be separated on older
description for a full-adder and considering CI faults on all
technologies, see Fig. 10.
instantiated gates, then normal ATPGs will typically generate
19 (8 SA + 11 TR) patterns. But those 19 patterns will still not
detect all CI defects as they will be detected with 21 CA
patterns. The list of all CA defects which are not detected with
SA and TR patterns is shown below in Fig. 8.

Fig. 10. 130nm Automotive Design


Fig. 8. SA/TR undetected Defects in cell SFA1

As listed in Fig. 8 there are seven CA defects (named D1 to The device contains an 8 bit C, Flash, SRAMs, Boot-
D7) that are not covered with state-of-the-art SA and TR ROM, on-chip OSC and PLL. Mixed signal components like
patterns, even not when CI faults are considered on a full gate multiple SAR ADCs / DACs are included as well. In addition
level description for the full adder cell. Fig. 9 shows these to the digital / mixed signal parts, a large power part is included
seven defects in the layout of the full-adder cell SFA1 which contains Low Side and High Side switches, a LIN
transceiver and High Voltage Monitor inputs. What is very
typical for those devices are the multiple on-chip voltage
regulators which take care on the internal voltage supplies.
Therefore, just a supply connection to the car battery is needed.
3.1 Experimental Test Flow
To investigate the effectiveness of the CA patterns in
relation to traditional SA, TR, IDDQ patterns and automotive-
specific Other Tests (OT1, OT2), we added the experimental
CA patterns to the test program and changed the test flow to
log unique CA fails as shown in Fig. 11 and Fig. 12.

Fig. 9. Layout of the SFA1 cell


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speed test vectors is 10,600, which results in a test vector count


increase of 94% compared to the existing TR patterns.
!
3.2 Wafer Sort Results
After enhancing the production test program as shown in
Fig. 11, we applied the normal production patterns and
experimental CA patterns during hot temperature wafersort1
Fig. 11. Wafersort1 Test Flow
for the 130nm automotive design. Fig. 14 summarizes the
number of CA failing parts in percent detected by the
Wafersort1 is performed at a hot temperature and consists
wafersort1 test program flow after having tested multimillion
of a slow-speed SA test, followed by an at-speed TR test. For
parts.
the CA experiments these two tests have been extended with a
CA slow-speed test (CA1) as well as a CA at-speed test (CA2).
The CA1 slow-speed patterns are topoff patterns to the existing
maximum coverage SA patterns. The CA2 at-speed patterns
are topoff patterns to the complete set of existing TR at-speed
patterns. A much more efficient and test time optimized pattern
set could be used in production by eliminating the SA and TR
patterns because the CA patterns are a superset of the SA and
TR patterns, but this was not done for this experiment because
we wanted to log the CA only detected parts. As the SA and
TR patterns have been executed before the CA tests any fail
detected by the CA patterns completely passed the normal SA
and TR tests. In addition, we executed several hundred of so-
called Other Tests1 (OT1) which are a mixture of digital and
analog tests also contributing significantly to the total test time.
All patterns except the CA patterns have been executed in
stop on fail mode. The two CA tests were done in data- Fig. 14. CA Failing Parts from Wafersort1
collection (monitoring, not stop on fail) mode, such that we
get the needed data for creating a Venn diagram. The slow-speed CA patterns detect a total of 23.7% (15.8%
+ 7.9%) from all CA failing parts. The at-speed CA patterns
The wafersort2 test flow shown in Fig. 12 is performed at detect a total of 84.2% (76.3% + 7.9%) from all CA failing
room temperature. It contains additional IDDQ tests which parts. The automotive-specific OT1 patterns do not detect any
contribute significantly to the total test time as well. The Other of the CA failing parts. The Venn diagram also shows the 7.9%
Tests2 (OT2) are with some changes comparable to wafersort1. overlap between the two CA tests. The resulting summary is
The CA tests are not executed again. The CA fail information that the CA1 has 15.8% unique fails and the CA2 detects
has been stored in a non-volatile (NV) memory on-chip in 76.3% unique fails.
wafersort1. Using this data, the CA binning is done at the end
of wafersort2 which allows identifying unique CA fails that The results from wafersort2 flow are shown in Fig. 15. As
have passed all other tests of wafersort1 and wafersort2. explained before, the wafersort2 is performed at room
temperature and in addition to the wafersort1 test flow the
wafersort2 test flow also executes an IDDQ test as part of the
normal production test.

Fig. 12. Wafersort2 Test Flow

The number of production and experimental test patterns


applied to the chosen 130nm automotive chip is shown in Fig.
13.

Fig. 13. Number of Test Patterns

As can be seen, the 1,200 additional CA1 slow-speed test Fig. 15. CA Failing Parts from Wafersort2
patterns increase the scan volume by 43% compared to the
existing SA production patterns. The quantity of the CA2 at-
!

The red circle in Fig. 15 includes all CA failures from REFERENCES


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39th Int'l Symposium for Testing & Failure Analysis, ISTFA
The authors thank Guenter Mueller, Michael Wittke, 2013
Martin Keim, Jay Jahangiri, Ahmad Abde Yazdani, Udo John,
Justus Kuhn, Anton Huber, Rosi Deppe, Erik Cordes, Hermann
Obermeir, Rainer Kress, and Mark Kassab for their assistance,
valuable discussion, implementations, and insight during this
project.

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