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Cell-aware Experiences in a High-Quality
Automotive Test Suite
F.Hapke1, R.Arnold2, M.Beck2, M.Baby2, S.Straehle2, J.F.Goncalves2, A.Panait2, R.Behr2, G.Maugard2, A.Prashanthi2,
J.Schloeffel1, W.Redemund1, A.Glowatz1, A.Fast1, J.Rajski3
1 2 3
Mentor Graphics Infineon Technologies Mentor Graphics
Hamburg, Germany Munich, Germany Wilsonville, Oregon, USA
AbstractHigh quality is an absolute necessity for automotive CA library characterization flow consisting of a layout
designs. This paper describes an approach to improve the overall extraction step, an analog fault simulation step of all CI bridges
defect coverage for CMOS-based high quality automotive designs. and opens and the CA synthesis step to create the new CA
We present results from a cell-aware (CA) characterization flow for ATPG library views. These finally can be used in a normal
216 cells, the pattern generation flow for a 130nm smart power chip design flow to generate production test patterns, which
design, and high-volume production test results achieved after had a significantly higher quality than state-of-the-art patterns.
testing multimillion parts. The idea behind CA tests is to detect cell- Achieving a high percentage of defect coverage is desirable for
internal (CI) bridges, opens, leaking and high resistive transistor integrated circuit chips manufactured for automotive
defects which are undetected with state-of-the-art tests. The
applications. Hence the purpose of test generation has been to
production test results have shown that the CA tests detect various
failing parts during a first wafer sort test which still resulted into
create a set of test patterns that detect as many manufacturing
unique failing parts after a second wafer sort test done at a
defects as possible.
different temperature and with additional tests. The obtained results First production test results for a 32nm technology have
encouraged us to continue this work beyond this paper to run been presented in [12] and [14]. In this paper we now focus on
further experiments with the final goal to eliminate the stuck-at a full application of the CA methodology, which includes slow-
(SA) and transition delay (TR) test by simultaneously improving the speed and at-speed CA tests for bridges and opens as well as
quality with CA tests which are a superset of SA and TR tests. transistor defects for a mature 130nm automotive technology.
1 INTRODUCTION Production test results from multimillion tested ICs of a high
quality automotive design and test flow are shown. Also
Todays demands for high quality automotive devices are included is an extensive outlook to the next steps with the final
extremely challenging. Higher performance of the integrated target to eliminate the state-of-the-art SA and TR tests by
circuit has to be combined with higher density on chip and applying CA tests to all automotive ICs, with the clear goal of
Zero-PPM fail rates. This can be managed only if all possible improving the quality and carefully reducing the test costs. A
defects in an integrated design can be addressed. Such physical physical failure analysis (PFA) needs to be done to check if the
defects can be shorts and opens external to library cells, but CA tests really find field quality relevant defects. In the
also inside of library cells, e.g. defects like leaking and following sections of the paper the potential defects found by
resistive transistors. One accepted method to deal with these the CA tests are called CA defects to differentiate from the
kinds of defects is fault-modeling. Such models can be used to field quality.
describe a specific faulty behavior in a sophisticated model.
2 VALIDATION FLOW 130NM DESIGN
This has been done since decades using well-known fault-
models like stuck-at [1], gate- and transition-delay [2], bridge- The investigation as shown in Fig. 1 incorporates the
[3] and gate-exhaustive [4] models as well as N-detect [5] and comparison of the CA with the traditional SA model and the
embedded-multi-detect [6] methods. In addition, as well TR fault model for an industrial design in a 130nm technology.
timing-aware [7] and layout-aware [8] fault modeling is state- The validation flow starts with the generation of state-of-
of-the-art. All of those models cover design structures like the-art SA and TR patterns. The second step in the flow is the
metal lines and interconnects between standard cells in an verification of the SA and TR patterns with respect to the CA
integrated circuit design. None of the mentioned fault models fault model. This evaluation is accomplished by a fault-
cover CI defects explicitly.
simulation of the SA and TR patterns considering the CI
One approach to deal with CI defects is the CA defects. The third step is the generation of the CA patterns
methodology [9], [10], [13]. Numerous publications about the which do achieve the highest possible defect coverage also
CA approach showed that the classical SA, TR, N-detect (ND) detecting all CI defects. As described in [14], a library
and gate-exhaustive (GE) approaches [11] do not target all real characterization is performed in advance once per technology
defects inside library cells or are too expensive for production node to create the needed CA view for each cell of the standard
tests. library. The results of this library characterization for the
130nm technology used in this design are presented in the
An overview of the latest state-of-the-art of the CA following two sub-chapters.
methodology was given in [14]. The tutorial covered the whole
As listed in Fig. 8 there are seven CA defects (named D1 to The device contains an 8 bit C, Flash, SRAMs, Boot-
D7) that are not covered with state-of-the-art SA and TR ROM, on-chip OSC and PLL. Mixed signal components like
patterns, even not when CI faults are considered on a full gate multiple SAR ADCs / DACs are included as well. In addition
level description for the full adder cell. Fig. 9 shows these to the digital / mixed signal parts, a large power part is included
seven defects in the layout of the full-adder cell SFA1 which contains Low Side and High Side switches, a LIN
transceiver and High Voltage Monitor inputs. What is very
typical for those devices are the multiple on-chip voltage
regulators which take care on the internal voltage supplies.
Therefore, just a supply connection to the car battery is needed.
3.1 Experimental Test Flow
To investigate the effectiveness of the CA patterns in
relation to traditional SA, TR, IDDQ patterns and automotive-
specific Other Tests (OT1, OT2), we added the experimental
CA patterns to the test program and changed the test flow to
log unique CA fails as shown in Fig. 11 and Fig. 12.
As can be seen, the 1,200 additional CA1 slow-speed test Fig. 15. CA Failing Parts from Wafersort2
patterns increase the scan volume by 43% compared to the
existing SA production patterns. The quantity of the CA2 at-
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