An Improved Transformerless Grid Connected Photovoltaic
Inverter with Common Mode Leakage Current Elimination
Monirul Islam*, Saad Mekhilef*, Fadi M. Albatsh*
*Power Electronics and Renewable Energy Research Laboratory (PEARL), Department of Electrical Engineering, Faculty of
Engineering, University of Malaya, Kuala Lumpur, 50603 Malaysia. E-mail: monir04eee@yahoo.com;
saad@um.edu.my; fbatsh83@yahoo.com
Keywords: Common Mode Voltage; Converter; Grid
connected; Junction Capacitance; Leakage Current; PV;
Transformerless.
Abstract
Transformerless PV inverters are most preferred for grid
connected photovoltaic (PV) generation system due to higher
efficiency and lower cost. However, to meet the safety
regulations, the leakage current, which deteriorates the power
quality and generates EMI of transformerless PV inverter,
have to be addressed carefully. In order to eliminate the
leakage current, an improved topology based on H5 topology
is proposed in this paper. The operation principle, common
mode (CM) characteristics, and the impact of junction
capacitance of the switches are analyzed in detail. Three-level
output voltage has been achieved in the proposed improved
inverter by implementing unipolar SPWM with wide input
voltage range. Furthermore, the European Union (EU)
efficiency is improved by replacing the IGBTs with
MOSFETs. The proposed improved inverter topology has
been simulated by MATLAB/Simulink software to validate
the accuracy of the theoretical explanations. Finally, a 1kw
prototype has been built and tested. Experimental results
show 98.2% maximum efficiency and 97.76% EU efficiency
on the 1kw prototype circuit with 16 kHz switching
frequency.
1. Introduction
Energy crisis is one of the most crucial problems in recent
time and renewable-energy sources play an important role in
the attempt to address these problems. Among the renewable-
energy sources, the photovoltaic (PVs) is one of the most up-
to-date techniques and third (after hydro and wind power)
most important renewable-energy sources in terms of globally
installed capacity. Based on the newest report on installed PV
power, the milestone of 100GW PV system was achieved at
the end of 2012, and the majority were grid-connected [1, 2].
A single-phase converter is used in low power grid-connected
applications, but its design embeds generally a line-frequency
transformer or a high-frequency transformer that adjusts the
converter dc voltage and separates the PV arrays from the
grid [3, 4]. Because of size, weight and price in favour of
high-frequency transformers, the aptitude is to remove the
line frequency transformers when designing the new
converter. Furthermore, the existence of the high-frequency
1
transformer desires several power stages, as a result, reducing
cost and increasing efficiency will be a challenging task [5].
Consequently, the transformerless grid connected PV
inverters are manifested to offer the benefits of lower cost,
higher efficiency, smaller size, and weight. However, a
galvanic connection is existed between the power grid and the
PV module due to the omission of transformer. Therefore,
fluctuating CM voltage is generated between the PV module
and the ground, as a result, leakage current flows through the
loop consisting of the parasitic capacitors, the filter inductors,
the bridge, and the utility grid [6-8]. This CM leakage current
increases the grid current harmonics and system losses and
also creates a strong conducted and radiated electromagnetic
interference. Consequently, if anyone touches the PV module
who is connected to the ground will be conducted by the
capacitive current [9-11].
Many topologies have been investigated to minimize the CM
leakage current and improve the efficiency of the
transformerless grid-connected PV inverters, which can be
separated into two groups: (1) half-bridge inverter topology,
(2) full-bridge inverter topology. The half-bridge inverter
topology eliminates the fluctuating CM voltage and produces
almost zero leakage current. The main drawback of the half-
bridge topology is the necessity of high input voltage
(700VDC) corresponds to 230VAC application [12]. On the
other hand, in the full-bridge inverter, this required input
voltage is only 350 VDC for the same application. But the
main disadvantage of the full-bridge inverter is that it can
employ only bipolar sinusoidal pulse width modulation
(SPWM) with two-level output. Consequently, high ripples in
the output current are produced and the efficiency of the
entire system is decreased. To overcome these problems,
many advanced topologies have been proposed in the
literature [13-21] shown in Fig. 1, which are based on the
full-bridge topology. These topologies can achieve three-level
output voltage by employing the unipolar SPWM and also
can keep constant CM voltage during all operational modes.
The main two issues for the transformerless PV inverter are;
(1) the inverter should not have any leakage current and (2)
achieve higher efficiency over wide load ranges. In order to
obtain these two main issues, an improved single phase
transformerless grid-tied PV inverter topology is proposed in
this paper. The main features of the proposed improved
inverter are: (1) the efficiency of the inverter is improved by
replacing the IGBTs with MOSFETs because of low
conduction and switching losses of the supper MOSFETs (2)
analysis of the influence of switches junction capacitance
 P P P
LA
S5
S1 S2 S1 S3 S1 S3
LA Cdc1 D7 LA
A S5
A A
Vpv PV Cdc Vg Vpv PV Cdc Co Vg Co Vg
B Vpv PV
B D8 B
S6 Cdc2
LB S3 S2 S4 S2 S4 LB
D1 D2 S4
S6
N N LB
N
(a) (b)
(c)

P
S1 P
S3 P
LA S5 S5
S1 S3 S1 S3
S5 LA Cdc1 LA
A A S6 A
Vpv Cdc1 Co Vg Vpv
PV PV Cdc Co Vg Co Vg
B Vpv PV
S6 B B
LB Cdc2 LB
LB S2 S4 S2 S4
S4
S2
N N N

(d) (e) (f)

Fig. 1. Some existing transformer-less topologies for grid-tied PV inverter (a) Topology proposed in [15] (b) HERIC topology
proposed in [19] (c) H6 topology proposed in [18] (d) Topology proposed in [20] (e) H5 topology proposed in [17] (f) oH5
topology proposed in [13]

and disconnection of PV module from the grid at the

freewheeling mode ensure minimized ground leakage current, P
S5
(3) dead time is not required at both high-frequency switching S1 S3
LA
commutation and grid zero-crossing instant which improves
A
the output power quality and increases the efficiency. The Vpv PV Cdc Co Vg
efficiency of the improved inverter topology, H6 topology B
and HERIC topology are measured and compared. S2 S4 LB

This paper is prepared as follows: The proposed improved

N
converter structure and operation principle with the unipolar
SPWM control scheme is investigated in section 2. The (a)
impact of switches junction capacitance is discussed in
section 3. Experimental and simulation results are presented
in section 4, and section 5 concludes the paper.

2. Improved inverter topology and modulation

2.1 Structure of the converter
In order to de-couple the converter from the grid in the
freewheeling mode, an extra MOSFET switch is added into
the conventional full H-Bridge topology and the two lower
high frequency IGBT switches of two phase legs are replaced
by MOSFET switches in this paper which is shown in Fig.
2(a). LA, LB, and Co constructs the LCL type filter, coupled to
the grid. This improved topology can achieve the three-level
output voltage with unipolar SPWM.
2.2 Operation principle analysis
Grid-tied photovoltaic system generally operates at unity
power factor. Fig. 2(b) shows the waveform of the gating
signals of the improved inverter. The additional switch S5
commutates at the switching frequency to ensure the dc de-
coupling states. In the positive half-cycle of grid current, S1 is
always on and S4 & S5 commutate at the switching frequency
with the identical commutation order to create +V dc and zero
(b)
Fig. 2. Improved transformerless grid-tied PV inverter (a)
proposed circuit configuration (b) gating signals with unity
power factor.
state. Likewise, in the negative half-cycle, S3 is always on
and S2 & S5 commutate at the switching frequency. The
freewheeling current flows through S1 and body diode of S3
in the positive half-cycle while S3 and body diode of S1 in in
the negative half-cycle. Consequently, four operational modes
are proposed that produce the output voltage states of +Vdc, 0,
and -Vdc. Fig. 3 shows the operational principles of the
proposed inverter.

2
 (a) (b)
P
S5
P
S5 S5
P
S1 S3
LA S1 S3 ic5 i1 ic3
LA
A C5
Vpv PV Cdc Co Vg Vpv
A C1 S1 C3 S3
PV Cdc Co Vg
B i3 LA
B
LB
S2 S4 S2 LB Vdc
S4 ic2
N
N ic4 i3 LB
C2 S2 C4 S4
ic5
(c) (d)
N
P P CPV i2
S5 S5
S1 S3 S1 S3
LA LA (a)
A A
Vpv PV Cdc Co Vg Vpv PV Cdc Co Vg C3
B B (Vdc) ic5 (Vdc) ic3
LB LB
S2 S4 S2 S4
C5
i1 ic3
N N
i3
LA LB (0) ic4
Fig. 3. Equivalent circuit of four operational modes; (a) ic2
Active and (b) freewheeling modes in the positive half cycle C2 C4
of grid current; (c) Active and (d) freewheeling modes in the
negative half cycle of grid current. i2 (b)

Fig. 4. Transient circuit by considering the switching from

Mode I: When S4 and S5 are turned-on, the inductor current mode I to mode II (a) Transient circuit (b) Simplified circuit
iL, flowing through S1, S4 and S5, is increased. In this mode,
VAB = +Vdc and the CM voltage is
VPV 3. Impact of junction capacitance
Vcm
1

V V
2 AN BN   1
V 0
2 PV  2
(1)
When the inverter commutates from each non-decoupling
state to decoupling state, the slope of voltage V AN and VBN
Mode II: Fig. 3(b) shows the freewheeling path when S4
depends on the junction capacitance of the switches. As a
and S5 are turned-off. In this mode, VAN falls and VBN rises
until their values are equal. Therefore, VAB = 0 and the result, the CM voltage is affected. The aforesaid four
inductor current decreases through S1 and the body diode of operational modes can be divided into two groups based on
S3. So the CM voltages can be defined as the decoupling and non-decoupling states.
In the active mode (mode I and mode III), the PV module and
1 VPV VPV VPV
Vcm
1

V V
2 AN BN  2 2

2 2
(2) the grid are directly coupled by the output filter inductors.
Therefore, the effect of switches junction capacitance on the

CM voltage is insignificant in this mode. But in the
Mode III: This mode starts when S2 and S5 are turned-on freewheeling mode (mode II and mode IV), the PV module is
and the inductor current increases reversely through S2, S3 disconnected from the grid by the additional switch S5 and the
and S5. Therefore, the output voltage VAB = -VPV and the CM CM voltage is influenced by the switches junction
voltage becomes capacitance. The complexity of eliminating leakage current is
increased, when the switches junction capacitance is taken
VPV
Vcm
1

V V
2 AN BN  12 0 V  PV 2
(3) into consider.
There are always two phases when the inverter commutates
Mode IV: In the negative half-cycle of grid current, free- from each non-decoupling state to decoupling state (from
wheeling mode starts when S2 and S5 are turned-off which is mode I to mode II as an example) because of the symmetry of
shown in Fig. 3(d). In this mode, VBN falls and VAN rises until the operation modes.
their values are equal. Therefore, VAB = 0 and the inductor
Phase I: An equivalent transient circuit can be drawn by
current decreases through S3 and the body diode of S1, like as
considering the commutation from mode I to mode II as
mode 2. The CM voltage is calculated as
shown in Fig. 4, where C1-C5 symbolizes the junction
1 VPV VPV VPV capacitors of the switches S1-S5. The transient charging or
Vcm
1

V V
2 AN BN  2 2

2 2
(4)
discharging circuits are drawn up by the junction capacitors
C2, C3, C4, and C5, when the switches S4 and S5 are turned-
It is clear that, during the aforementioned four commutation off but the body diode of S3 has not conducted to flow the
modes, Vcm almost remains at constant value that is Vcm = freewheeling current. The following equations are given by
1/2VPV [from (1) (4)]. Therefore, the improved inverter can applying Kirchhoffs current law
keep constant CM voltage during all operational modes with
unipolar SPWM. i i i (5)
1 c3 c5

3
 (Vdc) ic5
C2+C5
C5 Vdc
C2+C4+C5

(0)
ic2 i6 LA LB

C2
ic4

C4 CPV i6

Fig. 5. Simplified equivalent resonant circuit in mode II

(a)

i2 ic4 ic2  ic5 (6)

i3 ic2  ic3  ic5 (7)

where i1, i2, and i3 are the charging or discharging current of

the circuit and ic2, ic3, ic4, and ic5 are respectively the current
of C2, C3, C4 and C5. 160V

The equivalent circuit model for the transient state is given in

Fig. 4(b), where the primary voltages are shown in the
bracket. In Fig. 4(b), it is explicit that C4 is charged by C2
and C5 in parallel through the output filter inductors L A and
LB. Therefore, the voltage across C4 will increase and the
voltage across C2 will decrease until their values are equal.
According to the charge conversion theory, it is found that
C 2  C5 (8)
VAN VBN VPV
C 2  C 4  C5
Phase II: In the meantime, the body diode of S3 conducts to
freewheel and the transient state is ended. According to
equation (8), the equivalent resonant circuit is drawn in Fig.
5. The voltage VAN and VBN will be equal to VPV/2 only if C4
= C2+C5 at the end of transient state. Therefore, the CM
voltage will remain constant in mode II.
On the other hand, at the end of transient state, if C4 C2+C5
the voltage VAN, VBN and Vcm will not be equal to VPV/2. So
the condition of eliminating CM leakage current will be
broken. As a result, a high-frequency leakage current will
flow through the junction capacitors, the parasitic capacitors
and the filter inductors as shown in Fig. 5.
In the proposed unipolar SPWM inverter, there are always
two commutations from one of the non-decoupling modes to
one of the decoupling modes. When the inverter commutates
to mode IV from mode III, we can analyze same as before
and finally summarized the following equations to get V AN =
VBN = VPV/2 when the transient state is ended.
1) Commutation from mode I to mode II: C4=C2+C5
2) Commutation from mode III to mode IV: C2=C4+C5
Therefore, the condition of junction capacitor for eliminating
CM leakage current is concluded that C5=0 and C2=C4. But
for practical application, the junction capacitance of the
switches cannot be zero. Accordingly, the theoretical value is
amended for practical application as follows
C2 = C4 >> C5
(b)
Fig. 6. Waveforms of VAN, VBN, and Vcm by applying unipolar
SPWM when the switches junction capacitances are identical
(a) Simulated waveform (b) Experimental waveform
4. Simulation and experimental results
In order to verify the performance of the proposed improved
topology, a 1kWp PV array is simulated by using
MATLAB/Simulink software, having the frame of panels
connected to the ground with the parasitic capacitance of
75nF. Also, a 1 kW prototype has been built in our laboratory.
The specifications of the prototype are listed in Table 1.
The waveforms of VAN, VBN, and Vcm are shown in Fig. 6
when the switches junction capacitances are identical. The
condition of junction capacitance narrated in equation (9) for
eliminating the CM voltage is not fulfilled here, so the CM
voltage fluctuation is relatively large as shown in Fig. 6. The
simulated waveform shows the results V AN = VBN = 130V at
the end of transient state for each commutation of non-
decoupling modes to decoupling modes, and as a result, the
CM voltage is fluctuating from 130V to 200V. The
experimental results are similar to the simulated results which
are shown in Fig. 6(b).
Therefore, to verify the analysis proved in equation (9), two
additional capacitors whose values are much greater than the
junction capacitance of S5, are connected in parallel to S2 and
S4, respectively. Depending on two constraints, first,
increasing switching losses and second, minimization of CM
leakage current, additional capacitors value is selected as
5000pF. As a result, the simulation results presented in Fig.
7(a) shows the voltages VAN = VBN = 200V at the end of the
transient period. Consequently, CM voltage remains constant
(9) at 200V and the generating ground leakage current is

4
 ig(10A/div)

t=5ms/div

(a) Fig. 8. Experimental waveforms of grid current ig, grid voltage

Vg, and leakage current iLeakage.

(b)

Fig. 7. Waveforms of VAN, VBN, and Vcm after adding two

additional capacitors (a) Simulated waveform (b) Fig. 9. Experimental waveforms of grid current ig, grid voltage
Experimental waveform Vg, and differential voltage VAB.

minimized to safe level, since VAN and VBN are fully

complementary in the switching periods. The experimental
results are completely matched with simulation results which
are shown in Fig. 7(b). The measured peak value and RMS
value of CM leakage current are less than 40mA and 10mA
respectively as shown in Fig. 8, even though the practical
switches junction capacitances are non-linear and
challenging to be matched accurately. This peak and RMS
values are lower in magnitude corresponding to the German
standard VDE0126-1-1.
Fig. 10. Efficiency comparison curve
In Fig. 9, the inverter output voltage VAB has three levels as
Vdc, 0, -Vdc. It indicates that the proposed topology employs Table 1
unipolar SPWM with galvanic isolation and the differential Specifications of the prototype
mode characteristic is excellent. The grid-connected current Inverter Parameter Value
and voltage, shown in Fig. 9, shows that the proposed inverter Nominal Input Voltage 400VDC
can inject power to the grid with higher power factor and Grid Voltage / frequency 240V / 50Hz
lower harmonic distortion. Rated Power 1000 W
Nominal AC current 4.2A
The efficiency comparison curve among the proposed, H6 Switching Frequency 16kHz
and HERIC topologies with the same condition are illustrated DC bus capacitor 470F
in Fig. 10, which are measured by the fluke 1735 power Filter capacitor 2.2F
Filter Inductor LA, LB 3mH
logger from Fluke Corporation. It is clear that the efficiency PV parasitic capacitor Cpv1, Cpv2 75nF
of the proposed topology is higher than the H6 topology and
almost same to the HERIC topology. The maximum
efficiency of the proposed inverter is measured 98.2%. The 5 Conclusion
European Union (EU) efficiency of the proposed, H6 and
HERIC topologies are 97.76, 97.5, and 97.87 respectively, In this paper, an improved inverter topology based on the H5
which are calculated in equation (10). topology is presented to reduce the CM leakage current. The
operation modes of the topology and the impact of junction
KEU 0.03K5%  0.06K10%  0.13K20%  0.10K30%  0.48K50%  0.2K100% (10) capacitance of the switches are analyzed in details, which

5
ensure not to produce the CM leakage current because the
condition of eliminating leakage current is met completely.
Moreover, the three-level output voltage by employing
unipolar SPWM is achieved in the proposed inverter with
excellent differential mode characteristics. No dead time is
required at both the PWM commutation and the zero crossing
instant of grid cycle. Consequently, the higher quality and
lower THD of the grid-connected current are obtained. The
efficiency of the inverter is measured and compared with the
conventional H6 and HERIC topologies. The EU efficiency is
improved by replacing IGBTs with MOSFETs. The
maximum efficiency and EU efficiency of the proposed
inverter are measured 98.2% and 97.8%, respectively.
Therefore, the proposed inverter is very suitable for grid-
connected PV system.
Acknowledgements
The authors wish to acknowledge the financial support from
the University of Malaya through HIR-MOHE project
UM.C/HIR/MOHE/ENG/24 and UMRG project RP015A-
13AET.
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