FETCH CYCLE
T1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T3 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EXECUTION CYCLES
LDA
T4 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
STA
T4 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
JMP
T4 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ADD
T4 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0
SUB
T4 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1
INC
T4 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DEC
T4 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AND
T4 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 1
OR
T4 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 0
XOR
T4 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 0 1
NOT
T4 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
SHL
T4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
SHR
T4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ROR
T4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ROL
T4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CLA
T4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IN
T4 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
OUT
T4 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
T5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EXECUTION CYCLES
LDA
Cycle Hexadecimal
T4 EDFFFF
T5 F6FFFF
T6 FFFFFF
STA
Cycle Hexadecimal
T4 EDFFFF
T5 FF7F7F
T6 FFFFFF
JMP
Cycle Hexadecimal
T4 FDFEFF
T5 FFFFFF
T6 FFFFFF
ADD
Cycle Hexadecimal
T4 EDFFFF
T5 F7EFFF
T6 FEDBFE
SUB
Cycle Hexadecimal
T4 EDFFFF
T5 F7EFFF
T6 FE9BFD
INC
Cycle Hexadecimal
T4 FE9FFF
T5 FFFFFF
T6 FFFFFF
DEC
Cycle Hexadecimal
T4 FEDFFC
T5 FFFFFF
T6 FFFFFF
AND
Cycle Hexadecimal
T4 EDFFFF
T5 F7EFFF
T6 FEDBFB
OR
Cycle Hexadecimal
T4 EDFFFF
T5 F7EFFF
T6 FEDBFA
XOR
Cycle Hexadecimal
T4 EDFFFF
T5 F7EFFF
T6 FEDBF9
NOT
Cycle Hexadecimal
T4 FEDFF8
T5 FFFFFF
T6 FFFFFF
SHL
Cycle Hexadecimal
T4 FFFFBF
T5 FFFFFF
T6 FFFFFF
SHR
Cycle Hexadecimal
T4 FFFFDF
T5 FFFFFF
T6 FFFFFF
ROR
Cycle Hexadecimal
T4 FFFFF7
T5 FFFFFF
T6 FFFFFF
ROL
Cycle Hexadecimal
T4 FFFFEF
T5 FFFFFF
T6 FFFFFF
CLA
Cycle Hexadecimal
T4 7FFFFF
T5 FFFFFF
T6 FFFFFF
IN
Cycle Hexadecimal
T4 FEFDFF
T5 FFFFFF
T6 FFFFFF
OUT
Cycle Hexadecimal
T4 FEF7FF
T5 FFFFFF
T6 FFFFFF
AROM VALUES
COMMANDS ADDRESS/LOCATION VALUE(BINARY) VALUE(HEXA)
LDA 00000 000011 3
STA 00001 000110 6
JMP 00010 001001 9
ADD 00011 001011 11
SUB 00100 001110 14
INC 00101 010001 17
DEC 00110 010011 19
AND 00111 010101 21
OR 01000 011000 24
XOR 01001 011011 27
NOT 01010 011110 30
SHL 01011 100000 32
SHR 01100 100010 34
ROR 01101 100100 36
ROL 01110 100110 38
CLA 01111 101000 40
INPUT 10000 101010 42
OUTPUT 10001 101100 44
HALT 10010 111111 63