PHY-204 Lab Manual

Indian Institute of Science Education and Research Bhopal
Physics Laboratory Manual

PHY-204 (Electronics Lab.)
UG Physics Laboratory, I Floor Academic Building - III,
IISER Bhopal, Bhopal By-Pass Road, Bhauri, Bhopal, 462 066, M.P.
Content
1. CE (NPN) Transistor Characteristics and Amplifier
2. Clippers and Clampers
3. Digital to Analog and Analog to Digital Convertor
4. FET Characteristics
5. Logic Gates/ Binary Adder and Subtractor
6. Multiplexer/Demultiplexer
7. Operational Amplifier (Integrator/Differentiator)&

(Inverting/Noninverting)
8. P-N Junction Diode, Zener Diode and Light Emitting

Diode
Experiment No. 01 (A)
AB04 Common Emitter NPN Transistor Characteristics
Theory
Transistor characteristics are the curves, which represent relationship between
different DC currents and voltages of a transistor. These are helpful in studying the
operation of a transistor when connected in a circuit. The three important
characteristics of a transistor are:
1. Input characteristic.
2. Output characteristic.
3. Constant current transfer characteristic.
Input Characteristic :
In common emitter configuration, it is the curve plotted between the input current (IB)
verses input voltage (VBE) for various constant values of output voltage (VCE).
The approximated plot for input characteristic is shown in figure 1. This characteristic
reveal that for fixed value of output voltage VCE, as the base to emitter voltage
increases, the emitter current increases in a manner that closely resembles the diode
characteristics.
Figure 1
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AB04
Output Characteristic :
This is the curve plotted between the output current IC verses output voltage VCE for
various constant values of input current IB.
The output characteristic has three basic region of interest as indicated in figure 2 the
active region, cutoff region and saturation region.
In active region the collector base junction is reverse biased while the base emitter
junction if forward biased. This region is normally employed for linear (undistorted)
amplifier.
In cutoff region the collector base junction and base emitter junction of the transistor
both are reverse biased. In this region transistor acts as an Off switch.
In saturation region the collector base junction and base emitter junction of the
transistor both are forward biased. In this region transistor acts as an on switch.
Figure 2
Constant current transfer Characteristics :
This is the curve plotted between output collector current IC versus input base current
IB for constant value of output voltage VCE.
The approximated plot for this characteristic is shown in figure 3.
Figure 3
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AB04
Experiment
Objective :
Study of the characteristics of NPN transistor in common emitter configuration
and to evaluate :
1. Input resistance
2. Output resistance
3. Current gain
Equipments Needed :
1. Analog board of AB04.
2. DC power supplies +12V, +5V from external source or ST2612 Analog Lab.
3. Digital Multimeter (3 numbers).
4. 2 mm patch cords.
Circuit diagram :
Circuit used to plot different characteristics of transistor is shown in figure 4.
Figure 4
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AB04
Procedure :
Connect +5V and +12V DC power supplies at their indicated position from
external source or ST2612 Analog Lab.
To plot input characteristics proceed as follows :
1. Rotate both the potentiometer P1 and P2 fully in CCW (counter clockwise
direction).
2. Connect Ammeter between test point 2 and 3 to measure input base current
IB(A).
3. Short or connect a 2mm patch cord between test point 4 and 5.
4. Connect one voltmeter between test point 1 and ground to measure input voltage
VBE other voltmeter between test point 6 and ground to measure output voltage
VCE.
5. Switch On the power supply.
6. Vary potentiometer P2 and set a value of output voltage VCE at some constant
value (1V, 3V...)
7. Vary the potentiometer P1 so as to increase the value of input voltage VBE from
zero to 0.8V in step and measure the corresponding values of input current IB for
different constant value of output voltage VCE in an observation Table 1.
8. Rotate potentiometer P1 fully in CCW direction.
9. Repeat the procedure from step 6 for different sets of output voltage VCE.
10. Plot a curve between input voltage VBE and input current IB as shown in figure 1
using suitable scale with the help of Observation Table l. This curve is the
required input characteristic.
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AB04
Observation Table 1 :
Input Input current IB(A) at constant value of

S. no. voltage output voltage
VBE
VCE = 1V VCE = 3V VCE =5V
1. 0.0V
2. 0.1V
3. 0.2V
4. 0.3V
5. 0.4V
6. 0.5V
7. 0.6V
8. 0.7V
9. 0.8V
To plot output characteristics proceed as follows:

1. Switch Off the power supply.
direction).
3. Connect voltmeter between test point 6 and ground to measure output voltage
VCE.
4. Connect one Ammeter between test point 2 and 3 to measure input current
IB(A) and other Ammeter between test point 4 and 5 to measure output current
IC(mA).
6. Vary potentiometer P1 and set a value of input current IB at some constant value
(0A, 10A......100A)
7. Vary the potentiometer P2 so as to increase the value of output voltage VCE from
zero to maximum value in step and measure the corresponding values of output
current IC for different constant value of input current IB in an observation
table2.
8. Rotate potentiometer P2 fully in CCW direction.
9. Repeat the procedure from step 6 for different sets of input current IB.
10. Plot a curve between output voltage VCE and output current IC as shown in
figure 2 using suitable scale with the help of Observation Table 2. This curve is
the required output characteristic.
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AB04
Output Output current IC (mA) at constant value of

S. input current
voltage
No.
VCE
IB = 0A IB =10A IB =20A IB =30A IB =40A
1. 0.0V
2. 0.5V
3. 1.0V
4. 2.0V
5. 3.0V
6. 4.0V
7. 5.0V
8. 6.0V
9. 7.0V
10. 8.0V
To plot constant current transfer characteristics proceed as follows:

direction).
VCE.
4. Connect one Ammeter between test point 2 and 3 to measure input current IB
(mA) and other Ammeter between test point 4 and 5 to measure output current
IC (mA).
6. Vary potentiometer P2 and set a value of output voltage VCE at maximum value.
7. Vary the potentiometer P1 so as to increase the value of input current IB from
zero to 10mA in step and measure the corresponding values of output current IC
in an Observation Table 3.
8. Plot a curve between output current IC and input current IB as shown in figure 3
using suitable scale with the help of observation Table 3. This curve is the
required Transfer characteristic.
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AB04
Input
Output Current Ic (Ma) At Constant Output
S. No. current
Voltage Vce = Maximum
IB (A)
1. 00.0A
2. 10.0A
3. 20.0A
4. 30.0A
5. 40.0A
6. 50.0A
7. 60.0A
8. 70.0A
9. 80.0A
10. 90.0A
11. 100.0A
7
AB04
Calculations :
1. Input resistance : It is the ratio of change in the input voltage VBE to change in
the input current IB at constant value of output voltage VCE or it is the reciprocal
of the slope obtained from the input characteristic.
Mathematically :
1 1 VBE
RIn = =
Slope from Input charecteristics IB/VBE IB at constant VCB
To calculate input resistance determine the slope from the input characteristic
curve obtained from observation Table 1. Reciprocal of this slope will give the
required input resistance.
2. Output resistance : It is the ratio of change in the output voltage VCE to change
in the output current IC at constant value of input current IB or it is the reciprocal
of the slope obtained from the output characteristic.
Mathematically :
1 1 VCE
RIn = =
Slope from Input charecteristics IC/VCE IC at constant IB
To calculate output resistance determine the slope from the output characteristic
curve obtained from observation Table 2. Reciprocal of this slope will give the
required output resistance.
3. Current gain : It is the ratio of change in the output current IC to change in the
input current IB at constant value of output voltage VCE or it is the slope
obtained from the constant current transfer characteristic. It is denoted by ac
Mathematically :
ac = Slope of constant current transfer characteristic = IC
IB
To calculate current gain, determine the slope from the constant current transfer
characteristic curve obtained from observation Table 3. This slope is the required
current gain.
Results :
Input resistance Rin = ___________
Output resistance Rout ________ =
Current Gain ac = ___________
8
AB04
Data Sheet
9
AB04
10
Experiment No. 01(B)
AB15 Common Emitter Amplifier
Theory
Amplification is the process of increasing the strength of signal. An Amplifier is a
device that provides amplification (the increase in current, voltage or power of signal)
without appreciably altering the original signal.
Bipolar transistors are frequently used as amplifiers. A bipolar transistor is a current
amplifier, having three terminals Emitter, Base, Collector. A small current into base
controls a large current flow from the collector to emitter. The large current flow is
independent of voltage across the transistor from collector to emitter this makes it
possible to obtain a large amplification of voltage by taking the output voltage from a
resistor in series with the collector.
Transistor can be used as an Amplifier in three configurations:
1. Common Base
2. Common Emitter
3. Common Collector
Common Emitter Configuration :
In this arrangement, the input signal is applied between base and emitter and the
output is taken from the collector to emitter shown in figure 1.
Figure 1
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AB15
Transistor as an Amplifier in CE Configuration :

The conditions for which transistor works as an amplifier are:
1. Emitter Base junction is always forward biased.
2. Collector Base junction is always reverse biased.
To achieve this, a DC voltage VBB is applied in the input circuit in addition to signal
shown in figure 1. This voltage is known as bias voltage and its magnitude is such
that it always keeps the input circuit forward biased regardless the polarity of signal.
A input circuit has low resistance, therefore a small change in signal voltage causes a
appreciable change in emitter current, this causes almost same change in collector
current due to transistor action. The collector current is flowing through high load
resistance Rc produces a large voltage across it, thus a weak signal applied in the
input circuit appears in the amplified form in collector circuit.
Current relations in CE configurations
IE = IC + IB
IC = IE +ICEO
IC= IB
Where,
IC = Collector current
ICEO = current through collector to emitter when base is open.
= common emitter DC current gain. ranges between 20 - 300.
Voltage Gain :
The ratio of Output Voltage (VO) to the Input Voltage (Vi) is known as voltage
amplification or voltage gain of amplifier.
Voltage Gain (AV) = VO / Vi
Operation of Common Emitter amplifier :
In order to get faithful amplification, the transistor is properly DC biased. The
purpose of DC biasing is to obtain a certain DC collector current (IC) at a certain DC
collector voltage (VCE). These values of current and voltage are called operating point
(Quiescent point). To obtain DC operating point some biasing methods are used
called biasing circuits. These biasing arrangements should be such as to operate the
transistor in Active region.
The Most commonly used Biasing circuits is voltage divider method. In this method
two resistances R1 and R2 are connected across the supply voltage VCC and provide
proper biasing. A voltage divider formed by R1 and R2, and the voltage drop across R2
forward biased the base emitter junction this causes the base current and hence
collector current flows in zero signal condition. Resistance RE provides stabilization.
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AB15
Figure 2
Rth : = R1 R2
R1 + R2
Vth : = VCC + R2
R1 + R2
VTH = VBE + VE
VTH = VBE + IERE
IE = (VTH VBE) / RE
IE is approximately equal to IC.
IC = (V2 VBE) / RE
VCE = VCC IC (RC + RE)
This method is widely used because operating point of transistor can be made almost
independent of beta () and provides good stabilization of operating point.
If this circuit is used to amplify AC voltages, some more components must be added
to it.
Coupling Capacitors (C1) :
They are used to pass AC input signal and block the DC voltage from the preceding
circuit. This prevents DC in the circuitry on the left of coupling capacitor from
affecting the bias on transistor. The coupling capacitor also blocks the bias of
transistor from reaching the input signal source. It is also called blocking capacitor.
Bypass Capacitors (C3) :
It bypasses all the AC current from the emitter to the ground. If the capacitor CE is not
put in the circuit, the AC voltage developed across RE will affect the input AC
voltage, such a feedback is reduced by putting the capacitor C3.
13
AB15
Load Resistance (RO) :

It represents the load resistance is connected at the output.
The input to the amplifier is a sine wave that varies a few millivolts. It is introduced
into the circuit by the coupling capacitor and is applied between the base and emitter
with proper biasing circuit. As the input signal goes positive, the voltage across the
emitter-base junction becomes more positive. This in effect increases forward bias,
which causes base current to increase at the same rate as that of the input sine wave.
Emitter and Collector currents also increase but much more than the base current.
With an increase in collector current, more voltage is developed across RC. Since the
voltage across RC and the voltage across transistor (collector to emitter) must add up
to VCC, an increase in voltage across RC results in an equal decrease in voltage across
transistor. Therefore, the output voltage from the amplifier, taken at the collector of
transistor with respect to the emitter, is a negative alternation of voltage that is larger
than the input, but has the same sine wave characteristics.
During the negative alternation of the input, the input signal opposes the forward bias.
This action decreases base current, which results in a decrease in both emitter and
collector currents. The decrease in current through RC decreases its voltage drop and
causes the voltage across the transistor to rise along with the output voltage.
Therefore, the output for the negative alternation of the input is a positive alternation
of voltage that is larger than the input but has the same sine wave characteristics.
By examining both input and output signals for one complete alternation of the input,
we can see that the output of the amplifier is an exact reproduction of the input except
for the reversal in polarity and the increased amplitude (a few millivolts as compared
to a few volts).
Figure 3
Input and Output Waveforms of Common Emitter Amplifier with load resistance 1
K.
14
AB15
Operating Parameters of Common Emitter Amplifier :

1. Voltage Gain :
It is the ratio of output voltage (Vout) obtained to input voltage (Vin).
Av = Vout / Vin
Figure 4
2. Input Impedance :
It is the ratio of Input Voltage (Vin) to Input Current (Ii).
Zin = Vin / Ii
To measure the input impedance a known resistor (Rs) is placed in series before the
input coupling capacitor and the impedance could be calculated using the equation.
Zin = Rs / (Av/Av-1)
Where,
Av = voltage gain without the resistor (Rs)
Av= voltage gain with the resistor (Rs)
3. Output Impedance :
It is the ratio of Output Voltage (Vout) to Output Current (Io).
Zout = Vout /Io
To measure the Output impedance a known resistor (Rs) is placed from output to
ground and the output impedance could be calculated using the equation.
Zout = (Av /Av-1) * Rs
Where,
Av = voltage gain without the resistor (Rs)
Av = voltage gain with the resistor (Rs)
4. Current Gain :
It is the ratio of Output current (Io) to Input current (Ii).
Ai = Io / Ii
The Current gain could be calculated using the equation
15
AB15
Ai = - Av * Zin / RL
Characteristics of Common Emitter Amplifier :
1. It produces phase reversal of input signal i.e., input and output signals are 180
out of phase with each other.
2. It has very high voltage gain.
3. It has moderately low input impedance.
4. It has moderately large output impedance.
5. It has high current gain ().
Type of Amplifier Circuit

Characteristic
Common Common Common
Base Emitter Collector
Phase reversal No Yes No
Voltage Gain High Highest Nearly Unity
Input Impedance Lowest Moderate Highest
Output Impedance Highest Moderate Lowest
Current Gain Nearly unity High () Highest (+ 1)
16
AB15
Experiment
Objective :
Study of the Common Emitter Amplifier and for evaluation of Operating Point,
Voltage Gain (AV), Input and Output Impedance, Current Gain of the Amplifier.
Equipments Needed :
2. DC power supplies +12V external source or ST2612 Analog Lab.
3. Digital Multimeter
Circuit diagram :
Figure 5
17
AB15
Procedure :
1. Connect Test point 2 and Test point 3, Test point 4 and Test point 5, Test point
6 and Test point 7, using 2mm patch cords.
2. Connect +12V DC power supply at their indicated position from external source
or ST2612 Analog Lab.
4. For the measurement of Quiescent Point measure the VCE by connecting
Voltmeter between Test point 4 and Test point 6. Measure Collector current (Ic)
by connecting Ammeter between Test point 4 and Test point 5.
5. Connect a sinusoidal signal of 10mV (p-p) at 25 KHz frequency at the Test
point 1 (Input of amplifier) from external source or ST2612 Analog Lab.
6. Observe the amplified output on oscilloscope by connecting Test point 8 (output
of amplifier) to Oscilloscope.
7. Calculate Voltage gain of amplifier. Connect Load resistor of 1 K ohms at the
output and find the voltage gain of amplifier with load resistor.
8. Calculate input impedance, output impedance, and current gain of amplifier
using the mentioned formulas with resistance 1 K Ohm
Result :
Operating Point of the Common emitter amplifier
IC = _________ mA VCE = ____________ V
Voltage gain of the amplifier AV __________ =
Input impedance of amplifier Zin _________ =
Output Impedance of amplifier Zout _______ =
Current gain of amplifier Ai = _____________
Voltage gain reduces as load resistance is connected to circuit.
18
AB15
Data Sheet
19
AB88 Diode Clippers
Theory
Clippers :
The circuit with which the waveform is shaped by removing (or clipping) a portion of
the applied wave is known as a clipping circuits. This kind of processing is useful for
signal shaping, circuit protection, radars, digital and other electronic systems. In other
words clippers have the ability to clip off a portion of the input signal without
distorting the remaining part of the incoming wave. The simplest form of clipping
circuits is Diode clippers. The basic of Diode clipper is one resistance and a diode.
These clippers can remove signal voltages above or below a specified level
.Depending on the orientation of the diode, clippers are classified as-
1. Positive clippers
2. Negative clippers
3. Combination clippers
There are two general categories of clippers-
1. Series clippers
2. Parallel clippers
Positive clippers :
A positive clipper is that which removes the positive half-cycles of the input voltage
figure 1 shows the circuit of positive clipper using a diode.
Figure 1
20
AB88
How the circuit works ?

During the positive half cycle, the diode turns on and looks like a short across the
output terminals .Ideally, the output voltage is zero. On the negative half cycle, the
diode is open. In that case, a negative cycle appears across the output. But practically
silicon diode takes 0.7V for conduction and a germanium diode takes 0.3V for
conduction. This 0.7V and 0.3V is called clipping level or reference level of diode.
Therefore the clipping level is not zero, but 0.7V.
Suppose the input signal has a peak value of 10V, the output of clipper will look like
figure 2.
Figure 2
Negative clippers :
A negative clipper is that which removes the negative half-cycles of the input voltage.
If we reverse the polarity of the diode in positive clipper circuit, we get a negative
clipper.
Figure shows the circuit of negative clipper. The clipping level is at -0.7V. Suppose
the input signal has a peak of 10V, the ideal output signal will look like as figure 3(a)
and practical signal will look like as figure 3(b).
Figure 3a
21
AB88
Figure 3b
These both positive and negative clippers circuits are the type of parallel clipper. The
parallel configuration is defined as one where the diode is in a branch parallel to the
load.
Series clippers :
The series configuration is defined as one where the diode is in series with the load
figure 4 (a) shows series negative clipper. During the positive half cycle, the diode
turns on and looks like a short across the output terminals Ideally, complete positive
cycle getting in output. On the negative half cycle, the diode is open. In that case, zero
voltage appears across the output. This circuit ideally behaves as a half wave rectifier.
The output signal looks like as figure 4(a).
Negative series clipper Figure 4a
Positive series clipper Figure 4b
22
AB88
Figure 4(b) shows positive series clipper. The functionality of this circuit is exactly
opposite to series negative clipper. During the positive half cycle of the input signal,
diode is open this gives zero voltage at output. During the negative half cycle, the
diode turns on and looks like a short across the output terminal .The output voltage is
shown in figure 4 (b).
Biased Clipper :
The reference level or clipping level of a positive clipper is ideally zero or 0.7V
practically. If we want to change this reference level we add bias in the circuit.
Bias means applying an external voltage to change the reference level. By adding a
DC voltage source in series with a diode, we can change the clipping level of positive
clipper. But limitation is that a new V must be less than Vm of our normal operation.
Figure 5 shows the circuit of biased positive clipper and biased negative clipper.
Examine the output wave amplitude in both circuits.
Biased positive clipper Figure 5a
Biased Negative clipper

Figure 5b
23
AB88
Combinational clipper :
Combination clipper is a combination of biased positive and negative clipper. With a
combination clipper, a portion of both positive and negative half cycles of input
voltage can be removed or clipped. From figure 6 Diode D1 clips off positive parts
above the positive bias level, and diode D2 clips off parts below the negative bias
level.
When positive input voltage is greater than +V1 , diode D1 conducts heavily while
diode D2 remains reverse biased .Therefore, a voltage +V1 appears across the load.
This output stays at +V1 as long as the input voltage exceeds +V1. On the other hand,
during the negative half cycle, the diode D2 will conduct heavily and output stays at
V2 so long as the input voltage is greater than V2.
Between +V1 and V2 neither diode is on. Therefore, in this condition, most of the
input voltage appears across the load.
Using batteries for low voltage is impractical. We give variable voltage source by
vary a resistance. Figure 6 gives the circuit of combination clipper. Examine the
amplitude of output wave.
Figure 6
24
AB88
Experiment 1
Objective : Study of Parallel positive and parallel negative clipper
Equipments Needed :
1. Analog board AB88
2. DC power supplies +5V and -5V from external source or ST2612 Analog Lab.
3. Oscilloscope Caddo 802 or equivalent
4. Function generator
5. 2 mm patch cords
Circuit diagram :
This experiment investigates the generation of positive and negative clipped
waveform across the diode.
Figure 7
25
AB88
Procedure :
Connect +5V and -5V DC power supplies at their indicated position from
1. With the help of function generator set sine wave of 1 KHZ frequency and
amplitude 2Vpp approximately this is the input signal of clipper which we want
to clip.
2. Give input signal to terminal a.
3. Monitor output signal at terminal b with the help of oscilloscope. This is the
output of positive parallel clipper.
4. Disconnect input to terminal a and connect it to terminal c.
5. Monitor output signal at terminal d with the help of oscilloscope. This is the
output of negative parallel clipper.
26
AB88
Experiment 2
Objective : Study of series positive and series negative clipper
Equipments Needed :
3. Oscilloscope Caddo or equivalent
5. 2 mm patch cords
Circuit diagram :
waveform at the diode.
Figure 8
27
AB88
Procedure :
1. With the help of function generator set sine wave of 1 KHZ frequency and
amplitude 2Vpp approximately this is the input signal of clipper which we want
to clip.
2. Give input signal to terminal e.
3. Monitor output signal at terminal f with the help of oscilloscope. This is the
output of positive series clipper.
4. Disconnect input to terminal e and connect it to terminal g.
5. Monitor output signal at terminal h with the help of oscilloscope. This is the
output of Negative series clipper.
28
AB88
Experiment 3
Objective :
Study of combination clipper
Equipments Needed :
3. Oscilloscope Caddo 802 or equivalent
5. 2 mm patch cords
Circuit diagram :
waveform by combination clipper.
Figure 9
29
AB88
Procedure :
1. With the help of function generator set sine wave of 1KHZ frequency and
amplitude 10Vpp approximately this is the input signal of clipper which we
want to clip.
2. Give input signal to terminal k.
3. Monitor output signal at terminal m, with the help of oscilloscope.
4. Turn the potentiometer near VA, on the board, to its fully clockwise position.
This is the variable DC voltage which we want to add in series with diode to
achieve a clipping level.
5. Turn the potentiometer near VB, on the board, to its fully clockwise position.
This is the variable DC voltage which we want to add in series with diode to
achieve a clipping level.
6. Vary the potentiometer and examine the effect of adding DC voltage at terminal
m.
7. Examine the level of DC voltage at TP1 and TP2, with the help of AC/DC
switch on the oscilloscope or multimeter.
8. If zero DC voltage is present on TP2 and only vary TP1 at that time circuit act
like as positive biased clipper. Examine the output at terminal m.
9. If zero DC voltage is present on TP1 and only vary TP2 at that time circuit act
like as negative biased clipper. Examine the output at terminal m.
30
Experiment No. 02 (B)
AB89 Diode Clamper
Theory
Clampers :
A circuit that places either the positive or negative peak of a signal at a desired DC
level is known as a clamping circuit or we can say that the clamping network is one
that will clamp a signal to a different dc level.
Suppose the input signal of a clamping network is a sine wave having a peak to peak
value of 10V.The clamper adds the DC component and pushes the signal upwards or
downwards according to the configuration .The point should be noted here is that the
clamping circuit does not change the peak to peak or r.m.s. value of the waveform.
A clamping circuit should not change the peak to peak value of the signal; it should
only change the DC level. To do so, a clamping circuit uses a capacitor, together with
a diode and a load resistor RL, but it can also employ an independent dc supply to
introduce an additional shift .The operation of a clamper is based on the principle that
charging time of a capacitor is made very small as compared to its discharging time.
In the practical clamping circuit, the magnitude of RL and C must be chosen such that
the time constant is large enough to ensure that the voltage across the capacitor does
not discharge significantly during the interval the diode is nonconducting .
Clamper are classified as-
1. Positive clamper
2. Negative clamper
Positive Clampers :
Positive Clamper
Figure 1
The output of the clamping network is like that the shape of the original signal has not
changed; only there is upward shift in the signal. Such a clamper is called a positive
clamper. When a positive clamper has a sine wave input, it adds a positive DC voltage
to the sine wave. Stated another way, the positive clamper shifts the AC reference
level (normally zero) up to a DC level. This means that each point on the sine wave is
shifted upward. figure 1 shows the circuit of a positive clamper .The input signal is
assumed to be a sine wave with time period T. The clamped output is obtained across
RL. The circuit design incorporates two man features. Firstly, the values of C and RL
are so selected that time constant = CRL is very large. Secondly, RLC time constant
is deliberately made much greater than the time period T of the incoming signal.
31
AB89
How the circuit works ?

The capacitor is initially uncharged. On the first negative half cycle of the input
signal, the diode is forward biased. Therefore, the diode behaves as a short. At the
negative peak of the AC source, the capacitor has fully charged and its voltage is Vm.
The charging time constant is very small so that the capacitor will charge to Vm volts
very quickly .During this interval, the output voltage is directly across the short
circuit. Therefore,
Vout = 0V
When the input switches to positive half cycle, the diode is, reverse biased and
behaves as an open. Since the discharging time constant is much greater than the time
period T of the input signal, the capacitor remains almost fully charged to Vm volts
during the off time of the diode. The resulting waveform shown in figure 1 is a
positively clamped output that means the input signal has been pushed upward by Vm
volts, so that negative peaks fall on the zero level.
Ideally, the clamping is less than perfect because the negative peaks have a reference
level of 0.7V instead of 0V.
Negative Clamper :
The output of the clamping network is like that the shape of the original signal has not
changed; only it pushes the signal downwards so that the positive peaks fall on the
zero level or if we change the polarity of the diode in positive clamper we get the
negative clamper. Figure 2 shows the circuit of a negative clamper. The clamped
output is taken across RL.
Again, the clamping is less than perfect because the positive peaks have a reference
level of 0.7V instead of 0V. During the positive half cycle of the input signal, the
diode is forward biased. Therefore, the diode behaves as a short. The charging time
constant is very small so that the capacitor will charge to V volts very quickly. During
this interval the output voltage is directly across the short circuit. Therefore,
Vout = 0V
When the input switches to negative half cycle, the diode is reverse biased and
behaves as an open .Since the discharging time constant is much greater than the time
period of the input signal, the capacitor almost remains fully charged to V volts
during the off time of the diode. Applying Kirchhoffs voltage law to the input loop,
we get output amplitude equal to sum of input amplitude and the charged capacitor
voltage amplitude. The resulting output waveform shown in figure 2.
Negative Clamper
Figure 2
32
AB89
Although all the waveforms appearing in figures are sine wave, clamping networks
work equally well for square wave. Both positive and negative clampers are widely
used in television receivers to change the reference level of video signals. Clampers
are widely used in Radar and communication circuits.
Biased Clampers :
If we want to clamp input signal with some reference level, use biased clamper
circuits. Biased clampers are circuits, which use DC voltage in series with diode.
Figure 3 shows the circuits of biased clamper. In figure 3(a) during positive half cycle
of the input signal, the diode is forward biased, so it acts as a short. It is clear that
Vout = VA
Where VA is the DC voltage, Vm is the peak input voltage. Applying Kirchhoffs
voltage law to the input loop in figure 3(a), we have
Vm - Vc - VA =0
and
Vc = Vm - VA
Where Vc is the voltage across capacitor.
During the negative half cycle of the input signal, the diode is reverse biased and
behaves as an open. Now battery or DC voltage has no effect on Vout. Applying
Kirchhoffs voltage law to the outside loop of figure 3(a), we have,
-Vm - VC - Vout =0
and
Vout = - Vm - VC
This same procedure follows in an all biased clamper circuits to find the amplitude of
output wave.
33
AB89
(d)
Biased Clamper Circuits
Figure 3
34
AB89
Experiment 1
Objective :
To study clamper circuits
Equipments Needed :
3. Oscilloscope
5. 2 mm patch cords
Circuit diagram :
Circuit used to study different combinations of clamper is shown in figure 4
Figure 4
35
AB89
Procedure :
1. Apply sine wave of 1 KHz frequency and amplitude 10Vpp approximately with
zero DC voltage at terminal a.
2. To make the circuit of negative clamper as shown in figure 2, connect 2mm
patch cord between socket b & ground terminal.
3. Put oscilloscope in DC coupling mode and monitor output signal at terminal f
with respect to ground on oscilloscope.
4. To make circuit of positive clamper as shown in figure 1, disconnect 2 mm
patch cord between terminals b & ground and connect between c & ground.
5. Keep the oscilloscope in DC coupling mode and observe output at terminal f
with respect to ground.
6. Next to make circuit of biased clamper as shown in figure 3(a), remove 2 mm
patch cord between terminal c & ground and connect between b & d terminals.
7. Observe output signal at terminal f with respect to ground.
8. Vary the voltage VA to increase the DC voltage from 0 to 5V and observe the
output voltage at terminal f.
9. Observe the level of output DC voltage at TP1.
10. Disconnect 2 mm patch cord between terminal b and d and connect between c &
e terminals, to make biased clamper circuit as shown in figure 3(d).
11. Monitor output signal at terminal f with respect to ground.
12. Vary the voltage VB to decrease the DC voltage from 0 to -5V and observe the
output voltage at terminal f.
13. Observe the level of output DC voltage at TP2.
14. To make the another combination of biased clamper ,as shown in figure 3(b),
remove the 2mm patch cord between terminal c & e and connect between b & e
terminals. Observe the effect of adding DC voltage at terminal f.
15. Disconnect 2 mm patch cord between terminal b & e and connect between c & d
terminals, to make circuit same as figure 3(c). Observe the effect of adding DC
voltage at terminal f.
36
DB22 Analog to Digital Converter
Theory
The electronic circuit that translates an analog signal to digital signal is called an
Analog to Digital Converter (ADC). It accepts an analog input voltage Vi and
produces an output binary word D0 - D3, where D3 is most significant bit and D0 is the
least significant bit. ADC's are classified broadly into two groups according to their
conversion technique. Direct type ADC's and integrating type ADC's. Direct type
ADC's compare a given analog signal with the internal generated equivalent signal.
This group includes flash (comparator) type converter, counter type converter,
tracking or servo converter, successive approximation type converter.
Integrating type ADCs perform conversion in an indirect manner by first changing the
analog input signal to a linear function of time or frequency and then to a digital code.
The two most widely used integrating type converters are charge balancing ADC and
dual slope ADC.
4 Bit Counter Type ADC :
The principle of this converter is to adjust DACs input code until the DACs output
comes within (1/2) LSB to the analog input Vi which is to be converted to binary
digital form. 4 Bit Counter Type ADC is shown in Figure 1. The counter is reset to
zero count by active high reset pulse. Counter starts counting on application of active
low signal. These pulses go through the NAND gate, which is enabled by the voltage
comparator high output. The number of pulses counted increase with time. The binary
word representing the count is used as the input of DAC whose output is a staircase
waveform. The analog output Vd of DAC is compared to the analog input Vi by the
comparator. If Vi> Vd, the output of the comparator become high and the NAND gate
is enabled to allow the transmission of the clock pulses to the counter. When Vi Vd,
the output of comparator becomes low and the NAND gate is disabled. This stops the
counting at the time Vi Vd and the digital output of the counter represents the analog
input voltage Vi. Low speed is the most serious drawback of this converter. The
conversion time can be as long as (2 n-1) clock periods depending upon the magnitude
of input voltage Vi (n is number of bits).
Re set / Count :
This terminal will Reset counter on applying +12V and starts counting on application
of ground.
Clock : CMOS clock of +12V and frequency of 2 Hz.
Vi : This terminal is used to give analog voltage. Maximum DC voltage of +5V can
be connected. Counter will show 1111 for +5V. If Vi is greater than +5V then counter
will count continuously and will not stop after 1111 state comes.
Vd : Analog output of DAC. It increases with count.
Vc : Positive saturation voltage for Vi >Vd, 0V for Vi = Vd.
Va : It is equal to clock pulse for Vi > Vd and clock pulse is also present when counter
is reset. Their will be no clock pulse for Vi =Vd
37
DB22
D0-D3 : Digital output (D0). The digital output is indicated by LEDs. For logic 1 LED
will glow red and for logic 0 it will be off i.e will not glow.
38
DB22
Experiment
Objective :
Study of 4 bit Counter type ADC
Equipments Needed :
1. Digital board DB22
2. DC Power Supply +12V,-12V and ground external source or ST2611 Digital
Lab.
3. Oscilloscope
4. Digital Multimeter or Digital Lab ST2611.
Logic Diagram & Truth Table :
(Logic 1 = +5V & Logic 0 = GND)
Figure 1
Procedure :
Connect +12V, -12V and ground to their indicated position on DB22
experiment board from external DC power supply or from DC power block of
Digital Lab ST2611.
2. Reset the counter by connecting +12V to reset / count .
3. Connect DC voltage between 0V to +5V to Vi and clock pulse of frequency 2Hz
and amplitude +12V to the clock terminal.
4. Connect ground to reset / count terminal.
5. Observe output on LED display given on the board. Output can also be observed
on 8 bits LED display of Digital Lab ST2611 by connecting terminal B0 B1 B2
B3 to the LED display.
39
DB22
Vi D3 D2 Dl D0
0V 0 0 0 0
- 0 0 0 1
- 0 0 1 0
- 0 0 1 1
- 0 1 0 0
- 0 1 0 1
- 0 1 1 0
- 0 1 1 1
- 1 0 0 0
- 1 0 0 1
- 1 0 1 0
- 1 0 1 1
- 1 1 0 0
- 1 1 0 1
- 1 1 1 0
5V 1 1 1 1
Truth Table D3 is MSB Table 1
6. Observe Vd on multimeter during counting. It increases linearly with time.
7. Observe Vc on multimeter during counting. It will be high as long as Vi >Vd and
zero for Vi = Vd.
8. Observe Va on oscilloscope. Clock is observed until count is complete.
9. Reset the counter.
10. Repeat above procedure for various input voltage between 0V to +5V.
40
DB22
Data Sheet
Pinout Diagram :
LM358 (OP-AMP)
Wide power supply range :

1. Single supply : 3V to 32V
2. Dual supplies : 1.5V to 16V
CD 4029 (4 Bit Binary/Decade Counter)
Vdd = +12V, Vss = Gnd
41
DB22
DAC08 (8 Bit DAC) :
Vs = 15V, IREF = 2.0 mA
42
DB22
Absolute Maximum Ratings :

Operating Temperature
DAC08AQ, Q-55 oC to 125o C
DAC08HQ, EQ, CQ, HP, EP..0 oC to 70oC
DAC08CP, CS...-40 oC to +85oC
Junction Temperature (T1)..-65 oC to +150 oC
Storage Temperature Q Package.-65 oC to +150 oC
Storage Temperature P Package..-65 oC to +125 oC
Lead Temperature (Soldering, 60 Sec).300 oC
V+ Supply to V-Supply...36 V
Logic Inputs ....V-to V-plus 36V
VLC....V-to V+
Analog Current Outputs (at Vs =15 V) ...4.25 mA
Reference Input (V14 to V15) ..V- to V+
Reference Input Differential Voltage
(V14 to V 15) 18V
Reference Input Current (I14) ..5.0 mA
IC4011
Vss = +3V to +12V, VDD Gnd
43
DB16 Digital to Analog Converter
Theory
The electronic circuit that translates a digital signal to analog signal is called a Digital
to Analog converter (DAC). Three resistive techniques for digital to analog
conversion are weighted resistor DAC, R-2R ladder and inverted R-2R ladder. DAC's
in which the analog signal is allowed to vary is called multiplying DAC.
Consider a 4-bit DAC as shown in figure 1 where input is binary word 1000. The
circuit is simplified to the equivalent form of figure 2 and finally to figure 3 Voltage
at node C is :
( 2R )
5V
3 = 1.25V
2R
2R +
3
The output voltage V0 = -2R / R (5V/4) = 2.5V
Similarly output voltage for R-2R ladder type DAC corresponding to other 4-bit
binary words can be calculated.
4-Bit DAC
Figure 1
44
DB16
Figure 2
Figure 3
45
DB16
Experiment
Objective :
Study of 4 Bit R-2R Ladder DAC
Equipment Needed :
1. Digital board DB16.
2. DC Power Supply +12V and -12V from external source or ST2611 Digital Lab.
3. Oscilloscope, Digital Multimeter or Digital Lab ST2611.
(Logic 1 = +5V & Logic 0 = Gnd)
R-2R Ladder DAC
Figure 4
Scientech Technologies Pvt. Ltd. 7

DB16
D3, D2, D1, D0 is digital input.

V0 is analog output.
D3 D2 Dl D0 V0
0 0 0 0 0V
0 0 0 1 -
0 0 1 0 -
0 0 1 1 -
0 1 0 0 -
0 1 0 1 -
0 1 1 0 -
0 1 1 1 -
1 0 0 0 -
1 0 0 1 -
1 0 1 0 -
1 0 1 1 -
1 1 0 0 -
1 1 0 1 -
1 1 1 0 -
1 1 1 1 5V
Truth Table for D3 is MSB
Figure 5
Procedure :
Connect +12V, -12V and ground to their indicated position on
DB16 experiment board from external DC power supply or from DC power
block of Digital Lab ST2611.
1. Switch on the power supply.
2. Connect binary input to D3, D2, D1, D0 as per truth table and note the analog
output on multimeter record it in the table given above.
3. Output will monotonically increase.

DB16
Data Sheet
Pin out diagrams V+ = +12V, V- = -12V
IC7141

Experiment No. 04
AB08 FET Characteristics
Theory
FET is a voltage controlled current device so its characteristics are the curves which
represent relationship between different DC currents and voltages. These are helpful
in studying different region of operation of a Field effect transistor when connected in
a circuit. The two important characteristics of a Field Effect Transistor are:
1. Output /Drain characteristic.
2. Transfer characteristic.
Output / Drain Characteristics :
It is the curve plotted between output drain current ID versus output drain to source
voltage VDS for constant values of input Gate to source voltage VGS as shown in figure
1.
Figure 1
It can be subdivided into following four regions:
Ohmic region OA :
This part of the characteristic is linear indicating that for low values of VDS, current
varies directly with voltage following Ohm's Law. It means that JFET behaves like an
ordinary resistor till point A (called knee) is reached.
Curve AB :
In this region, ID increases at inverse square law rate upto point B which is called
Pinch-off point. This progressive fall in the rate of increase of ID is caused by the
square law increase in the depletion region at each gate up to point B where the two
regions are closest without touching each other. The drain to source voltage VDS
corresponding to point B is called pinch-off voltage VPO.

AB08
Pinch-off region BC :
It is also known as saturation region or 'amplifier' region. Here, JFET operates as a
constant-current device because ID is relatively independent of VDS. It is due to the
fact that as VDS increases channel resistance also increases proportionally thereby
keeping ID practically constant at IDSS.
Drain current in this region is given by Shockley's equation
It is the normal operating region of the JFET when used as an amplifier.
ID = IDSS [1 (VGS / VPO)2 ] = IDSS [ (VGS / VGS (off))2 ]
Breakdown region :
If VDS is increased beyond its value corresponding to point C (called avalanche
breakdown voltage), JFET enters the breakdown region where ID increases to an
extensive value. This happens because the reversed biased gate channel PN junction
undergoes avalanche breakdown when small change in VDS produce very large
change in ID.
JFET characteristics with External Bias :
Figure 2 shows a family of ID versus VDS curves for different values of VGS. It is seen
that as the negative gate bias voltage is increased:
Pinch-off voltage VP is reached at a lower value of VDS than VGS = 0. Value of VDS
for breakdown is decreased.
Figure 2

AB08
Transfer Characteristic :
It is the curve plotted between output drain current versus input Gate to source voltage
for constant values of output drain to source voltage as shown in figure 3.
Figure 3
It is similar to the transconductance characteristics of a vacuum tube or a transistor. It
shows that when VGS = 0, ID = IDSS and when ID = 0, VGS = VPO. The transfer
characteristic approximately follows the equation
ID = IDSS [1 (VGS / VPO)2 ] = IDSS [ 1 (VGS / VGS(off))2 ]
The above equation can be written as VGS = VGS (off) [1 (ID / IDSS)1/2 ] These
characteristics can also be obtained from the drain/output characteristics by reading
off VGS and IDSS values for different values of VDS.
The various parameters of a JFET can be obtained from its two characteristics.
The main parameters of a JFET when connected in common source mode are
AC Drain Resistance, rd :
It is the AC resistance between drain and source terminals when JFET is operating in
the pinch-off region. It is given by
rd = change in VDS at VGS constant or rd = VDS / ID | VGS
change in ID
An alternative name is dynamic drain resistance. It is given by the slope of the drain
characteristics in the pinch off region. It is sometimes written as rds emphasizing the
fact that it is the resistance from drain to source. Since rd is usually the output
resistance of a JFET, it may also be expressed as an output admittance yos. Obviously,
yos = 1/rd. It has a very high value.

AB08
Transconductance, gm :
It is simply the slope of transfer characteristics
gm = change in ID at VDS constant or rd = ID / VGS | VDS
change in VGS
Its unit is siemens (S) /Mho. It is also called forward transconductance (gfs) or forward
transadmittance Yfs. The transconductance measured at IDSS is written as gmo.
Mathematically
gm = gmo [1 (VGS / VP)]
Amplification factor, :
It is given by
= change in VDS at ID constant or = VDS / VGS | IDS
change in VGS
It can be proved from above that = gm rd = gfs rd
DC drain resistance, RDS :
It is also called the static or ohmic resistance of the channel. It is given by
RDS = VDS / ID

AB08
Experiment
Objective :
Study of the characteristics of JFET (Junction field effect transistor) in common
source configuration and evaluation of:
1. AC drain resistance
2. Transconductance
3. Amplification factor
4. Drain Resistance
Equipments Needed :
2. DC power supplies +12V,-5V from external source or ST2612 Analog Lab.
Circuit diagram :
Figure 4

AB08
Procedure :
1. Connect -5V and + 12V DC power supplies at there indicated position from
2. To plot Drain characteristics proceed as follows :
3. Rotate both the potentiometer P1 and P2 fully in counter clockwise direction.
4. Connect Ammeter between test point 3 and 4 to measure output drain current ID
(mA).
5. Connect one voltmeter between test point 1 and ground to measure input voltage
VGS other voltmeter between test point 2 and ground to measure output voltage
VDS.
7. Vary the potentiometer P2 so as to increase the value of output voltage VDS from
zero to 10V in step and measure the corresponding values of output drain
current ID for different constant value of output voltage VDS in an observation
table 1.
8. Rotate potentiometer P2 fully in Counter Clockwise direction.
9. Rotate potentiometer P1 and set the value of input gate to source voltage at some
constant value (-1V, -2V, -3V.)
10. Repeat the procedure from step 6 for different sets of input voltage VGS.
11. Plot a curve between output voltage VDS and output current ID at different
constant values of input gate to source voltage as shown in figure 2 using
suitable scale with the help of observation table 1. This curve is the required
output/Drain characteristic.

AB08
Output Output Drain current ID (mA) at constant Value

S. no. voltage of input voltage
VDS (volt) VGS = 0V VGS = -1V VGS = -2V VGS = -3V
1. 0.0V
2. 1.0V
3. 2.0V
4. 3.0V
5. 4.0V
6. 5.0V
7. 6.0V
8. 7.0V
9. 8.0V
10. 9.0V
1. To plot Transfer characteristics proceed as follows :
3. Rotate both the potentiometer P1 and P2 fully in Counter Clockwise (counter
clockwise direction).
VDS.
5. Connect one Ammeter between test point 3 and 4 to measure output current
ID(mA)
6. Vary potentiometer P2 and set a value of output voltage VDS at some constant
value (1 V, 2V, 3V..........)
7. Vary the potentiometer P1 so as to increase the value of input voltage VGS from
zero to maximum value in step and measure the corresponding values of output
current ID in an observation table 2
8. Rotate potentiometer P1 fully in Counter Clockwise direction.

9. Repeat the procedure from step 5 for different sets of output voltage VDS.
10. Plot a curve between input voltage VGS and output current ID as shown in Figure
3 using suitable scale with the help of observation table 2. This curve is the
required Transfer characteristic.

AB08
Output Drain current ID (mA) at constant value of input

Input voltage voltage
S. No.
VGS (volt)
VDS = 1V VDS = 2V VDS = 3V VDS = 4V VDS = 5V
1. 0.0V
2. -0.5V
3. -1.0V
4. -1.5V
5. -2.0V
6. -2.5V
7. -3.0V
8. -3.5V
9. -4.0V

AB08
Calculations :
AC Drain Resistance, rd :
It is the AC resistance between drain and source terminals when JFET is operating in
the pinch-off region. To calculate AC drain resistance calculate the slope of the drain
characteristics in the pinch off region obtained from Observation Table 1.
rd = change in VDS at VGS constant or rd = VDS / ID | VGS
change in ID
It has a very high value.
Transconductance, gm :
To calculate transconductance determine slope of the transfer characteristics obtained
from Observation Table 2
gm = change in ID at VDS constant or rd = ID / VGS | VDS
change in VGS
Its unit is siemens (S) / mho.
Amplification factor, :
It is given by
= change in VDS at ID constant or = VDS / VGS | IDS
change in VGS
or = gm * rd
DC drain resistance, RDS :
It is also called the static or ohmic resistance of the channel. It is given by
RDS = VDS /ID
Results :
AC
Drain Resistance rd = _________
Transconductance, gm = _______
Amplification factor = _______
DC drain resistance, RDS _______________=

AB08
Data Sheet

AB08

DB01 Logic Gates
Theory
Logic Gate is a digital circuit with one or more input but only one output. AND, OR,
NAND, NOR, NOT, EX-OR Gates are some examples of Logic Gates. Each Gate has
one or two binary input variable designated by X & Y and one binary output variable
Z. The logic diagram and Truth Table of Logic Gates is shown in experiment section.
OR Gate : The OR gate has two or more than two inputs and one output. This
operation is represented by a plus sign eg. X +Y= Z is read X or Y is equal to Z
meaning that Z=1 if X=1 or if Y=1 or if both X=1 & Y=l. If both X=0 & Y=0 then
Z=0.The output voltage of OR Gate is high if any or all of the input voltages are high
that is +5 V or 1 (TTL level is used). Logic equation is Z = X + Y (X & Y are inputs
& Z is output.)
AND Gate : It has two or more than two inputs. This operation is represented by a dot
or by absence of an operator eg. X.Y=Z or XY=Z is read X AND Y is equal to Z. The
logical operation AND is interpreted to mean that Z=l if and only if X=l and Y=l
otherwise Z=0
NOT Gate : It has one input and one output. This operation is represented by prime
(bar). For example X= Z is read X not equal to Z" meaning that Z is what X is not. In
other words if X=l, then Z=0 but if X= 0 then Z=l.
NAND Gate : It has two inputs & one output. NAND function is compliment of AND
function. The bubble on output represents inversion after AND ing. The logic
equation is Z = (X.Y)'. The output is high if any of the input is low.
NOR Gate : It has two or more than two inputs and one output. The NOR function is
complement of OR function .The output is low if any input is high.
EX-OR Gate: Exclusive OR Gate has two inputs and one output. The output is high
if and only if the two inputs ie. X & Y are different ie. If X=l & Y=0 or X=0 & Y=l
otherwise output will be low.
The logic equation is XY' + X'Y = XY=Z.
Note : Refer Truth Tables and logic diagrams shown in experiment section.

DB01
Experiment
Objective :
Study of Logic Gates and verification of Truth Tables.
Equipments Needed :
2. DC power supply+5V from external source or Digital Lab ST2611.
3. Digital multi meter or Digital Lab ST261l.
Logic diagram & Truth Table :
(Logic 1 = +5 V & Logic 0 = GND)
X Y Y
0 0 0
0 1 1
1 0 1
1 1 1
.
OR Gate
X Y Y
0 0 0
0 1 0
1 0 0
1 1 1
AND Gate

DB01
X Y Y
0 0 1
0 1 0
1 0 0
1 1 0
NOR Gate
X Z
0 1
1 0
NOT Gate
X Y Y
0 0 1
0 1 1
1 0 1
1 1 0
NAND Gate

DB01
X Y Y
0 0 0
0 1 1
1 0 1
1 1 0
EX-OR Gate
Procedure :
1. Connect +5 V and ground to their indicated position on DB01 experiment board
from external DC power supply or from DC power block of Digital Lab
ST2611.
2. Connect inputs 00, 01, 10, 11 as per Truth Table to pin X and Y of AND Gate.
3. Switch on the power supply.
4. Observe output Z of AND Gates on multi meter or on logic probe or on LED
display of Digital Lab ST2611 and prove Truth Tables.
5. Repeat above steps for remaining Logic Gates.

DB01
Data Sheet
General Description :
The 74HC/HCT04 are high-speed Si-gate CMOS devices and are pin compatible with
low power schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A. The 74HC/HCT04 provides six inverting buffers.
Pin out diagram :
(Pin 14 = Vcc = + 5V)
Function Table :

DB01
standard no. 7A. The 74HC/HCT00 provide the 2-input NAND function.
Function Table :

DB01
standard no. 7A. The 74HC/HCT32 provide the 2-input OR function.
Function Table :

DB01
standard no. 7A. The 74HC/HCT08 provide the 2-input AND function.
Function Table :

DB01
This device contains four independent gates each of which performs the logic NOR
function.
Function Table :

DB01
Function Table :
H = High voltage level

L = Low voltage level
Note : Pull up resistance of 1K is required in open collector ICs to get output.

DB08 Binary Adder-Subtracter
Theory
Half Adder :
The combinational circuit that performs the addition of two bits is called a Half
Adder. This circuit has two binary inputs and two binary outputs. The input variable
X, Y designate the augends and addend bits, the output variables Sh, Ch produces the
sum and carry. The logic diagram and Truth Table are shown in experiment section.
The Boolean equation is
Sh = X.Y +X.Y= XY
Ch = X.Y
Full Adder :
The circuit that performs the addition of three bits (two significant bits and a previous
carry) is called a full adder. It consists of three inputs X, Y, Z. Two of the input
variable, denoted by X and Y, represents the two significant bits to be added. The
third input, Z, represents the carry from the previous lower significant position. The
output Sf gives the value of the least significant bit of sum and Cf gives the output
carry. The logic diagram for 3-bit full adder is shown in experiment section. The
Boolean equation is
Sf = XYZ + XYZ+ XYZ+ XYZ
Cf = X.Y + X.Z +Y.Z
The full adder introduced above forms the sum of two bits and a previous carry. Two
binary number of n bits each can be added in parallel by means of binary parallel
adder. Consider two 2 bit numbers Y0 X0, Y1 X1
Y0 X0 Y0 X0
+ Y1 X1 = Y1 X1
SUM C0 S1 S0
It can also be constructed with two full adder in cascade, with the output carry from
one full adder connected to the input carry of the next full adder. An n bit parallel
adder requires n full adder. The Truth Table and logic diagram for 2 bit binary parallel
adder is shown in experiment section.
Half Subtracter :
A Half Subtracter is a combinational circuit that subtracts two bits and produces their
difference. It has two inputs X, Y. X is minuend and Y is subtrahend. The output bits
are designated by Bh, Dh. Dh is difference bit and Bh is borrow bit (generates the
binary signal that informs the next stage that a 1 has been borrowed). The logic
diagram and Truth Table for 2 bit Half Subtracter is shown in experiment section.
The Logic equation is
Dh = XY+XY= XY

DB08
Experiment
Objective :
Verification of Truth Table for the following Digital Circuits
1. 2 Bit Binary Half Adder.
2. 3 Bit Binary Full Adder.
3. 2 Bit Binary Parallel Adder.
4. 2 Bit Binary Half Subtracter.
Equipment Needed :
1. Digital board DB08
2. DC Power Supply +5 V from external source or ST2611 Digital lab.
3. Digital Multimeter or Digital Lab ST2611.
(Logic 1 = +5 V & Logic 0=GND)
X Y Ch Sh
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
2 Bit Binary Half Adder
Figure 1
X Y Z Cf Sf
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
3 Bit Binary Half Adder 1 1 1 1 1
Figure 2

DB08
2 Bit Binary Parallel Adder

Figure 3
Y0 X0 Y1 X1 C0 S1 S0
0 0 0 1 0 0 1
0 1 0 1 0 1 0
0 1 1 1 1 0 0
1 0 1 0 1 0 0
1 0 1 1 1 0 1
Truth Table

DB08
X Y Bh Dh
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
2 Bit Binary Half Subtracter

Figure 4
Procedure :
1. Connect +5 V and ground to their indicated position on DB08 from external DC
Power Supply or from DC power block of Digital Lab ST -2611.
2. Switch on the Power Supply.
3. Connect inputs X, Y as per Truth Table to 2 bit binary Half Adder.
4. Observe output Sh, Ch on multimeter or on LED display of Digital Lab ST2611
and prove Truth Table.
5. Switch Off the Power Supply.
6. Connect output Sh, CH of 2 bit binary Half Adder to input Sh, Ch of 3 bit binary
Full Adder.
7. Connect input X, Y, Z to 3 bit binary Full Adder as per Truth Table shown.
8. Observe output Sf, Cf on multimeter or on LED display of Digital Lab ST2611
and prove Truth Table.
9. Repeat above steps and prove Truth Table for 2 bit binary parallel Adder and 2
bit binary Half Subtracter.

DB08
Data Sheet
Pinout diagrams : (Pin 14 = Vcc = +5 V)

low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard number 7A.
The 74HC/HCT00 provide the 2-input NAND function.

DB08
Quad 2- Input Exclusive-OR Gate 54LS/74S136
Pinout Diagram : (Pin 14 = Vcc = + 5 V)
Function
Table
H = High voltage level

L = Low voltage level

DB08
standard number 7A.
The 74HC/HCT32 provide the 2-input OR function.

DB08
standard number 7A.
The 74HC/HCT08 provide the 2-input AND function.

DB08
standard number 7A.
The 74HC/HCT04 provides six inverting buffers.
Note : Pull up resistance of 1 K is required in open collector ICs to get output

Experiment No. 06
DB10 Multiplexer-Demultiplexer
Theory
Multiplexing means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single
output line. The selection of a particular input line is controlled by a set of selection
lines. There are 2n input lines and n selection lines whose bit combinations determine
which input is selected.
A 4 to 1 Line Multiplexer is shown in figure 1. Each of the four input lines, D0 to D3
is applied to one input of an AND gate. Selection lines S1, S0 are decoded to select a
particular AND gate. When S1, S0 = 10. The AND gate associated with input D2 has
two of its inputs equal to 1 and third input connected to D2. The other three AND
gates have at least one input equal to 0, which makes their output equal to 0. The OR-
gate output is now equal to the value of D2, thus providing a path from the selected
input to the output. A multiplexer is also called a data selector, since it selects one of
many inputs and steers the binary information to the output line. Whenever any input
is selected which is in form of clock pulse all other inputs should be at zero level i.e.
logic 0.
A demultiplexer is a circuit that receives information on a single line and transmits
this information on one of 2n possible output lines. The selection of a specific output
line is controlled by the bit values of n selection lines. 1 to 4 Line Demultiplexer is
shown in figure 2 the single input variable D has a path to all four outputs, but the
input information is directed to only one of the output lines, as specified by the binary
value of the two selection lines S1 and S0. If the selection lines S1, S0 = 1, 0 output
D2 will be same as the input value D, provided D =0 while all other outputs are
maintained at 1. For D=1.
All outputs are at high level. Clock pulse given to D input can be obtained at output
lines through selection lines S1 S0.
Table 1a and 2a shows Truth Table for 4 to 1 Line Multiplexer and 1 to 4 line de-
multiplexer.

DB10
Experiment
Objective :
To study the following circuit and verify their Truth Table.
1. 4 To 1 Line Multiplexer
2. 1 To 4 Line De-Multiplexer
Equipments Needed :
2. DC Power Supply +5 V from external source or ST2611 Digital lab.
3. Oscilloscope, Digital Multimeter or Digital Lab ST2611.
Logic diagram & Truth Table :
(Logic 1 = +5 V & Logic 0=GND)
Figure 1
D0 Dl D2 D3 S1 S0 Z
1 0 1 0 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 1
1 0 1 0 1 1 0
Table 1a

DB10
D D D
D2 S1 S0 Z
0 1 3
I 0 0 0 0 0 I
0 I 0 0 0 1 I
0 0 I 0 1 0 I
0 0 0 I 1 1 I
I (Clock Pulse of 1 KHz)

Table 1b
Figure 2
D S1 S0 D0 D1 D2 D3
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
Table 2a
D S1 S0 D0 D1 D2 D3
I 0 0 I 1 1 1
I 0 1 1 I 1 1
I 1 0 1 1 I 1
I 1 1 1 1 1 I
I (Clock Pulse of 1 KHz)
Table 2b

DB10
Procedure :
1. Connect +5 V and ground to their indicated position on DB10 from external DC
power supply or from DC power block of Digital Lab ST2611.
2. Switch ON the power supply.
3. Connect inputs D0-D3 as per Truth Table1a to 4 to 1 line
multiplexer. Circuit as shown in figure 1.
4. Observe output, Z on multimeter or on LED display of Digital Lab ST2611 and
prove Truth Table.
5. Repeat step 3 and 4 for Table 1b. Observe results on Oscilloscope.
6. Connect input D as per Truth Table 2a to 1 to 4 Line Demultiplexer circuit as
shown in figure 2.
7. Observe output D0-D3 on multimeter or on LED display of Digital Lab
ST2611 and prove Truth Table.
8. Repeat steps 2 & 3 for Table 2b and observe output on Oscilloscope.

DB10
Data Sheet

DB10

DB10

DB10
TRIPLE 3-INPUT NAND GATE 7412
Note : Pull up resistance of 1 k is required in open collector ICs to get output.

AB44 Operational Amplifier (Integrator/Differentiator)
Theory
Operational amplifier is a direct-coupled high-gain amplifier usually consisting of one
or more differential amplifiers and usually followed by a level translator and an
output stage. The output stage is generally a push-pull or push-pull complementary-
symmetry pair. An operational amplifier is available as a single integrated circuit
package.
The operational amplifier is a versatile device that can be used to amplify DC as well
as AC input signals and was originally designed for performing mathematical
operations such as addition, subtraction, multiplication, and integration. Thus the
name operational amplifier stems from its original use for these mathematical
operations and is abbreviated to op-amp. With the addition of suitable external
feedback components, the modern day op-amp can be used for a variety of
applications, such as AC and DC signal amplification, active filters, oscillators,
comparators, regulator, regulators, integrator, differentiator.
Integrator :
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator or the integration amplifier. Such a circuit is obtained by
using a basic inverting amplifier configuration if the feedback resistor RF is replaced
by a capacitor CF as shown in figure1.
Figure 1
The expression for the output voltage Vout is given by :
Vout = - (l/R1CF) 0 t Vin dt + C
Where C is the integration constant and is proportional to the value of the output
voltage Vout at time t = 0 seconds.
When Vin = 0, the integrator of figure 1 works as an open-loop amplifier. This is
because the capacitor CF acts as an open circuit (XCF =) to the input offset voltage
Vin. In other words, the input offset voltage Vio and the part of the input current
charging capacitor CF produce the error voltage at the output of the integrator.
Therefore, in the practical op-amp shown in figure 2, to reduce the error voltage at the
output, a resistor RF is connected across the feedback capacitor CF. Thus, RF limits the
low-frequency gain and hence minimizes the variations in the output voltage.

AB44
Figure 2
The 0dB frequency i.e. the frequency at which the gain is 0dB is given by :
Fb = R1 CF
Both the stability and the low-frequency roll-off problems can be corrected by the
addition of a resistor RF as shown in the practical integrator. The term stability refers
to a constant gain as frequency of an input signal is varied over a certain range. Also
low frequency roll-off refers to the rate of decrease in gain at lower frequencies.
The gain limiting frequency Fa is given by :
Fa = RF CF
Generally, the value of fa and in turn R1CF and RFCF values should be selected such
that Fa < Fb. For example, if Fa = Fb/10, then RF = 10 R1. In fact, the input signal will
be integrated properly if the time period T of the signal is larger than or equal to RF
CF. That is,
T RF CF where RF CF = Fa
A workable integrator can be designed by implementing the following
steps :
1. Select Fa equals to the maximum frequency of the input signals to be integrated.
Then, assuming a value of CF < 1F, calculate the value of RF.
2. Choose Fb = 10 Fa and calculate the value of R1 = RF / 10.
The integrator is most commonly used in analog computers and analog to digital and
signal-wave shaping circuits.

AB44
Differentiator :
Figure 3 shows the differentiator or differentiation amplifier. As its name implies, the
circuit performs the mathematical operation of differentiator; that is the output
waveform is the derivative of the input waveform. The differentiator may be
constructed from a basic inverting amplifier if an input resistor R1 is replaced by a
capacitor C1.
Figure 3
The expression for the output voltage is given by :
Vout = RFC1 * dVin / dt
Thus the output Vo is equal to the RF C1 times the negative instantaneous rate of
change of the input voltage Vin with time.
The differentiator performs the reverse of the integrator's function. However, the
differentiator of figure 3 will not do this because it has some practical problem. The
gain of the circuit (RF / Xc1) increases with increase in frequency at a rate of 20dB /
decade. This makes the circuit unusable. Also, the input impedance Xc1 decreases
with increase in frequency, which makes the circuit very susceptible to high-
frequency noise. When amplified, this noise can completely override the
differentiated output signal.
The frequency at which the gain is 0dB is given by :
Fa = RF C1
Both the stability and the high-frequency noise problems can be corrected by the
addition of two components: R1 and CF, as shown in figure 4. This circuit is a
practical differentiator.

AB44
Figure 4
The gain limiting frequency Fb is given by
Fb = R1C1
Generally, the value of Fb and in turn R1C1 and RF CF values should be selected such
that
Fa < Fb < Fc
Where Fc is unity gain bandwidth
The input signal will be differentiated properly if the time period T of the input signal
is larger than or equal to RF C1. That is,
T RF C1
A workable differentiator can be designed by implementing the following steps :
1. Select Fa equals to the highest frequency of the input signals to be differentiated.
Then, assuming a value of C1<1F, calculate the value of RF.
2. Choose Fb = 10 Fa and calculate the value of R1 and CF so that
R1C1 = RFCF.

AB44
Experiment 1
Objective :
Study of Operational Amplifier as an Integrating Amplifier/Integrator
Equipments Needed :
2. DC Power Supplies +12V and -12V from external source or ST2612 Analog
Lab.
3. Oscilloscope
4. 2mm. Patch Cords.
Circuit diagram :
Circuit used to study Integrating Amplifier is shown in figure 5.
Figure 5

AB44
Procedure :
Connect +12V, -12V, DC power supplies at their indicated position from
1. Select Fa = 10K, the maximum frequency of the input signals to be integrated.
2. As CF < 1F i.e. 100 PF, calculate the value of RF.
3. Choose Fb = 10Fa and calculate the value of R1 = RF /10.
4. Use potentiometer R1 and RF set the above calculated values of R1 and RF.
5. Connect a patch cord between test point A, B and C, D.
6. Apply an input voltage of 1Vpp at the test point Vin l.
7. Measure and trace the output waveform at the test point Vout.
8. Vary the frequency of input signal and observe its effect on the output
waveform.
9. Repeat the above procedure for different maximum frequencies of input signal.
10K, 50K, 100K etc.

AB44
Experiment 2
Objective :
Study of Operational Amplifier as a Differentiating Amplifier/Differentiator
Equipments Needed :
1. Analog Board of AB44.
2. DC Power Supplies +12V and -12 from external source or ST2612 Analog Lab.
3. Cathode Ray Oscilloscope
4. Function Generator
5. 2mm. Patch Cords
Circuit diagram :
Circuit used to study Differentiating Amplifier Circuit is shown in figure 6.
Figure 6

AB44
Procedure :
Connect +12V and -12V DC Power supplies at their indicated position from
1. Select Fa = 100Hz, the maximum frequency of the input signals to be
differentiated.
2. As C1 = .001F, calculate the value of RF using relation
Fmax = Fa = RF C1.
3. Choose Fb = 10Fa and calculate the value of R1 using the relation Fb = R1 C1
4. Use potentiometer R1 and RF to set the above calculated values of R1 and RF.
5. Connect a patch cord between test point C, D
6. Apply sine, square, triangular wave one by one of 1 Vpp at the test point Vin l.
7. Measure and trace the output waveform at the test point Vout.
8. Vary the frequency of input signal for a maximum of 1K, 10K & 100K and
observe its effect on the output waveform.

AB44
Data Sheet

AB42 Operational Amplifier (Inverting/Noninverting)
Theory
Operational amplifier is a direct-coupled high-gain amplifier usually consisting of one
or more differential amplifiers and usually followed by a level translator and an
output stage. The output stage is generally a push-pull or push-pull complementary-
symmetry pair. An operational amplifier is available as a single integrated circuit
package.
The operational amplifier is a versatile device that can be used to amplify DC as well
as AC input signals and was originally designed for performing mathematical
operations such as addition, subtraction, multiplication, and integration. Thus the
name operational amplifier stems from its original use for these mathematical
operations and is abbreviated to op-amp. With the addition of suitable external
feedback components, the modern day op-amp can be used for a variety of
applications, such as AC and DC signal amplification, active filters, oscillators,
comparators, regulator, regulators, and others.
The op-amp may be used as an inverting, non-inverting, or differential amplifier, and
that the negative feedback can be used to stabilize the voltage gain and increase the
bandwidth of the op-amp circuit.
The Inverting Amplifier :
Figure 1 shows the inverting amplifier in which only one input is applied and that is to
the inverting input terminal. The non-inverting input terminal is grounded.
Without feedback with feedback

Figure 1
Since V1 = 0V, and V2 = Vin
Out put voltage Vout is given by
Vout = -A * Vin,
Where A is Open loop gain.
Also Output voltage of closed loop circuit.
Vout = -AC1 * Vin = - (Rf / R1) Vin. ..........................................(1)
Where AC1 is closed loop gain.

AB42
The Non-Inverting Amplifier :

Figure 2 shows the non-inverting amplifier in which only one input is applied and that
is to the non-inverting input terminal. The inverting input terminal is grounded.
Without feedback with feedback
Figure 2
Since V1 = Vin, and V2 = 0V, Output voltage Vout is given by
Vout = A * Vin,
Where A is Open loop gain.
Also Output voltage
Vout = -ACl * Vin = (1+Rf / R1) Vin.................................(2)
Where AC1 is closed loop gain.

AB42
The Differential Amplifier :

Since the op-amp amplifies the difference between the two input signals, this is called
the differential amplifier.
Figure 3 shows the differential amplifier in which input signals Vin1 and Vin2 are
applied to the positive and the negative input terminals. The source resistance R1 and
R2 are normally negligible compared to the input resistance Ri. Therefore the voltage
drop across these resistors can be assumed to be zero.
Without feedback With feedback

Figure 3
Output voltage Vout for differential amplifier is given by
Vout = A (Vinl - Vin2),
Where A is the open loop voltage gain.
Also Vout = Rf/Rl (Vinl- Vin2) .................................(3)
If R1 = R2 and Rf = R3 for closed loop circuit.

AB42
Input offset voltage :

Input offset voltage Vio is the differential input voltage that exists between two input
terminals of an op-amp without any external inputs applied. In other words, it is the
amount of the input voltage that should be applied between two input terminals in
order to force the output voltage to zero.
Figure 4
Common Mode Rejection Ratio :
Data sheets list the common-mode rejection ratio (CMRR). It is defined as the ratio of
differential voltage gain to common-mode voltage gain. Generally, the CMRR value
is very large and is therefore usually specified in decibels (dB), where
CMRR (dB) = 20 log (AD/ACM)
The CMRR can also be expressed as the ratio of the change in the offset voltage to the
total change in common-mode voltage. Thus
CMRR = Vio/ VCM or CMRR (dB) = 20 log (Vio/Vcm)
CMRR is a measure of the degree of matching between two input terminals; that is,
the larger the value of CMRR (dB), the better is the matching between the two input
terminals and the smaller is the output common-mode voltage.
Frequency Response :
The gain of the op-amp is a complex number that is a function of frequency.
Therefore, at a given frequency the gain will have a specific magnitude as well as a
phase angle. This means that variation in operating frequency will cause variation in
gain magnitude and its phase angle.
The manner in which the gain of the op-amp responds to different frequency is called
the frequency response. A graph of the magnitude of gain versus frequency is called
the frequency response plot.

AB42
Experiment 1
Objective :
Study of Operational amplifier as a Differential amplifier
Equipments Needed :
2. DC power supplies +12V and -12V from external source or ST2612 Analog
Lab.
3. Variable DC supplies (+5V and +12V)
4. Digital multi-meter.
5. 2 mm. patch cords.
Circuit diagram :
Circuit used to study Differential amplifier circuit is shown in figure 5.
Figure 5

AB42
Procedure :
Connect +12V, -12V DC power supplies at their indicated position from
1. Set the value of feedback resistance RF equals to 10K with the help of
potentiometer observing its value at sockets E and F.
2. Set the value of resistance ROM equals to 10 K with the help of potentiometer
observing its value at sockets H and Vin2.
3. Connect a patch cord between test point B & H; and F & G, Vin2 & ground to
configure a Differential Amplifier.
4. Switch ON the power supplies.
5. Connect the +5V supply at socket Vin1; that is inverting input for Op-amp.
Keep this supply at constant +5V.
6. Connect the Variable +12V supply at socket A; that is noninverting input for
op-amp. Set the supply voltage at 1V.
7. Calculate the value of output by using Eq.3;
Vout = Rf/R1 (Vinl- Vin2)
8. Where Vin1 is the input at socket A noninverting terminal, and Vin2 is the
input at socket Vin1 inverting terminal.
9. Connect the multimeters probes at socket Vout and Ground.
10. Note the output voltage and verify the difference between calculated and
measured output voltage.
11. Increase the input voltage at noninverting terminal (socket A) with the margin
of 1V up to 10 V whilst keeping input voltage at inverting terminal at constant
+5V.
12. Repeat the above steps from 7 to 10.
The Differential output of two AC signal can be observe
1. If the inputs which are given in the input terminals are at same frequency and
have 180 phase shift.
2. Then the difference between both signal will appear at the output
3. It is difficult to get the inputs which have same frequency, thus this bridges are
used at measuring the differential voltage at AC Bridges.
Note :
1. Try to make given circuits on the bread board strip given on the Analog Board
to practice and understand its connections.

AB42
Observation Table :
S. No. VIN1 VIN2 VOUT VOUT

(Calculated) (Measured)
Conclusion : The calculated and measured output are almost the same.

AB42
Experiment 2
Objective :
Study of Operational amplifier as an Inverting amplifier
Equipments Needed :
2. DC power supplies +12V and -12V
4. Oscilloscope
Circuit diagram :
Circuit used to study Inverting amplifier circuit is shown in figure 6.
Figure 6

AB42
Procedure :
potentiometer RF observing its value at sockets E and F.
2. Set the value of resistance ROM equals to 5 K with the help of potentiometer ROM
observing its value at socket H and Vin2.
3. Connect a patch cord between sockets F & G; and Vin2 & ground to
configure the Inverting amplifier.
4. Connect Function generators probe at the socket Vinl; to apply 1Vpp, 1 KHz,
sine wave signal at input.
5. Observe the input amplitude on oscilloscope CHII.
6. Calculate the output for the given value of input using Eq.1
Vout = - (Rf / R1) Vin.
7. Observe the output waveform between socket Vout and Ground on oscilloscope
CHI.
8. Note the output voltage and Verify the difference between calculated and
measured output voltage
9. Note the phase shift between the output and input waveform.
10. Repeat the above procedure for different value of feedback resistance RF.
11. Repeat the above procedure for different value of input voltage Vin.
Note : To see the phase shift between input and output signal its necessary to connect
both, input and output signal at the oscilloscope channels.

AB42
Observation Table :
Phase shift
S. No. VIN RF RF VOUT VOUT
/R1 ()
(Measured)
(Calculated)
Conclusion :
1. The calculated and measured output is almost the same.
2. The Phase shift between input and output signal is 180

AB42
Experiment 3
Objective :
Study of Operational amplifier as a Non-inverting amplifier
Equipments Needed :
2. DC power supplies +12V and -12V
3. Oscilloscope
Circuit diagram :
Circuit used to study non-inverting circuit is shown in figure 7.
Figure 7

AB42
Procedure :
potentiometer RF observing its value at sockets E and F.
2. Connect a patch cord between sockets F & G; and Vin1 & ground to
configure the Noninverting amplifier.
3. Connect Function generators probe at the socket H; to apply 1Vpp, 1 KHz,
sine wave signal at noninverting input terminal.
4. Observe the input amplitude on oscilloscope CHII.
5. Calculate the output for the given value of input using equation 2
Vout = (1+Rf / R1) Vin
6. Observe the output waveform between socket Vout and Ground on oscilloscope
CH I.
7. Note the output voltage and Verify the difference between calculated and
measured output voltage
8. Note the phase shift between the output and input waveform.
9. Repeat the above procedure for different value of feedback resistance RF.
10. Repeat the above procedure for different value of input voltage Vin.
Note : To see the phase shift between input and output signal its necessary to connect
both input and output signal at the oscilloscope channels.

AB42
Observation Table :
Phase Shift
S. No. VIN RF 1+(RF VOUT VOUT
/R1) ()
(Measured)
(Calculated)
Conclusion :
1. The calculated and measured output is almost the same.
2. The Phase shift between input and output signal is 0.

AB42
Data Sheet

Experiment No. 08
AB01 Diode Characteristics
Theory
Introduction:
A diode is an electrical device allowing current to move through it in one direction
with far greater ease than in the other. The most common type of diode in modem
circuit design is the semiconductor diode, although other diode technologies exist.
Semiconductor diodes are symbolized in schematic diagrams as shown below
Figure 1
When placed in a simple battery-lamp circuit, the diode will either allow or prevent
current through the lamp, depending on the polarity of the applied voltage:
Figure 2
When the polarity of the battery is such that electrons are made to flow through the
diode, the diode is said to be forward-biased. Conversely, when the battery is
"backward" and the diode blocks current, the diode is said to be reverse biased. A
diode may be thought of as a kind of switch: "closed" when forward-biased and
"open" when reverse-biased.

AB01
V-I Characteristic:
The static voltage-current characteristics for a P-N Junction diode are shown in figure 3.
Figure 3
Forward Characteristic:
When the diode is in forward-biased and the applied voltage is increased from zero,
hardly any current flows through the device in the beginning. It is so because the
external voltage is being opposed by the internal barrier voltage VB whose value is
0.7V for Si and 0.3V for Ge. As soon as VB is neutralized, current through the diode
increases rapidly with increasing applied supply voltage. It is found that as a little
voltage of 1.0V produces a forward current of about 50mA.
Reverse Characteristic:
When the diode is reverse-biased, majority carrier are blocked and only a small
current (due to minority carrier) flows through the diode. As the reverse voltage is
increased from zero, the reverse current very quickly reaches its maximum or
saturation value Io which is also known as leakage current. It is of the order of
nanoAmperes (nA) and microAmperes (A) for Ge.
As seen from figure 3, when reverse voltage exceeds a certain value called breakdown
voltage VBR, the leakage current suddenly and sharply increases, the curve indicating
zero resistance at this point.
Zener Diode:
It is the reverse-biased heavily-dopped silicon (or germanium) P-N Junction diode
which is operated in the breakdown region where current is limited by both external
resistance and power dissipation of the diode. Silicon is preferred to diode because of
its higher temperature and current capability. Zener breakdown occurs due to breaking
of covalent bonds by the strong electric field set up in the depletion region by the
reverse voltage.
It produces an extremely large number of electrons and holes, which constitute the
reverse saturation current (called zener current Iz) whose value is limited only by the
external resistance in the circuit.

AB01
V-I Characteristic:
Figure 4 shows typical characteristics in the negative quadrant. The forward
characteristic is simply that of an ordinary forward-biased junction diode. The
important points of the reverse characteristic are Vz = Zener breakdown voltage.
Iz min = Minimum current to sustain breakdown
Iz max = Maximum Zener current limited by, maximum power dissipation. Since its
reverse characteristic is not exactly vertical, the diode possesses some resistance
called Zener dynamic impedance. Its value is given by Zz = Vz / Iz.
Zener diode are available having zener voltage of 2.4V to 200V. This voltage is
temperature dependent. The product Vz, Iz, gives their power dissipation. Maximum
ratings vary from 150mW to 50W.
Figure 4
For proper working of a Zener diode in any circuit, it is essential that it must
1. Be reverse-biased,
2. Have voltage across it greater than Vz,
3. Be in a circuit where current is less than Izmax.
Light-emitting Diodes:
Diodes, like all semiconductor devices, are governed by the principles described in
quantum physics. One of these principles is the emission of specific-frequency radiant
energy whenever electrons fall from a higher energy level to a lower energy level.
A diode intentionally designed to glow like a lamp is called a light-emitting diode, or
LED. Diodes made from a combination of the elements gallium, arsenic, and
phosphorus (called gallium-arsenide-phosphide) glow bright red, and one of some of
the most common LED manufactured. By altering the chemical constituency of the
PN junction, different colors may be obtained. Some of the currently available colors
other than red are green, blue, and infra-red (invisible light at a frequency lower than
red). Other colors may be obtained by combining two or more primary-color (red,
green, and blue). The schematic symbol for an LED is a regular diode shape inside of
a circle, with two small arrows pointing away (indicating emitted light)

AB01
Figure 5
This notation of having two small arrows pointing away from the device is common
to the schematic symbols of all light-emitting semiconductor devices. Conversely, if a
device is light-activated (meaning that incoming light stimulates it), then the symbol
will have two small arrows pointing toward it. It is interesting to note, though, that
LEDs are capable of acting as light-sensing devices: they will generate a small
voltage when exposed to light, much like a solar cell on a small scale. This property
can be gainfully applied in a variety of light-sensing circuits.
Because LEDs are made of different chemical substances than normal rectifying
diodes, their forward voltage drops will be different. Typically, LEDs have much
larger forward voltage drops than rectifying diodes, anywhere from about 1.6 Volts to
over 3 Volts, depending on the color. Typical operating current for a standard-sized
LED is around 20 mA. When operating an LED from a DC voltage source greater
than the LED's forward voltage, a series-connected "dropping" resistor must be
included to prevent full source voltage from damaging the LED. LED starts emitting
light as its forward voltage reaches at a particular level and its intensity will increase
further with the increase in applied forward voltage. LEDs emit no light when reverse
biased. In fact, operating LEDs in reverse direction will quickly destroy them if the
applied voltage is quite large. LEDs V-I characteristic curve is shown in figure 6.
Characteristics of LED
Figure 6

AB01
Experiment 1
Objective:
Study of characteristics of Silicon diode in:
1. Forward bias
2. Reverse bias
Equipments Needed:
2. DC power supplies +12V from external source or ST2612 Analog Lab.
Circuit diagram:
Circuit used to plot different characteristics of Si diode is shown in figure 7.
Figure 7

AB01
Procedure:
Connect +12V DC power supplies at their indicated position from external
source or ST2612 Analog Lab.
To plot forward characteristics proceed as follows
1. Rotate potentiometer P1 fully in CCW (counter clockwise direction).
2. Connect Ammeter between test point 2 and 8 to measure diode current ID (mA).
3. Connect one voltmeter between test point 1 and 9 to measure voltage VD diode
5. Vary the potentiometer P1 so as to increase the value of diode voltage VD from
zero to 1V in step and measure the corresponding values of diode current ID in
an observation Table 1.
6. Plot a curve between diode voltage VD and diode current ID as shown in figure 3
(First quadrant) using suitable scale with the help of observation Table 1. This
curve is the required forward characteristics of Si diode.
Observation Table 1:
Diode Diode current
S. No.
Voltage (VD) ID (mA)
1. 0.0V
2. 0.1V
3. 0.2V
4. 0.3V
5. 0.4V
6. 0.5V
7. 0.6V
8. 0.7V
9. 0.8V
10. 0.9V
11. 1.0V
To plot Reverse characteristics of a Si diode proceed as follows
2. Connect Ammeter between test point 3 and 8 to measure diode current ID (nA).
zero to 10V in step and measure the corresponding values of diode current ID in

AB01
(third quadrant) using suitable scale with the help of observation Table 2. This
curve is the required forward characteristics of Si diode.
Diode
S. No. Diode current ID (nA)
Voltage (VD)
1. 0.0V
2. 1.0V
3. 2.0V
4. 3.0V
5. 4.0V
6. 5.0V
7. 6.0V
8. 7.0V
9. 8.0V
10. 9.0V
11. 10.0V

AB01
Experiment 2
Objective:
Study of characteristics of Zener diode in
1. Forward bias
2. Reverse bias
Equipments Needed:
1. Analog board of AB01
Circuit diagram:
Circuit used to plot different characteristics of Zener diode is shown in figure 8
Figure 8

AB01
Procedure:
To plot Forward characteristics proceed as follows:
2. Connect Ammeter between test point 6 and 8 to measure diode current Iz (mA).
3. Connect one voltmeter between test point 1 and 9 to measure voltage Vz diode.
5. Vary the potentiometer P1 so as to increase the value of Zener voltage Vz from
zero to 0.8 in step and measure the corresponding values of diode current Iz in
6. Plot a curve between diode voltage Vz and diode current Iz as shown in figure 4
(First quadrant) using suitable scale with the help of observation Table l. This
curve is the required forward characteristics of zener diode.
Diode
S. No. Diode current Iz (mA)
Voltage (Vz)
1. 0.0V
2. 0.lV
3. 0.2V
4. 0.3V
5. 0.4V
6. 0.5V
7. 0.6V
8. 0.7V
9. 0.8V

AB01
To plot Reverse characteristics of a Zener diode proceed as follows

2. Connect Ammeter between test point 7 and 8 to measure diode current Iz (mA).
3. Connect one voltmeter between test point 1 and 9 to measure voltage Vz diode
zero to 12V in step and measure the corresponding values of diode current Iz in
6. Plot a curve between diode voltage Vz and diode current Iz as shown in figure 4
(third quadrant) using suitable scale with the help of observation Table 2. This
curve is the required Reverse characteristics of Zener diode.
Diode
S. No. Diode current Iz (mA)
Voltage (Vz)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

AB01
Experiment 3
Objective:
Study of characteristics of Light emitting diode (LED) in
1. Forward bias
2. Reverse bias
Equipments Needed:
1. Analog board of AB01
Circuit diagram:
Circuit used to plot different characteristics of Light Emitting Diode (LED) is shown
in figure 9.
Figure 9
Procedure:
To plot forward characteristics proceed as follows:
2. Connect Ammeter between test point 4 and 8 to measure diode current ID (mA).

AB01

zero t o maximum in steps and measure the corresponding values of diode
current ID in an observation Table 1.
6. Also consider the effect on light intensity with the change in diode voltage and
diode current.
using suitable scale with the help of observation Table 1. This curve is the
required forward characteristics of Light emitting diode.
Diode
S. No. Diode current ID (mA)
Voltage(VD)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

AB01
To plot Reverse characteristics proceed as follows:

2. Connect Ammeter between test point 5 and 8 to measure diode current ID(A)
3. Connect one voltmeter between test point 1 and 9 to measure voltage VD diode.
zero to maximum in steps and measure the corresponding values of diode
current 1D in an observation Table 2.
6. Plot a curve between diode voltage VD and diode current 1D as shown in figure 5
(Third quadrant) using suitable scale with the help of observation Table 2. This
curve is the required forward characteristics of Light emitting diode.
Diode
S. No. Diode current ID (A)
Voltage(VD)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

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Indian Institute of Science Education and Research Bhopal

Physics Laboratory Manual

UG Physics Laboratory, I Floor Academic Building - III,

1. CE (NPN) Transistor Characteristics and Amplifier

2. Clippers and Clampers

3. Digital to Analog and Analog to Digital Convertor

5. Logic Gates/ Binary Adder and Subtractor

7. Operational Amplifier (Integrator/Differentiator)&

8. P-N Junction Diode, Zener Diode and Light Emitting

AB04 Common Emitter NPN Transistor Characteristics

Input Input current IB(A) at constant value of

To plot output characteristics proceed as follows:

Output Output current IC (mA) at constant value of

To plot constant current transfer characteristics proceed as follows:

AB15 Common Emitter Amplifier

Transistor as an Amplifier in CE Configuration :

Load Resistance (RO) :

Operating Parameters of Common Emitter Amplifier :

Type of Amplifier Circuit

Phase reversal No Yes No

Voltage Gain High Highest Nearly Unity

Input Impedance Lowest Moderate Highest

Output Impedance Highest Moderate Lowest

Current Gain Nearly unity High () Highest (+ 1)

AB88 Diode Clippers

How the circuit works ?

Negative series clipper Figure 4a

Positive series clipper Figure 4b

Biased positive clipper Figure 5a

Biased Negative clipper

AB89 Diode Clamper

How the circuit works ?

DB22 Analog to Digital Converter

Wide power supply range :

Vdd = +12V, Vss = Gnd

DAC08 (8 Bit DAC) :

Vs = 15V, IREF = 2.0 mA

Absolute Maximum Ratings :

Vss = +3V to +12V, VDD Gnd

DB16 Digital to Analog Converter

R-2R Ladder DAC

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D3, D2, D1, D0 is digital input.

Truth Table for D3 is MSB

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Pin out diagrams V+ = +12V, V- = -12V

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AB08 FET Characteristics

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Output Output Drain current ID (mA) at constant Value

8. Rotate potentiometer P1 fully in Counter Clockwise direction.

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Output Drain current ID (mA) at constant value of input

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DB01 Logic Gates

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