2015 International Conference on Electrical Information and Communication Technology (EICT)
A Survey on Interconnect Encoding for Reducing
Power Consumption, Delay, and Crosstalk
Sujan Kumar Saha1, Bulbul Ahmed2, Jiangjiang Liu3
1,2Department of Electrical Engineering and 3Department of Computer Science
Lamar University
Beaumont, USA
Email: 1ssaha@lamar.edu, 2bahmed@lamar.edu, and 3jane.liu@lamar.edu
AbstractWith the advancement of technologies, interconnect
circuits are shrinking dramatically. Capacitances of
interconnects are increasing due to minimized wire size and inter
wire spacing. As a result, interconnect power consumption, delay,
and crosstalk are increasing significantly, which is affecting
overall interconnect performance. Various techniques such as
buffer insertion, shielding, skewing, and encoding are used to
minimize delay, crosstalk, and power consumption. This paper
studies a set of encoding methods for reducing power
consumption, crosstalk, and delay, and also presents a
comprehensive comparison and analysis of these encoding
techniques.
Keywordsencoding, power, delay, bus invert, shielding,
weighted code mapping.
I. INTRODUCTION
In Deep Sub-Micron (DSM) technology, the VLSI circuit
components are now at the size of nanometer range. Along
with the components, interconnects are also shrinking very
quickly due to aggressive scaling down of technology. In this
case, wire width is getting thinner but height is not decreasing
so rapidly to keep resistance constant. As a result, the ratio of
height to width is increasing prominently. Lots of research has
been accomplished on low power circuit designs, focusing on
the reduction of circuit component power consumption. But,
now in today's Deep sub-Micron technology, interconnect
energy is no longer ignorable. Due to the dense placement of
interconnects, coupling capacitance is increased, which
dominates the self capacitance of the wire. Consequently
problems with crosstalk delay, noise and power consumption
arise which affects the overall circuit performance.
Coupling capacitance contributes to extra power
consumption because of the different switching pattern of the
adjacent bus. Opposite transition between two adjacent buses
causes worst case cross talk and produces a large delay and
energy consumption in the interconnect. Different techniques
have been applied to minimize crosstalk, delay, and power
consumption. Some are at the circuit level and some are at the
architecture level. Among these, bus encoding is a widely used
method. This method is used to change the bit patterns of the
data so that self-transitions, charging, discharging, and toggle
transitions are reduced, which will eventually minimize power
consumption, delay, and also crosstalk in some instances. In
this paper, a set of encoding methods will be discussed to
reduce power, and the rest of the methods are for minimizing
978-1-4673-9257-0/15/$31.00 2015 IEEE
12
delay and crosstalk. All methods are explained in Section II,
Section III contains results reported by corresponding papers
and a comprehensive comparison, followed by the conclusion
in Section IV.
II. SELECTED BUS ENCODING METHODS
A. Bus Invert
Bus Invert encoding method [1] is one of the most widely
used encoding methods. This encoding method is mainly
focused on reducing the number of transitions. According to
the method, only one control bit is needed to indicate the
inversion. To implement Bus Invert encoding, first of all, we
need to calculate the hamming distance between the data of
two consecutive cycles. Hamming distance between the two
data strings of length n is the total number of positions at which
the corresponding data are different. If the hamming distance is
greater than n/2 where n is the number of the bus width or
length of data string, set control bit=1 and invert all the bits of
next cycle original data. If the hamming distance is less than
n/2, then set control=0 and keep the data value as it is in the
next cycle. At the receiver side, the contents of the bus must be
conditionally inverted according to the control bit.
In the example figure 1, there are 9 transitions between
current cycle data and next cycle original data, which have
been marked as light blue. So, hamming distance is 9. In the
other 7 positions, the data is same as it is in the current cycle.
As data length is 16 and hamming distance is greater than 8,
control bit will be equal to 1 and all the bits of next cycle
original data will be inverted. After the inversion hamming
distance is 7. Thus, due to inversion of the next cycle bits, 2
self-transitions have been reduced.
As only one control bit is used to transfer the encoding
information, area overhead is very small. Also this method
doesnt require an extra clock cycle. Yet here, only self-
transition is reduced, but crosstalk due to coupling capacitance
Current
0 1 1 0 1 0 1 0 1 1 0 0 0 0 1 1
cycle data
Next cycle
1 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0
original data
Next cycle
1 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1
encoded data
Fig.1. Bus Invert Encoding (bus width 16 bit, control bit 1 )

between adjacent wires is not considered.
B. Odd Even Invert
Odd Even Invert [2] encoding is a modified version of Bus
Invert encoding. This method is also focused on reducing the
number of transitions. As the number of transition is directly
proportional to power, it also reduces power consumption of
interconnects. The authors of this paper mentioned two
encoding approaches, Simple Odd Even Invert and Calculated
Odd Even Invert.
Initially there are some common features of these two
encoding methods. First, we have to divide bus lines into two
groups, odd lines and even lines. Bus lines are selected
according to their position. Odd position lines go to the odd
group and even position lines go to the even group. For this
encoding method, two extra control lines are required to send
the encoding information. There are four possible cases with
two control lines: no bus lines are inverted (00), only odd lines
are inverted (10), only even lines are inverted (01), and all
lines are inverted (11). We need to transfer the bits over the
invert-lines according to what we have done. This information
needs to be transferred to decode the original bits. In the next
subsection, two encoding approaches have been described
separately.
1) Simple Odd Even Invert: To implement simple Odd-
Even Bus Invert, only self transitions are considered. Coupling
transition is not considered in this method. Coupling transiton
is the impact of one wire due to the transition of the adjacent
wire. According to this encoding, if the number of self-
transitions on the odd lines is more than or equal to the half of
odd lines, the odd lines are inverted, and if the number of self-
transitions on the even lines is more than or equal to the half
of even lines, the even lines are inverted. Following the
example of figure 3 makes it easy to understand the encoding.
In the example, there are 4 transitions in odd lines and 5
transitions in even lines. So all bus lines have been inverted
and control bits are 11. After inversion, there are 7 transitions,
which is less than the original number of transitions. Also, it
should be noted that there was one toggle before inversion.
After the inversion, the toggle is removed automatically. Still,
if there is any toggle, then we need to apply the two phase
transfer method to remove the toggle. The two Phase transfer
method delays one of the two adjacent lines by a half cycle.
So, this encoding method introduces some delay to eliminate
toggle. The amount of delay depends on the number of toggles
after inversion.
C0 C1
No Invert 0 0
Even Invert 0 1
Odd Invert 1 0
Both Invert 1 1
Fig.2. Control Bit of Odd Even Encoding
13
Current
cycle data
0 1 1 0 1 0 1 0 1 1 0 0 0 0 1 1
Next cycle
original data 1 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0
Next cycle
encoded data 1 1 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1
Fig.3. Simple Odd Even Invert Encoding (bus width 16 bit, control bit 2)
2) Calculated Odd Even Invert: Calculated Odd-Even Bus
Invert [2] encoding is slightly different from Simple Odd-
Even Bus Invert encoding. In Simple Odd Even Invert, only
self transitions have been considered. Whereas in Calculated
Odd Even Invert, coupling transitions are considered.
According to figure 2, there can be four types of inversions.
For each of the inversion types, the total number of coupling
transitions (charging and discharging) [2] are calculated
between current cycle data and next cycle original data. Then
that inversion type is selected for encoding which has the least
number of coupling transitions. For example, in figure 4,
current and next cycle data are 0110101011000011 and
1101011010011010. For 00 type inversion, the total coupling
transition is 20, for 01 type its 11, for 10 type its 15, and for
11 type its 20. In this case it has been considered that one
toggle transition is equivalent to 4 coupling transitions. As we
get an 11 transition for 01 type inversion, which is smallest, it
is selected as encoded data.
C. Temporal and Shielding Coding (TSC)
The encoding approach of Sainarayanan et al. [4] is useful
for eliminating crosstalk delay. Table I shows crosstalk
induced delay categorization of a wire due to two adjacent
lines. In this table represents 10 transition, represents
01 transition, and means there is no change of data bit.
Also here, Cg is ground capacitance, R is total resistance of
wire, Cc is coupling capacitance, and is the ratio of Cc to Cg.
The encoding method is developed to eliminate crosstalk class
5 and 6. According to this approach, actual data to be
transmitted is divided into groups of 3 bits. Encoded data is
transmitted in the first temporal cycle and the information of
encoding and shielding is transmitted in the 2nd temporal
cycle. So every 3-bit real data is encoded as 2 consecutive
groups of 3-bit data to be transmitted in two consecutive
temporal cycles. To avoid worst-case crosstalk in boundaries of
every 3-bit group, 0 is transmitted between two adjacent 3-bit
groups as a shielding bit. So this approach needs an extra 1-bit
line after every 3-bit group. That's 8-bit data will be encoded as
10-bit data length.
For example, a data dt-1 = 101 0 100 0 00 is the encoded
data transmitted at time "t-1", and data dt = 01001101 is
original data to be transmitted at time "t". Before encoding
Current
0 1 1 0 1 0 1 0 1 1 0 0 0 0 1 1
cycle data
Next cycle
1 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0
original data
Next cycle
encoded data 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1
Fig.4. Calculated Odd Even Invert Encoding (bus width 16 bit)
 TABLE I. CROSSTALK CATEGORIZATION
CC Delay Pattern of switching
1 0 , , , , ,
, , ,
2 CgR , 1 1 1 0 0 1
3 CgR(1+) , , ,
4 CgR(1+2) , ,,, ,
5 CgR(1+3) , , ,
6 CgR(1+4) ,
this, both data will be checked for crosstalk class according to
the crosstalk categorization table. As in this case, the crosstalk
class is greater than 1, so 3-bit groups will be inverted as the
encoded data 101 0 100 0 01 and transmitted in the first
temporal cycle. The 2nd temporal cycle contains the encoding
and shielding information. If the data is inverted, in the 2nd
temporal cycle in every 3 bit groups, 3rd bit will be set to 1;
otherwise it will be 0, and the first and second bits are kept
same to the 1st temporal cycle so that there is no transition. So,
for the encoded data, 2nd temporal cycle data will be 101 0 101
0 01. Finally, given data dt will be encoded as 2 consecutive
temporal cycle data.
This method is further modified by adding two extra bit
lines into both sides of the shielding bit. These extra bits are
inserted in such a way so that the transition is same as the
boundary bits of the 3-bit group. This modified approach can
eliminate crosstalk class 5, 6, and also crosstalk class 4 as well
as any transition pattern that is , , , , , .
However these methods do not include inductance effect,
increase bit lines in modified approach and eventually increase
the area overhead.
D. Temporal Crosstalk Shielding(TCS)
Najeeb et al. [5] reduces both power and crosstalk delay by
reducing bus width and using the temporal shielding approach.
Original data is divided into several blocks before encoding.
Then the data is encoded into two data packets and transmitted
over two consecutive clock cycles. For example, the original
data of n bits is divided into k bit blocks, then the number of
groups are now n/k and encoded into two m bit data blocks.
This is done in such a way so that n is a multiple of k and m is
less than k. As the encoded bit m is less than k, active bus
width is reduced. Keeping bus area constant, spacing among
wires is increased so that coupling capacitance decrease. This
Current cycle data 1 0 1 1 0 0 0 0
Next cycle original data 0 1 0 0 1 1 0 1
Next cycle encoded data 1 0 1 0 1 0 0
Encoding information 1 0 1 0 1 0 1
Fig.5. Temporal and Shielding Coding (bus width 8 bit, shielding bit 2)
Original Dala Block D1 1 1 1 0 0 0 0 0
Original Data Block D2 1 0 1 1 1 1 0 1
Encoded Data Block of
D1 TP1
1 0 1 0 0 1
Zero Vector 0 0 0 0 0 0 TP2
1 1 0 1 1 1
Encoded Data Block of
D2 TP3
1 1 0 0 1 1
Fig.6. Temporal Crosstalk Shielding (bus width 8 bit)
method is also developed to eliminate crosstalk in class 5 and 6
of Table I.
If data D1 was transmitted at time Tt-1 and D2 is to be
transmitted at Tt, D2 is encoded according to following Table
II proposed by this approach. Here each 4-bit block is encoded
into two 3-bit blocks. As the original data block is encoded into
two data blocks, 4 cycles are needed to transmit two original
data, and for these 4 transmissions, there are 3 transitions. The
transition between the first transmission to the second one is
named Transition Pattern 1(TP1), between 2nd and 3rd is TP2,
and between 3rd and 4th is TP3. The Encoding Table is formed
in such a way that there is no opposite transition between two
adjacent blocks. Thus at TP1 and TP3, crosstalk class 5 and 6
are eliminated. This crosstalk may only happen at TP2. A
crosstalk analyzer is used to detect crosstalk class 5 and 6; if
found, then it sends a crosstalk identification vector before the
next data is transmitted. To eliminate class 5 and 6 crosstalk, a
Zero vector is transmitted between those affected data. At the
receiver end, according to the decode bit, the decoder detects
whether it receives zero vector or useful data. If zero vector is
received, then it is discarded, and if it receives other than zero
vector, the data is stored and using stored data and bus data, the
original data is recovered. This approach is efficient for
addressing bus delay reduction because there is less crosstalk
and it improves power efficiency for the data bus.
E. Variable Cycle Transmission with Hybrid Spatial
Temporal Redundancy (VCT_HSTR)
Zhang et al. [6] attempted to reduce both energy and delay.
Thats why the encoding method proposed in [6] combines
Weighted Code Mapping (WCM) [13] with temporal
redundancy. The Weighted Code Mapping focuses on
reducing energy, whereas Temporal Redundancy reduces
delay. The WCM algorithm relies on probability distribution of
the data pattern. All patterns do not have the same probability
of occurring. Suppose for the data set {00, 01, 10, 11}, the
probability set is {0.1, 0.4, 0.4, 0.1}. Each value of the
probability set represents the corresponding probability of the
data value. So, the more probable data is mapped to a code
0 0 1 word, which has less number of transitions among the bits. The
authors also mentioned that one easy way of getting WCM
0 0 1 code is to perform bitwise XOR operation between two
consecutive cycle data.
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 TABLE II. TEMPORAL CROSSTALK SHIELDING ENCODING TABLE

4-bit 3 bit 4-bit 3 bit 4-bit 3 bit 4-bit 3 bit

Original data Encoded Original data Encoded Original data Encoded Original data Encoded
data data data data
0000 001 0100 011 1000 100 1100 111
001 001 100 001
0001 001 0101 011 1001 100 1101 111
011 011 110 011
0010 001 0110 011 1010 110 1110 111
101 111 000 101
0011 001 0111 100 1011 110 1111 111
111 000 110 111

After getting the code words, the delay between two
consecutive codes are measured using the crosstalk delay types
mentioned in Table I. If the delay is greater than type 4, then a
temporal redundant code is inserted between the code words.
Before doing this, it also checks whether the delay is type 6 or
not. If the delay is type 6, then the 2nd code word is inverted;
otherwise its not. The temporal redundant code is either all
zeros or all ones. It is decided based on the total delay of three
consecutive codes (current code, temporal code, and next
code). By using the following example of figure, it will be easy
to understand the encoding method. Suppose two consecutive
WCM codes are 101111000 and 010001000. As the delay
between the codes is type 6, the 2nd one is inverted. So now
the 2nd one is 101110111. Then the total delay of the two sets
{101111000, 000000000, 101110111} and {101111000,
111111111, 101110111} is measured, where 000000000 and
111111111are temporal codes. The set which has less delay is
selected as encoded data. In this example, the set {101111000,
000000000, 101110111} has less delay. So this is the encoded
data.
F. Opposite Transition Forbidden Weighted Code Mapping
(OTF_WCM)
This method [6] is a slightly modified version of WCM
coding. The original WCM encoding method doesnt guarantee
to eliminate crosstalk type 5 and 6. This encoding method
generates a WCM codebook that doesnt have an opposite
transition pattern. As a result, all crosstalk type 5 and 6 and
some of type 4 are eliminated. If W denotes the set of code
words of n bits, W can be represented as W ={w | w =
Current Cycle WCM Code 1 0 1 1 1 1 0 0 0
Next Cycle WCM Code 0 1 0 0 0 1 0 1 0
Fig. 7. Transition between two WCM code
Current Cycle WCM Code 1 0 1 1 1 1 0 0 0
Temporal Code 0 0 0 0 0 0 0 0 0
Next Cycle WCM Code 0 1 0 0 0 1 0 1 0
Fig. 8. VCT_HSTR Encoding (bus width 9 bit)
a1a2aiai+1.an, ai=0,1}, where i denotes the index of the
opposite transition bit lines. The W will be an opposite
transition forbidden (OTF) codebook if it doesnt have 2
transitions with each other. In the original WCM coding, the
codes are selected in such a way that transition energy is
minimized.
According to this encoding method, after selecting WCM
codes, each code is checked whether it is OTF or not. If it is
OTF, then it is selected as a mapping code for a particular data
pattern. As the codes of OTF codebook are guaranteed not to
have type 5 and 6 crosstalk delay, it can be said that this
encoding method is optimized for both energy and delay.
G. Encoding for Crosstalk
Verma et al. [7] proposed an encoding method to eliminate
worst-case crosstalk by reducing actual data bit lines. Required
components are counter, controller, comparator, and register to
design the encoder. Counter counts the number of 0s and 1s in
input data lines and feeds these two inputs to the controller.
Controller output follows the number, which one is higher. For
example, if the number of 1s is greater than the number of 0s,
controller output is set to 1 and vice versa. Then controller
output is fed to the comparator and also to the decoder. Actual
data lines are fed into the comparator along with the controller
output. In the comparator, the controller output is compared
with every bit in actual data lines to get the inverted bit
positions.
For example, in the 8-bit data 10110101, the number of
1s is 5, which is greater than the number of 0s, which is 3. The
controller output is set to 1 and is fed into the comparator along
with original data to be compared. XOR operation between
controller output and original data is performed at comparator,
and the positions where controller output does not match are
the inverted bit positions. In this example, inverted bit positions
are 1, 3, and 7 if we set the index from LSB to MSB. So, in
binary form, 001, 011, and 110 are stored in three registers and
then transferred to the decoder for retrieving original data.
Although this method reduces actual bus width, for the use of
register, area overhead increases and to transfer register bits, an
extra clock cycle is introduced.
H. Crosstalk Quantitive Approach
In the previous encoding methods, the inductive effect was
not considered. As operating frequency is increasing in recent
days, the inductance of the wires is also adding noise and

15
 between the next cycle original data and next cycle inverted
Current Cycle Data 0 0 1 1 0 1 0 1 0
data. And the lesser one is selected to transfer to the bus using
the MUX. The comparator output is used as the selector of
Next Cycle Non- MUX. So, for the above example, inverted data will be selected
inverted data 0 1 1 0 1 0 1 1 0 as encoded data.

Current Cycle Data 0 0 1 1 0 1 0 1 0 III. ANALYSIS AND COMPARISON OF ENCODING METHODS

Next Cycle Non-
inverted data 1 0 0 1 0 1 0 0 1
Fig.9. Crosstalk quantitative approach
delay. Ruan et al. [8] considered the inductance effect as well
as capacitance to determine the encoded data. They used the
RLC model instead of the RC model to represent bus lines. Just
like the two capacitances (self and coupling), there are also two
kinds of inductances, self-inductance and mutual inductance.
Total inductance is the summation of self-inductance and
mutual inductance between wires. But capacitance and
inductance effects are not dominant at the same time. When
data of two adjacent wires changes towards the opposite
direction (zero to one and one to zero), the capacitance effect
dominates over the inductance effect. On the other hand, when
data of adjacent lines changes towards the same direction (both
zero to one or one to zero) the inductance effect dominates over
the capacitance effect. Thats why both effects have been
considered to define the cost function. The cost function is the
summation of the toggle number multiplied by 2 and the
maximum of switch up and switch down. Switch up means
01, and switch down means 10.
Cost = Toggle#2+Max(Switchup #,Switchdown #)
The major components of the encoder are pattern generator,
two cost estimators, one comparator, one MUX, and one Latch.
Using the Latch, current cycle data is transferred to both cost
estimators. On the other hand, the pattern generator generates
two data for two cost estimators.
One is non-inverted next cycle data with control bit 0, and
the other one is inverted next cycle data with control bit 1.
These two data are transferred to the two cost estimators. Thus,
using the current cycle and next cycle data, the cost estimator
calculates the cost according to the above mentioned formula.
The following example of 8-bit data illustrates the encoding
method completely. After calculating the cost, these are
transferred to the comparator to determine which one costs less
In the previous section, we have explained the algorithm
and working principle of all the encoding methods. In this
section, the important results reported by the authors and their
comparison will be described. In Table III, the power,
crosstalk, and delay reduction of all the methods have been
presented. The area overhead, power consumption, delay, extra
control line, and cycle number induced by the codec are also
mentioned. From the table, we can say that, the Temporal
Crosstalk Shielding and VCT_HSTR encoding approaches
improve power efficiency of the bus significantly. They can
reduce power consumption up to 46% and 45.47%. On the
other hand, Temporal and Shielding Coding and OTF_WCM
are more efficient in reducing delay. Both of the methods can
reduce delay by about 49%.
Most of the methods didnt measure crosstalk separately.
Only the last two methods showed crosstalk reduction. Among
these, Encoding for Crosstalk can reduce crosstalk by 35% to
40% and Crosstalk Quantitative Encoding can reduce up to
14%. On the other hand, in Temporal and Shielding Coding
(TSC) and Temporal Crosstalk Shielding (TCS), codec area
and codec induced delay has been measured directly in m2
units and time units. TSC takes less area and induces less
delay compared to TCS. The other two methods, VCT_HSTR
(1) and OTF_WCM measured area in terms of a NAND gate
count. In Temporal and shielding coding, though power
reduction was not measured, codec power consumption is
1.1mW, which is less than the other methods, and there is no
need for an extra line for this encoding method. Again,
Temporal Crosstalk Shielding can reduce the number of bus
line by 25%. This means for each 4-bit data, the encoded data
is 3-bit, but codec area and power overhead is higher than the
other methods. Though the OTF_WCM can reduce delay by
48.46%, it needs an extra 7 lines for a 16-bit wide bus. Most of
the encoding methods dont add extra cycles to transfer
encoded data. Only in TCS, VCT_HSTR, and Encoding for
Crosstalk methods, extra cycles are required to send encoded
data.

TABLE III. RESULT COMPARISON OF SELECTED ENCODING METHODS

Encoding Method Power Crosstalk Delay Codec Area Codec Codec Extra Extra
Power Induced Control Cycle
Delay Line
Bus Invert 25% - - - - - 1 0
Simple Odd Even Invert 32% - - - - - 2 0
Calculated Odd Even Invert 30% - - - 5% - 2 0
Temporal & Shielding Coding - - 22-49% 871m2 1.1mW 237ps 33.3% 1
Temporal Crosstalk Shielding 46% - 11% 2127.2m2 5.7mW 1.2ns -25% 1~2
VCT Encoding with HSTR 45.47% - 28.15% 200116 - - 2 0~1
OTF_WCM 38.46% - 48.46% 217147 - - 7 0
Encoding for Crosstalk - 35-40% - - - - 0 0~2
Crosstalk Quantitative Encoding 11-19% 11-14% 7-19% - 1.1-8.6 - 1 0

16

IV. CONCLUSION
In today's deep submicron technology, a significant amount
of power is consumed in interconnect due to crosstalk. In this
paper, we surveyed several methods for increasing energy and
delay efficiency in modern VLSI interconnects. Our study
shows differences, similarities, and specific ways of reducing
interconnect power consumption and delay among different
research works. Based on our survey, we tried to present a
comparative study of all methods. We selected some research
works accomplished over the past few years. Among them, we
classified 7 research works based on 8 criteria including power,
crosstalk, delay, codec area, codec power, codec induced delay,
extra control line, and extra clock cycle. Most of the techniques
we presented focus on power consumption reduction, and the
rest are based on delay reduction.
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