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VLSI Design EE-407


EE-10 OHT:
01
Max Marks: 30 1st April 2015
Time: 50 min

1. Tick the most appropriate answer (12)


I. Moore predicted that no. of transistors integrated on single
chip would be
a. Double every c. Double every
18-24 months 2 years
b. Increase d. Both a & b
exponentially
II. While fabricating CMOS on silicon wafer, following material
is used for insulation
a. Silicon di- c. Poly silicon
oxide d. Arsenic
b. Aluminum
III. While fabricating CMOS on silicon wafer, following material
is used for diffusion
a. Silicon di- c. Poly silicon
oxide d. Arsenic
b. Aluminum
IV. While fabricating CMOS on silicon wafer, following material
is used for gate fabrication
a. Silicon di- c. Poly silicon
oxide d. Arsenic
b. Aluminum
V. Diffusion can be done by using the technique of
a. CVD c. Spin coating
b. Ion d. Both a & b
implantation
VI. PMOS is fabricated by creating
a. P-well in N- c. P+ type
type substrate source & drain
b. P+ type in N substrate
source & drain d. None of above
in P substrate
VII. Which of the following is true
a. n>p c. n/p>1
b. n<p d. n/p>1
VIII. Which of the following, IC designer have freedom to
change?
a. Cox c. L
b. W d. n & p
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IX. Which of the following, IC designer can never change?


a. Cox c. L
b. W d. Both a & b
X. Primary benefit of CMOS technology over others is
a. Area efficient c. Power efficient
b. Fast switching d. Cost effective
XI. To which of the following, power dissipation of CMOS is NOT
linearly dependent
a. Switching c. Supply voltage
frequency d. Load
b. Gate capacitance
capacitance
XII. Reducing silicon area of a CMOS circuit reduces
a. Parasitic c. Current
capacitance driving
b. Delays capacity
d. Both b & c
e.
f.
2. A. For the following logic expression; design CMOS circuit whose
current driving capabilities are equal to that of a basic inverter
having (W/L)n= 4/2 & (W/L)p=10/2. * (10)
g.
h. F=AB+CD+E
i.
j. B. While making following assumptions/technology
specifications, calculate the power dissipation of resulting circuit.
(8)
k.
l. Assumptions:
m. Parasitic capacitance is negligible
n. Static power dissipation is negligible
o. Avg switching is 100 per second
p. The circuit is driving identical circuit at o/p
q. i.e. gate capacitance and load capacitance are same
r. Technology:
s. Process: 0.35m
t. n/p= 2.5
u. tox= 7.6x10-9m
v. ox= 35x10-12F/m
w. supply voltage: 5V
x. *WAQ