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Review Questions . What do RISC and CISC stand for? 2. True or false. The CISC architecture executes the vast majority of its instruc- tions in 2, 3, or more clock cycles, while RISC executes them in one clock. 3. RISC processors normally have a (large, small) number of general-pur- pose registers. 4. True or false. Instructions such as “ADD R16, ROMmemory” do not exist in RISC microcontrollers such as the AVR. 5, How many instructions does the ATmega have? 6. True or false. While CISC instructions are of variable sizes, RISC instructions are all the same size. 7. Which of the following operations do not exist for the ADD instruction in RISC? (a) register to register (b) immediate to register (c) memory to memory 8. True or false. Harvard architecture uses the same address and data buses to fetch both code and data. SECTION 2.10: VIEWING REGISTERS AND MEMORY WITH AVR STUDIO IDE The AVR microcontroller has great tools and support systems, many of them free or inexpensive. AVR Studio is an assembler and simulator provided for free by Atmel Corporation and can be downloaded from the web- site. See for tutorials on how to use the AVR Studio assembler and simulator. Many assemblers and C compilers come with a simulator. Simulators allow us to view the contents of registers and memory after executing each instruction (single-stepping). It is strongly recommended to use a simulator to single-step some of the programs in this chapter and future chapters. Single-stepping a pro- gram with a simulator gives us a deeper understanding of microcontroller architec- ture, in addition to the fact that we can use it to find the errors in our programs. Figures 2-21 through 2-23 show screenshots for AVR simulators from AVR Studio. See the following website for a tutorial on using AVR Studio: http:/ CHAPTER 2: AVR ARCHITECTURE AND ASSEMBLY LANGUAGE 97