1, JANUARY 2000
AbstractThis paper describes the laboratory implementation late the parallel distributed nature of NNs. The simulation re-
and real-time test results of a new neural network (NN) based dig- sults presented may be said to be close to the expected in a phys-
ital differential relay used for detecting faults and classifying in- ical system as the generator model represents fairly closely the
ternal faults in the stator winding of synchronous generators. De-
tails of the software written to enable the operation of the relay are physical system [6] and the sequential algorithm can obtain the
described. Behavior of the NN based relay is observed and the ex- same output of a dedicated NN hardware, except for a longer
perimental results are presented. computation time [7].
Index TermsDigital differential protection, generators, micro- Computer simulation is still different from the real physical
processor based instrument, neural networks. system since the operating environment of the physical system
is not ideal, due to the existence of noise, current transformer
(CT) mismatches and CT saturation. Therefore, after theoret-
I. INTRODUCTION
ical development and computer simulation, the next desirable
in the field current during a fault help the FNN, used for fault of two parts. The first part is a FNN that classifies the phases
detection, to differentiate between the three generator states. as faulty or healthy. The second part is a simple fault classifier
Details of the structure and method of training of the proposed confirmation logic that averages the FNN output.
NN based differential relay has been described in [3]. In this The inputs to the FNN are the line-side ( , , )
section a brief description of the function and structure of the and the neutral-end ( , , ) currents, each current being
important modules is given. represented by four consecutive samples making a total of 24
inputs to the FNN. Samples of the field current are not used in
A. Fault Detector Module this module as they do not help in classifying the phases. The
The FNN based fault detector module is the main part of the FNN has three layers, with 14 tan-sigmoid neurons in the first
differential protection scheme. Its function is to differentiate be- hidden layer, 7 tan-sigmoid neurons in the second hidden layer
tween three generator states, namely the normal operation state and 3 log-sigmoid neurons in the output layer. Each neuron in
(NOS), external fault state (EFS), and internal fault state (IFS). the output layer is responsible for a fault in one of the phases. As
The inputs to the FNN are 7 currents, each current being rep- an example, suppose there is an internal fault in phase , then
resented by five consecutive samples, making a total of 35 in- the output of phase neuron will be mapped to a value greater
puts (the sampling rate is 20 samples/cycle, 1200 Hz). The FNN than 0.95, indicating that this phase is faulty, while the outputs
has three layers, with 18 tan-sigmoid neurons in the first hidden of the two other neurons will be less than 0.1, indicating that
layer, 10 tan-sigmoid neurons in the second hidden layer and these two phases are healthy.
3 log-sigmoid neurons in the output layer. Each neuron in the The fault classifier logic does not indicate that a certain phase
output layer is responsible for one fault type, except the first is faulty except after confirming the output of the FNN fault
one that signals the normal state. Therefore depending on the classifier. The classifier confirms the presence of an internal
state of the generator one output is mapped to a value greater fault in one of the phases by averaging five consecutive outputs
than 0.9 while the two others are less than 0.1. The FNN was of each of the three output neurons. So, for the fault classifier
trained in a static manner using the back propagation algorithm logic to indicate that there is an internal fault in phase , the
[4]. conditions specified in (4) should exist for 3 consecutive sam-
ples. For a two phase fault, for example in phases and , the
B. Trip Logic Module relay would not indicate that these two phases are faulty unless
the boundary conditions of (5) exist for 3 consecutive samples
The trip logic module issues a trip signal only when it con-
firms that the output of the fault detector module is either an and and (4)
internal fault or a prolonged external fault that may affect the
generator. In order to confirm the presence of a certain state
(normal, external or internal), the fault logic module averages
six consecutive outputs of each of the three output neurons. The and and (5)
generator is considered to be operating at its normal state if (1)
where , , and are the averaged outputs
is valid. A trip decision is taken in the case of an internal fault
of phase , phase , and phase neurons.
if the conditions specified in (2) exist for 3 consecutive samples
C. Hardware Structure
Current transformers, having turns ratio of 50/5 A, are used
in this laboratory setup with current shunts (5 A/100 mV) con-
nected to their secondaries, Fig. 2. An additional current shunt (2
A/100 mV) is connected in the field circuit, to enable recording
the field current. As the produced voltage signals are in the milli-
volt range, it is essential to amplify the signals before converting
them to digital form. A 7-channel amplifier is used for amplifi-
cation purposes. To avoid aliasing problems, an antialiasing low
pass filter, with a cut-off frequency of 600 Hz, is installed.
A data acquisition system (DAS) is connected to the low pass
filter output as shown in Fig. 2. The DAS is connected to a dig-
ital signal processing (DSP) board via two links. One link is for
the multiplexing command and the other for the analog voltage
signals to pass on to the analog to digital converter (A/D) of
the DSP board. The DSP board contains a Texas Instruments
TMS320C30 DSP chip. The board is mounted inside an 80 486
PC which is equipped with corresponding development and de-
bugging tools. Fig. 2. Hardware structure.
D. Software Structure
The relay software, running on DSP, is developed in C lan-
guage. In addition, a communication routine, running on PC, is
also developed to further facilitate the implementation process.
The PC communication routine functions as a man machine in-
terface. It first initializes vectors and flags for DSP-PC com-
munication. Then, it loads the DSP code into the chip. It then
reads the FNNs weights and biases and sends them to the DSP
chip through a dual access RAM (DARAM). After the incep-
tion of the main relay loop by the DSP, the PC communication
routine reads the outputs of the fault detector module and trip
logic module. It should be noted that once the relay detects an
internal fault, it activates the fault classifier module, and sub-
sequently the communication routine reads the outputs of the
fault classifier module. Once the DSP program is stopped, as
explained below, the output data is saved in a file.
The DSP program first initializes the vectors and flags for
DSP-PC communication then it reads the FNNs parameters
from DARAM, reset all counters and set all the scales. The set- Fig. 3. Flow chart of the main relay loop of the DSP program.
ting of the scales is very important as all inputs should have
a value between 1, so they can be processed by the FNNs. input signal is done at the beginning of each intersampling pe-
After initializing the DAS and the sampling time counter, the riod. The DAS program is executed in about 0.12 ms. Following
DSP program enters the main relay loop. The relay then waits that, the main relay loop proceeds in the manner shown in Fig. 3.
for the DAS program to be executed. The DAS program is a very The DSP program is stopped if an internal fault is detected and
small program, which is also performed by the DSP board. In classified or if an external fault is detected, as indicated in Fig. 3.
this program multiplexing, A/D conversion and scaling of each The main relay loop, including the DAS program, is executed
MEGAHED AND MALIK: EXPERIMENTAL TESTING OF A NEURAL NETWORK BASED DIGITAL DIFFERENTIAL RELAY 83
in 0.76 ms. This time is well within the available intersampling Fig. 7. EFS, 3 phase at machine terminals with CT saturation, FI = 10.
time of 0.833 ms.
B. EFS Results
The DSP program, Fig. 3, allows for an external fault to per-
sist for 30 samples after its detection before it is stopped. In
other words, if the DSP board is connected to a circuit breaker,
which is not the case, a trip signal will be issued after 30 sam-
ples based on the detection of a prolonged external fault. All the
results presented in this section are up to the sample the DSP Fig. 8. IFS, pg at 100% of phase b, FI = 32.
84 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 15, NO. 1, JANUARY 2000
Fig. 9. IFS, pg at 50% of phase a, FI = 51. Fig. 10. IFS, pp at 100% of phase a and 100% of phase b, FI = 25.
program is stopped. In the figures presented in this paper the The results shown in Fig. 8 are for an internal single phase
term pg indicates a single phase to ground fault, ppg indicates a to ground fault at 100% of phase , and those in Fig. 9 are for
two phase to ground fault, pp means a phase to phase fault and a similar fault at 50% of phase . The relay tripping time is
FI is the fault inception time in samples. 89 samples (less than one half cycle) after fault inception and
The results shown in Fig. 5 are for an external single phase to classification takes 7 samples. The relay also clearly detected
ground fault occurring at the machine terminals. The NN based and classified internal phase to phase faults, as shown in Fig. 10.
relay clearly indicated the existence of an EFS. Current trans-
former mismatches are more appreciable during external faults V. CONCLUSIONS
involving more than one phase. The response of the NN based
relay to a phase to phase fault is shown in Fig. 6. It is shown that Implementation of the NN based relay in a laboratory envi-
the relay is not affected by CT mismatches, which can cause a ronment and real-time test results on a physical model power
conventional digital differential relay to maloperate. system are presented in this paper. The relay is implemented in
In this laboratory setup it has been found that a terminal 3 a real-time digital environment by means of a DSP board. The
phase fault causes CTs to saturate. Current transformer satu- real-time test results done indicate that the relay is always suc-
ration presents a problem to differential relays in general. The cessful in detecting any of the generator three states. The relay
response of the relay to a 3 phase fault at the machine terminals also performs very well in the presence of CT mismatches and
is shown in Fig. 7. The relay clearly indicated the existence of saturation. The FNN based modules are able to detect and clas-
an EFS. The only effect of saturation may be the fluctuations sify internal faults they have not been exposed to during training.
occurring, in the EFS and IFS neurons, for a couple of samples. Finally, the relay tripping time is half a cycle or less (8 to 10
However, the averaging scheme diminished these fluctuations samples) and classification time is also within half a cycle (7 to
and the tripping speed of the relay has also not been affected, 10 samples).
Fig. 7(b).
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