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8-Channel/4-Channel

Fault-Protected Analog Multiplexers


ADG508F/ADG509F
FEATURES FUNCTIONAL BLOCK DIAGRAMS
All switches off with power supply off ADG508F
Analog output of on channel clamped within power
supplies if an overvoltage occurs S1
Latch-up proof construction
Low on resistance (270 typical)
Fast switching times D
tON: 230 ns maximum
tOFF: 130 ns maximum
Low power dissipation (3.3 mW maximum) S8
Fault and overvoltage protection (40 V to +55 V)
1 OF 8
Break-before-make construction DECODER
TTL and CMOS compatible inputs

00035-001
APPLICATIONS A0 A1 A2 EN

Existing multiplexer applications (both fault-protected and Figure 1.


nonfault-protected)
ADG509F
New designs requiring multiplexer functions

S1A
GENERAL DESCRIPTION DA
The ADG508F and ADG509F are CMOS analog multi- S4A

plexers, with the ADG508F comprising eight single channels


and the ADG509F comprising four differential channels. These
S1B
multiplexers provide fault protection. Using a series n-channel,
DB
p-channel, n-channel MOSFET structure, both device and signal S4B
source protection is provided in the event of an overvoltage or
1 OF 4
power loss. The multiplexer can withstand continuous overvolt- DECODER
age inputs from 40 V to +55 V. During fault conditions with

00035-101
power supplies off, the multiplexer input (or output) appears as
A0 A1 EN
an open circuit and only a few nanoamperes of leakage current
Figure 2.
will flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal PRODUCT HIGHLIGHTS
sources that drive the multiplexer. 1. Fault protection. The ADG508F/ADG509F can withstand
The ADG508F switches one of eight inputs to a common output continuous voltage inputs from 40 V to +55 V. When a
as determined by the 3-bit binary address lines A0, A1, and A2. fault occurs due to the power supplies being turned off, all
The ADG509F switches one of four differential inputs to a the channels are turned off and only a leakage current of a
common differential output as determined by the 2-bit binary few nanoamperes flows.
address lines A0 and A1. An EN input on each device is used 2. On channel saturates while fault exists.
to enable or disable the device. When disabled, all channels are 3. Low RON.
switched off. 4. Fast switching times.
5. Break-before-make switching. Switches are guaranteed
break-before-make so that input signals are protected
against momentary shorting.
6. Trench isolation eliminates latch-up. A dielectric trench
separates the p and n-channel MOSFETs thereby
preventing latch-up.

Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 20012011 Analog Devices, Inc. All rights reserved.
ADG508F/ADG509F

TABLE OF CONTENTS
Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................5
Applications....................................................................................... 1 ESD Caution...................................................................................5
General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................6
Functional Block Diagrams............................................................. 1 Typical Performance Characteristics ..............................................8
Product Highlights ........................................................................... 1 Terminology .................................................................................... 10
Revision History ............................................................................... 2 Theory of Operation ...................................................................... 11
Specifications..................................................................................... 3 Test Circuits..................................................................................... 12
Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 15
Truth Tables................................................................................... 4 Ordering Guide .......................................................................... 17

REVISION HISTORY
7/11Rev. E to Rev. F
Deleted ADG528F ..............................................................Universal
Changes to Features Section and General Description Section . 1
Changes to Specifications Section.................................................. 3
Deleted Timing Diagrams Section ................................................. 4
Changes to Table 4............................................................................ 5
Added Table 5.................................................................................... 6
Added Table 6.................................................................................... 7
Replaced Typical Performance Characteristics Section .............. 8
Changes to Terminology Section.................................................. 10
Changes to Figure 27 and Figure 28............................................. 13
Changes to Figure 31...................................................................... 14
Changes to Theory of Operation Section.................................... 11
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 17
7/09Rev. D: Rev. E
Updated Format..................................................................Universal
Added TSSOP .....................................................................Universal
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 18
4/01Data Sheet Changed from Rev. C to Rev. D.
Changes to Ordering Guide ............................................................ 1
Changes to Specifications Table...................................................... 2
Max Ratings Changed ...................................................................... 4
Deleted 16-Lead Cerdip from Outline Dimensions .................. 11
Deleted 18-Lead Cerdip from Outline Dimensions .................. 12

Rev. F | Page 2 of 20
ADG508F/ADG509F

SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V 10%, VSS = 15 V 10%, GND = 0 V, unless otherwise noted.

Table 1.
B Version
Parameter +25C 40C to +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS + 1.4 V typ Output open circuit
VDD 1.4 V typ
VSS + 2.2 V typ Output loaded, 1 mA
VDD 2.2 V typ
RON 270 350 typ 10 V VS +10 V, IS = 1 mA;
390 max VDD = +15 V 10%, VSS = 15 V 10%
See Figure 21
RON Drift 0.6 %/C typ VS = 0 V, IS = 1 mA
On-Resistance Match Between
Channels, RON 3 % max VS = 10 V, IS = 1 mA
LEAKAGE CURRENTS
Source Off Leakage IS (Off ) 0.02 nA typ VD = 10 V, VS = +10 V;
1 50 nA max See Figure 22
Drain Off Leakage ID (Off ) 0.04 nA typ VD = 10 V, VS = +10 V;
ADG508F 1 60 nA max See Figure 23
ADG509F 1 30 nA max
Channel On Leakage ID, IS (On) 0.04 nA typ VS = VD = 10 V;
ADG508F 1 60 nA max See Figure 24
ADG509F 1 30 nA max
FAULT
Source Leakage Current IS (Fault) 0.02 nA typ VS = +55 V or 40 V, VD = 0 V, see Figure 25
(With Overvoltage) 2 2 A max
Drain Leakage Current ID (Fault) 5 nA typ VS = 25 V, VD = +10 V, see Figure 23
(With Overvoltage) 2 A max
Source Leakage Current IS (Fault)
(Power Supplies Off ) 1 nA typ VS = 25 V, VD = VEN = A0, A1, A2 = 0 V
2 A max See Figure 26
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 1 A max VIN = 0 or VDD
CIN, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS 1
tTRANSITION 175 ns typ RL = 1 M, CL = 35 pF;
220 300 ns max VS1 = 10 V, VS8 = +10 V; see Figure 27
tOPEN 90 ns typ RL = 1 k, CL = 35 pF;
60 40 ns min VS = 5 V; see Figure 28
tON (EN) 180 ns typ RL = 1 k, CL = 35 pF;
230 300 ns max VS = 5 V; see Figure 29
tOFF (EN) 100 ns typ RL = 1 k, CL = 35 pF
130 150
tSETT, Settling Time ns max VS = 5 V; see Figure 29
0.1% 1 s typ RL = 1 k, CL = 35 pF;
0.01% 2.5 s typ VS = 5 V

Rev. F | Page 3 of 20
ADG508F/ADG509F
B Version
Parameter +25C 40C to +85C Unit Test Conditions/Comments
Charge Injection 15 pC typ VS = 0 V, RS = 0 , CL= 1 nF; see Figure 30
Off Isolation 93 dB typ RL = 1 k, CL = 15 pF, f = 100 kHz; VS = 7 V rms;
see Figure 31
CS (Off ) 3 pF typ
CD (Off )
ADG508F 22 pF typ
ADG509F 12 pF typ
POWER REQUIREMENTS
IDD 0.05 0.2 mA max VIN = 0 V or 5 V
ISS 0.1 1 A max
1
Guaranteed by design, not subject to production test.

TRUTH TABLES
Table 2. ADG508F Truth Table 1
A2 A1 A0 EN On Switch
X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8
1
X = dont care.

Table 3. ADG509F Truth Table 1


A1 A0 EN On Switch Pair
X X 0 None
0 0 1 1
0 1 1 2
1 0 1 3
1 1 1 4
1
X = dont care.

Rev. F | Page 4 of 20
ADG508F/ADG509F

ABSOLUTE MAXIMUM RATINGS


TA = 25C unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
Table 4. rating only; functional operation of the device at these or any
Parameter Rating other conditions above those indicated in the operational
VDD to VSS 48 V section of this specification is not implied. Exposure to absolute
VDD to GND 0.3 V to +48 V maximum rating conditions for extended periods may affect
VSS to GND +0.3 V to 48 V device reliability.
Digital Input, EN, Ax 0.3 V to VDD + 0.3 V or
20 mA, whichever occurs first
VS, Analog Input Overvoltage with VSS 25 V to VDD + 40 V ESD CAUTION
Power On (VDD = +15 V, VSS = 15 V)
VS, Analog Input Overvoltage with 40 V to +55 V
Power Off (VDD = 0 V, VSS = 0 V)
Continuous Current, S or D 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 40 mA
Operating Temperature Range
Industrial (B Version) 40C to +85C
Storage Temperature Range 65C to +150C
Junction Temperature 150C
TSSOP
JA, Thermal Impedance 112C/W
Plastic DIP Package
JA, Thermal Impedance
16-Lead 117C/W
SOIC Package
JA, Thermal Impedance
Narrow Body 77C/W
Wide Body 75C/W

Rev. F | Page 5 of 20
ADG508F/ADG509F

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS


A0 1 16 A1
EN 2 15 A2
VSS 3 ADG508F 14 GND
S1 4 TOP VIEW 13 VDD
S2 5 (Not to Scale) 12 S5
S3 6 11 S6
S4 7 10 S7

00035-004
D 8 9 S8

Figure 3. ADG508F Pin Configuration

Table 5. ADG508F Pin Function Descriptions


Pin No. Mnemonic Description
1 A0 Logic Control Input.
2 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4 S1 Source Terminal 1. This pin can be an input or an output.
5 S2 Source Terminal 2. This pin can be an input or an output.
6 S3 Source Terminal 3. This pin can be an input or an output.
7 S4 Source Terminal 4. This pin can be an input or an output.
8 D Drain Terminal. This pin can be an input or an output.
9 S8 Source Terminal 8. This pin can be an input or an output.
10 S7 Source Terminal 7. This pin can be an input or an output.
11 S6 Source Terminal 6. This pin can be an input or an output.
12 S5 Source Terminal 5. This pin can be an input or an output.
13 VDD Most Positive Power Supply Potential.
14 GND Ground (0 V) Reference.
15 A2 Logic Control Input.
16 A1 Logic Control Input.

Rev. F | Page 6 of 20
ADG508F/ADG509F
A0 1 16 A1
EN 2 15 GND
VSS 3 ADG509F 14 VDD
S1A 4 TOP VIEW 13 S1B
S2A 5 (Not to Scale) 12 S2B
S3A 6 11 S3B
S4A 7 10 S4B

00035-005
DA 8 9 DB

Figure 4. ADG509F Pin Configuration

Table 6. ADG509F Pin Function Descriptions


Pin No. Mnemonic Description
1 A0 Logic Control Input.
2 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4 S1A Source Terminal 1A. This pin can be an input or an output.
5 S2A Source Terminal 2A. This pin can be an input or an output.
6 S3A Source Terminal 3A. This pin can be an input or an output.
7 S4A Source Terminal 4A. This pin can be an input or an output.
8 DA Drain Terminal A. This pin can be an input or an output.
9 DB Drain Terminal B. This pin can be an input or an output.
10 S4B Source Terminal 4B. This pin can be an input or an output.
11 S3B Source Terminal 3B. This pin can be an input or an output.
12 S2B Source Terminal 2B. This pin can be an input or an output.
13 S1B Source Terminal 1B. This pin can be an input or an output.
14 VDD Most Positive Power Supply Potential.
15 GND Ground (0 V) Reference.
16 A1 Logic Control Input.

Rev. F | Page 7 of 20
ADG508F/ADG509F

TYPICAL PERFORMANCE CHARACTERISTICS


2000 2000
TA = 25C
VDD = +15V
1750 1750 VSS = 15V
VDD = +5V
1500 VSS = 5V 1500 TA = 125C
TA = 105C
TA = 85C
1250 1250
VDD = +10V TA = 25C
VSS = 10V
RON ()

RON ()
1000 1000
VDD = +15V
750 VSS = 15V 750

500 500

250 250

00035-011
00035-008
0 0
15 10 5 0 5 10 15 15 10 5 0 5 10 15
VD, VS (V) VD, VS (V)

Figure 5. On Resistance as a Function of VD (VS) Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures

1m 1m

100 VDD = 0V 100 VDD = +15V


VSS = 0V VSS = 15V
10 VD = 0V 10 VD = 0V
IS INPUT LEAKAGE (A)

IS INPUT LEAKAGE (A)

1 1
OPERATING RANGE
100n 100n

10n 10n
OPERATING RANGE
1n 1n

100p 100p

10p 10p
00035-009

00035-012
1p 1p
50 40 30 20 10 0 10 20 30 40 50 60 50 40 30 20 10 0 10 20 30 40 50 60
VS SOURCE VOLTAGE (V) VS SOURCE VOLTAGE (V)

Figure 6. Source Input Leakage Current as a Function of VS (Power Supplies Figure 9. Source Input Leakage Current as a Function of VS (Power Supplies
Off) During Overvoltage Conditions On) During Overvoltage Conditions

1m 0.3

VDD = +15V
100 VDD = +15V VSS = 15V
VSS = 15V 0.2
VS (VD) = 10V
10 VD = 0V TA = 25C
LEAKAGE CURRENTS (nA)
ID INPUT LEAKAGE (A)

1 0.1

100n
ID (OFF)
0.0
10n
IS (OFF)
1n 0.1
OPERATING RANGE
100p
0.2 ID, IS (ON)
00035-013

10p
00035-010

1p 0.3
50 40 30 20 10 0 10 20 30 40 50 60 14 10 6 2 2 6 10 14
VS SOURCE VOLTAGE (V) VS, VD (V)

Figure 7. Drain Output Leakage Current as a Function of VS (Power Supplies Figure 10. Leakage Currents as a Function of VD (VS)
On) During Overvoltage Conditions

Rev. F | Page 8 of 20
ADG508F/ADG509F
100 0
TA = 25C
VDD = +15V
VDD = +15V
VSS = 15V 20 VSS = 15V
VD = +10V
10
LEAKAGE CURRENTS (nA)

VS = 10V

OFF ISOLATION (dB)


40
ID (OFF)

1 60
ID (ON)

80

0.1 IS (OFF)
100

00035-014
0.01 120

000354-113
25 35 45 55 65 75 85 95 105 115 125 1k 10k 100k 1M 10M 100M 1G
TEMPERATURE (C) FREQUENCY (Hz)

Figure 11. Leakage Currents as a Function of Temperature Figure 14. Off Isolation vs. Frequency, 15 V Dual Supply

260 40
TA = 25C
35 VDD = +15V
240
tTRANSITION VSS = 15V

220 30

PIN CAPACITANCE (pF)


SWITCHING TIME (ns)

200 tON (EN) 25


DRAIN OFF

180 20

160 15

140 10

tOFF (EN)
120 5 SOURCE OFF
00035-015

100 0
15 10 5 0 5 10 15

00035-114
10 11 12 13 14 15
POWER SUPPLY (V) VS (V)

Figure 12. Switching Time vs. Dual Power Supply Figure 15. Capacitance vs. Source Voltage

300 30
VDD = +15V VDD = +15V
VSS = 15V VSS = 15V
250 tON (EN) 20 TA = 25C
SWITCHING TIME (ns)

200 10
tTRANSITION
QINJ (pC)

150 0

100 tOFF (EN) 10

50 20
00035-016

0 30
00035-115

40 20 0 20 40 60 80 100 120 15 10 5 0 5 10 15
TEMPERATURE (C) VS (V)

Figure 13. Switching Time vs. Temperature Figure 16. Charge Injection vs. Source Voltage

Rev. F | Page 9 of 20
ADG508F/ADG509F

TERMINOLOGY
VDD CD (Off)
Most positive power supply potential. Channel output capacitance for off condition.

VSS CIN
Most negative power supply potential. Digital input capacitance.

GND tON (EN)


Ground (0 V) reference. Delay time between the 50% and 90% points of the digital input
and switch on condition.
RON
Ohmic resistance between D and S. tOFF (EN)
Delay time between the 50% and 90% points of the digital input
RON Drift and switch off condition.
Percentage change in RON when temperature changes by one
degree Celsius. tTRANSITION
Delay time between the 50% and 90% points of the digital
RON inputs and the switch on condition when switching from
RON represents the difference between the RON of any two one address state to another.
channels as a percentage of the maximum RON of those two
channels. tOPEN
Off time measured between 80% points of both switches when
IS (Off) switching from one address state to another.
Source leakage current when the switch is off.
VINL
ID (Off) Maximum input voltage for Logic 0.
Drain leakage current when the switch is off.
VINH
ID, IS (On) Minimum input voltage for Logic 1.
Channel leakage current when the switch is on.
IINL (IINH)
IS (FaultPower Supplies On) Input current of the digital input.
Source leakage current when exposed to an overvoltage
condition. Off Isolation
A measure of unwanted signal coupling through an off channel.
ID (FaultPower Supplies On)
Drain leakage current when exposed to an overvoltage Charge Injection
condition. A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IS (FaultPower Supplies Off)
Source leakage current with power supplies off. IDD
Positive supply current.
VD (VS)
Analog Voltage on Terminals D, S. ISS
Negative supply current.
CS (Off)
Channel input capacitance for off condition.

Rev. F | Page 10 of 20
ADG508F/ADG509F

THEORY OF OPERATION
The ADG508F/ADG509F multiplexers are capable of withstand- During fault conditions (power supplies off), the leakage
ing overvoltages from 40 V to +55 V, irrespective of whether the current into and out of the ADG508F/ADG509F is limited to
power supplies are present or not. Each channel of the multiplexer a few microamps. This protects the multiplexer and succeeding
consists of an n-channel MOSFET, a p-channel MOSFET, and an circuitry from over stresses as well as protecting the signal
n-channel MOSFET, connected in series. When the analog input sources which drive the multiplexer. Also, the other channels
exceeds the power supplies, one of the MOSFETs will saturate of the multiplexer will be undisturbed by the overvoltage and
limiting the current. The current during a fault condition is will continue to operate normally.
determined by the load on the output. Figure 17 illustrates Q1 Q2 Q3
+55V
the channel architecture that enables these multiplexers to OVERVOLTAGE

withstand continuous overvoltages. n-CHANNEL


MOSFET

00035-017
When an analog input of VSS + 2.2 V to VDD 2.2 V (output SATURATES
VDD VSS
loaded, 1 mA) is applied to the ADG508F/ADG509F, the
multiplexer behaves as a standard multiplexer, with spec- Figure 17. +55 V Overvoltage Input to the On Channel
ifications similar to a standard multiplexer, for example,
the on-resistance is 390 maximum. However, when an Q1 Q2 Q3
40V
overvoltage is applied to the device, one of the three OVERVOLTAGE
MOSFETs saturate. n-CHANNEL
MOSFET
p-CHANNEL

00035-018
Figure 17 to Figure 20 show the conditions of the three MOSFETs IS ON
MOSFET
VSS VDD SATURATES
for the various overvoltage situations. When the analog input
applied to an on channel approaches the positive power supply Figure 18. 40 V Overvoltage on an Off Channel with
Multiplexer Power On
line, the n-channel MOSFET saturates because the voltage on
the analog input exceeds the difference between VDD and the
n-channel threshold voltage (VTN). When a voltage more nega- +55V
Q1 Q2 Q3

tive than VSS is applied to the multiplexer, the p-channel OVERVOLTAGE

MOSFET will saturate because the analog input is more n-CHANNEL

00035-019
MOSFET IS
negative than the difference between VSS and the p-channel OFF

threshold voltage (VTP). Because VTN is nominally 1.4 V and Figure 19. +55 V Overvoltage with Power Off
VTP 1.4 V, the analog input range to the multiplexer is limited
to VSS + 1.4 V to VDD 1.4 V (output open circuit) when a
15 V power supply is used. Q1 Q2 Q3
40V
OVERVOLTAGE
When the power supplies are present but the channel is off, n-CHANNEL
again either the p-channel MOSFET or one of the n-channel MOSFET IS
p-CHANNEL
ON

00035-020
MOSFETs will remain off when an overvoltage occurs. MOSFET IS
OFF
Finally, when the power supplies are off, the gate of each Figure 20. 40 V Overvoltage with Power Off
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off because the gate to source voltage applied to this
MOSFET is negative.

Rev. F | Page 11 of 20
ADG508F/ADG509F

TEST CIRCUITS
IDS

V1

ID (ON)
S D
S D
NC A
VS
VD

00035-025
00035-021
NC = NO CONNECT
RON = V1/IDS

Figure 21. On Resistance Figure 24. ID (On)

VDD VSS
VDD VSS

IS (OFF) VDD VSS


S1 VDD VSS
A S1
A
S2 D
S2 D
VS S8
S8
EN 0.8V
EN 0.8V
00035-022

VD VS VD

00035-026
Figure 22. IS (Off) Figure 25. Input Leakage Current (with Overvoltage)

0V 0V

VDD VSS
VDD VSS
0V A2 S1 A VS
VDD VSS
S1 A1
ADG508F
ID (OFF) A0
S2 D S8
A EN
S8 VD D
EN 0.8V
GND
00035-023

VS

00035-027
Figure 23. ID (Off) Figure 26. Input Leakage Current (with Power Supplies Off)

Rev. F | Page 12 of 20
ADG508F/ADG509F
VDD VSS

VDD VSS 3V
A2 S1 VS1 ADDRESS
50% 50%
VIN 50 A1 DRIVE (VIN)
S2 TO S7
A0
S8 VS8
ADG508F*
2.4V EN
D VOUT
RL CL 90%
GND
1M 35pF
VOUT

90%
*SIMILAR CONNECTION FOR ADG509F.

00035-024
tTRANSITION tTRANSITION

Figure 27. Switching Time of Multiplexer, tTRANSITION

VDD VSS 3V

ADDRESS
VDD VSS DRIVE (VIN)
A2 S1 VS
VIN 50 A1
S2 TO S7
A0
ADG508F* S8
D VOUT 80%
2.4V EN VOUT 80%
RL CL
GND
1k 35pF

tOPEN

00035-029
*SIMILAR CONNECTION FOR ADG509F.

Figure 28. Break-Before-Make Delay, tOPEN

VDD VSS 3V

ENABLE
VDD VSS DRIVE (VIN) 50% 50%
A2 S1 VS
A1 0V
S2 TO S8
A0
ADG508F* VOUT
0.9VOUT
D VOUT
EN OUTPUT
RL CL
VIN 50 GND
1k 35pF 0.1VOUT
00035-030

0V
tON (EN) tOFF (EN)

*SIMILAR CONNECTION FOR ADG509F.

Figure 29. Enable Delay, tON (EN), tOFF (EN)

Rev. F | Page 13 of 20
ADG508F/ADG509F
VDD VSS

3V
VDD VSS
A2 LOGIC
A1 INPUT (VIN)
A0
ADG508F*
0V
RS S D
VOUT
EN CL
VS
1nF
VOUT VOUT
VIN GND

QINJ = CL VOUT

00035-033
*SIMILAR CONNECTION FOR ADG509F.

Figure 30. Charge Injection

VDD VSS
0.1F 0.1F

NETWORK
ANALYZER
VDD VSS
NC 50

SA SB 50
IN
VS
D
VOUT
VIN RL
GND 50

00035-034
VOUT
OFF ISOLATION = 20 log
VS

Figure 31. Off Isolation

Rev. F | Page 14 of 20
ADG508F/ADG509F

OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)

16 9 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
8
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC
0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001-AB


CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

073106-B
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 32. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)

10.00 (0.3937)
9.80 (0.3858)

16 9
4.00 (0.1575) 6.20 (0.2441)
1
3.80 (0.1496) 8 5.80 (0.2283)

1.27 (0.0500) 0.50 (0.0197)


BSC 45
1.75 (0.0689) 0.25 (0.0098)
0.25 (0.0098) 8
1.35 (0.0531)
0.10 (0.0039) 0
COPLANARITY SEATING
0.10 0.51 (0.0201) 0.25 (0.0098) 1.27 (0.0500)
PLANE
0.31 (0.0122) 0.40 (0.0157)
0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AC


CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
060606-A

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR


REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 33. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)

Rev. F | Page 15 of 20
ADG508F/ADG509F
10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)


BSC 45
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8
0.10 (0.0039) 0
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

03-27-2007-B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 34. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)

5.10
5.00
4.90

16 9

4.50
6.40
4.40 BSC
4.30
1 8

PIN 1
1.20
MAX
0.15 0.20
0.05 0.09 0.75
0.30 8 0.60
0.65 0.19 0 0.45
SEATING
BSC PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]


(RU-16)
Dimensions shown in millimeters

Rev. F | Page 16 of 20
ADG508F/ADG509F
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADG508FBNZ 40C to +85C 16-Lead PDIP N-16
ADG508FBRN 40C to +85C 16-Lead SOIC_N R-16
ADG508FBRNZ 40C to +85C 16-Lead SOIC_N R-16
ADG508FBRNZREEL7 40C to +85C 16-Lead SOIC_N R-16
ADG508FBRWZ 40C to +85C 16-Lead SOIC_W RW-16
ADG508FBRWZ-REEL 40C to +85C 16-Lead SOIC_W RW-16
ADG508FBRUZ 40C to +85C 16-Lead TSSOP RU-16
ADG508FBRUZ-REEL7 40C to +85C 16-Lead TSSOP RU-16
ADG509FBNZ 40C to +85C 16-Lead PDIP N-16
ADG509FBRN 40C to +85C 16-Lead SOIC_N R-16
ADG509FBRNZ 40C to +85C 16-Lead SOIC_N R-16
ADG509FBRNZREEL7 40C to +85C 16-Lead SOIC_N R-16
ADG509FBRWZ 40C to +85C 16-Lead SOIC_W RW-16
ADG509FBRWZ-REEL 40C to +85C 16-Lead SOIC_W RW-16
ADG509FBRUZ 40C to +85C 16-Lead TSSOP RU-16
ADG509FBRUZ-REEL7 40C to +85C 16-Lead TSSOP RU-16
1
Z = RoHS Compliant Part.

Rev. F | Page 17 of 20
ADG508F/ADG509F

NOTES

Rev. F | Page 18 of 20
ADG508F/ADG509F

NOTES

Rev. F | Page 19 of 20
ADG508F/ADG509F

NOTES

20012011 Analog Devices, Inc. All rights reserved. Trademarks and


registered trademarks are the property of their respective owners.
D00035-0-7/11(F)

Rev. F | Page 20 of 20