Description
The figure above shows an up/down counter. If the counter is enabled, up or down counting
operation can be performed. If up/down is ‘HIGH’ ,then the counter counts up, else the counter
counts down.
iNPUT output
clear enable count clk qa, qb, qc
1 x x x 0,0,0
0 x x d2,d1,d0
0 0 x q=q
0 1 1 q = q+1
0 1 0 q = q-1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------
entity updown is
generic (n:natural:=4);
end updown;
-------------------------------------------------
begin
gate: process(clock,reset,count)
begin
if(reset='1') then
temp := "0000";
q <= std_logic_vector(temp);
q <= std_logic_vector(temp);
temp := temp-1;
q <= std_logic_vector(temp);
end if;
end behav;
Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------------------------
entity updown_tb is
end updown_tb;
-------------------------------------------------------------------------------------------------------
begin
port map(count => count_tb,clock => clock_tb,reset => reset_tb,q => q_tb);
--------------------------------------------------------------------------------------------------------
start:process
begin
for i in 0 to 30 loop
end loop;
wait;
start1:process
begin
for i in 0 to 5 loop
end loop;
wait;
start2:process
begin
for i in 0 to 5 loop
end loop;
wait;
end behav;
Ring Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------
entity ring is
generic (n:natural:=4);
end ring;
-------------------------------------------------
begin
gate: process(clock,reset)
begin
if(reset='1') then
temp := "0001";
q <= std_logic_vector(temp);
q <= std_logic_vector(temp);
end if;
end behav;
Test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------------------------
entity ring_tb is
end ring_tb;
-------------------------------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------------------------------
start:process
begin
for i in 0 to 30 loop
end loop;
wait;
start1:process
begin
for i in 0 to 5 loop
end loop;
wait;
end behav;
Johnson Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----------------------------------------------
entity johnsoncounter is
generic (n:natural:=4);
end johnsoncounter;
------------------------------------------------
begin
gate: process(clock)
begin
if(reset='1') then
temp := "0000";
q <= std_logic_vector(temp);
else
end if;
end if;
end behav;
Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------
entity johnsoncounter_tb is
end johnsoncounter_tb;
-------------------------------------------------
signal clock_tb,reset_tb:std_logic;
begin
dut: entity work.johnsoncounter
port map(clock=>clock_tb,reset=>reset_tb,q=>q_tb);
start: process
begin
clock_tb <='0';
start1: process
begin
end behav;
Barrel Shifter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------
entity barrelshifter is
generic (n:natural:=8;s:natural:=3);
shift: in std_logic);
end barrelshifter;
begin
start: process(datain,shift)
begin
if(shift='1') then
else
end if;
Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------
entity barrelshifter_tb is
end barrelshifter_tb;
signal shift_tb:std_logic;
begin
start: process
begin
temp := temp + 1;
datain_tb <= std_logic_vector(temp);
end loop;
start1: process
begin
end behav;
Binary 2 BCD
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------
entity bin2bcd is
begin
start: process(datain)
begin
temp1 := unsigned(datain);
temp := "00000";
for i in 0 to 3 loop
temp := temp + 3;
temp := (temp+temp)+("000"&temp1(3));
else
temp := (temp+temp)+("000"&temp1(3));
end if;
end loop;
end behav;
Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----------------------------------------
entity bin2bcd_tb is
end bin2bcd_tb;
-----------------------------------------
begin
name:entity work.bin2bcd
start: process
begin
for i in 1 to 50 loop
temp := temp+1;
wait for 5 ns;
end loop;
wait;
end behav;
Gray2excess3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------
entity gray2excess3 is
);
end gray2excess3;
begin
start: process(datain)
begin
temp(3) := (datain(3));
else
end if;
end behav;
Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----------------------------------------
entity gray2excess3_tb is
end gray2excess3_tb;
-----------------------------------------
begin
name:entity work.gray2excess3
start: process
begin
for i in 0 to 50 loop
temp:= temp+1;
end loop;
wait;
end behav;
Excess2gray
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------
entity xs32gray is
);
end xs32gray;
begin
start: process(datain)
begin
temp := unsigned(datain);
temp := temp-3;
end behav;
Test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----------------------------------------
entity xs32gray_tb is
end xs32gray_tb;
-----------------------------------------
begin
name:entity work.xs32gray
start: process
begin
for i in 0 to 11 loop
temp:= temp+1;
wait;
end behav;