CHANDRA BIHARI GOYAL

33# Reddy PG, Near Novel Business Center

BTM, 1st Layout Bangalore-560068
Mobile: +91-7816853417
Email-id: goyalchandra1992@gmail.com

Career Objective:
Looking for a responsible position as a VLSI design engineer with a view to utilize and enhance my skills and
experience towards professional growth.

Core Competency
Experience of designing blocks & sub-systems like PLLs, ADCs, DACs, LVDS, CDRs,VCOs, OpAmps,
Comparators, Voltage References etc. Experience of designs in 40nm, 45nm, 90nm, 130nm, 0.18um
Experience
Presently working as a Analog Layout Trainee at Digicomm Semiconductor Private Limited
Block #1-Analog
Project Title Block Name Phase Lock Loop(PLL)
Technology 40nm/28nm
Organization
Digicomm Semiconductor Private Limited, Bangalore
name
Duration May 2016 to till now
Responsibilities:- Develop layout from schematic (PFD, Charge Pump, Divider), floor plan, placement, routing
Clean DRC and LVS.
Minimizing parasitic capacitances and employing EM protection circuits.
Tools Used Stablesoft Slam Plus, Cadence Virtuoso

Block #2-Analog
Project Title Block Name Two Stage Operational Amplifier
Technology 40nm/28nm
Organization
Digicomm Semiconductor Private Limited, Bangalore
name
Matching the current mirror and differential pair.
Description Parasitic should match input and output signal path.
Clean DRC and LVS
Tools Used Stablesoft Slam Plus, Cadence Virtuoso

Projects PG level:

Project Title Design of Multistage Noise Shaping Sigma Delta ADC.

A first-order 1-bit sigma-delta (-) analog-to-digital converter is designed and
simulated using Cadence Virtuoso with 90nm CMOS process technology. We cascaded
Description
the three stages of Sigma delta ADC which is useful for the noise shaping application

Tools Used Cadence Virtuoso

Project Title Sine and cosine generator using cordic algorithm implemented in Asic.
Objective of this paper is to generate sine and cosine function using CORDIC algorithm.
Description CORDIC comes fast when to evaluate DSP algorithms uses basic function such as addition,
multiplication, trigonometric functions etc.
Tools Used Cadence NC launch, Cadence RC launch, Cadence SOC Encounter.
 Project Title ASIC implementation of 8-bit Adding-CPU processor design.
In this project implementation involving arithmetic, data path and control path instruction in
Description verilog code and performing functional verification, timing analysis and carried out RTL to
GDS-II physical design flow by using Cadence Encounter.
Tools Used Cadence NC launch, Cadence RC launch, Cadence SOC Encounter.

Technical Skills:
Languages / Scripting
Hardware Tools / Utilities
Operating Systems
Verilog HDL, Basic of PERL and TCL scripting.
Calibre, Cadence Encounter, Cadence Virtuoso, Prime-time, Model-Sim,
Xilinx design ISE 14.3, Cadence RC launch, Cadence NC launch, Matlab.
Windows, Linux Ubantu

Basic Academic Credentials:

Qualification Board / University Year of passing Percentage / CGPA

M.Tech. Vellore Institute of Technology,Vellore
2016 8.5
(VLSI Design)
Rajiv Gandhi Proudyogiki
B.E. (ECE) Vishwavidyalaya ,Bhopal 2012 8.3

Govt. Boys HS School Sabalgarh,

H.S.C. 2008 82%
Mp board
Govt. Boys No.2 Jeenfield, Sabalgarh,
S.S.C. 2006 80%
Mp board

Research Paper Publications:

Published IEEE Conference on SINE AND COSINE Generator Using CORDIC Algorithm Implementation in ASIC
IEEE SPONSERED THIRD INTERNATIONAL CONFERENCE ON (ICIIECS16)

Personal Details:
Fathers name : Ram Kumar Goyal
Date of Birth : 05/07/1992
Nationality : Indian
Languages Known : English, Hindi
Hobbies : listening song, Cricket
:

Extra Curricular Activities & Achievements:

Did 18 days certification program on C, C++ & CORE JAVA, from ABV- IIITM College Gwalior.
Attended Xix day workshop on RTL to GDSII FOR IC DESIGN at VIT University Organized by
Department of Micro & Nano electronics
I Participated the workshop held on IIT-BOMBAY Techfest in 2012
Attended One day workshop on RTL DESIGN AND FUNCTIONAL Verification at VIT
University Organized by MAVEN SILICON

Declaration:
I hereby declare that the above given information and details are true to the best of my knowledge.

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